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? 2004 microchip technology inc. preliminary ds39646b pic18f8722 family data sheet 64/80-pin, 1-mbit, enhanced flash microcontrollers with 10-bit a/d and nanowatt technology
ds39646b-page ii preliminary ? 2004 microchip technology inc. information contained in this publication regarding device applications and the like is provi ded only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. microchip makes no representations or war- ranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, migratable memory, mxdev, mxlab, picmaster, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, rflab, rfpicdem, select mode, smart serial, smarttel and total endurance are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2004, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
? 2004 microchip technology inc. preliminary ds39646b-page 1 pic18f8722 family peripheral highlights: two master synchronous serial port (mssp) modules supporting 2/3/4-wire spi? (all 4 modes) and i 2 c? master and slave modes two capture/compare/pwm (ccp) modules three enhanced capture/compare/pwm (eccp) modules: - one, two or four pwm outputs - selectable polarity - programmable dead time - auto-shutdown and auto-restart two enhanced addressable usart modules: - supports rs-485, rs-232 and lin 1.2 - auto-wake-up on start bit - auto-baud detect 10-bit, up to 16-channel analog-to-digital converter module (a/d) - auto-acquisition capability - conversion available during sleep dual analog comparators with input multiplexing high-current sink/source 25 ma/25 ma four programmable external interrupts four input change interrupts external memory interface (pic18f8527/8622/8627/8722 only): address capability of up to 2 mbytes 8-bit or 16-bit interface 8, 12, 16 and 20-bit address modes power-managed modes: run: cpu on, peripherals on idle: cpu off, peripherals on sleep: cpu off, peripherals off idle mode currents down to 15 a typical sleep current down to 0.2 a typical timer1 oscillator: 1.8 a, 32 khz, 2v watchdog timer: 2.1 a special microcontroller features: c compiler optimized architecture: - optional extended instruction set designed to optimize re-entrant code 100,000 erase/write cycle enhanced flash program memory typical 1,000,000 erase/write cycle data eeprom memory typical flash/data eeprom retention: 100 years typical self-programmable under software control priority levels for interrupts 8 x 8 single-cycle hardware multiplier extended watchdog timer (wdt): - programmable period from 4 ms to 131s single-supply in-circuit serial programming? (icsp?) via two pins in-circuit debug (icd) via two pins wide operating voltage range: 2.0v to 5.5v fail-safe clock monitor two-speed oscillator start-up nanowatt technology device program memory data memory i/o 10-bit a/d (ch) ccp/ eccp (pwm) mssp eusart comparators timers 8/16-bit external bus flash (bytes) # single-word instructions sram (bytes) eeprom (bytes) spi? master i 2 c? pic18f6527 48k 24576 3936 1024 54 12 2/3 2 y y 2 2 2/3 n pic18f6622 64k 32768 3936 1024 54 12 2/3 2 y y 2 2 2/3 n pic18f6627 96k 49152 3936 1024 54 12 2/3 2 y y 2 2 2/3 n pic18f6722 128k 65536 3936 1024 54 12 2/3 2 y y 2 2 2/3 n pic18f8527 48k 24576 3936 1024 70 16 2/3 2 y y 2 2 2/3 y pic18f8622 64k 32768 3936 1024 70 16 2/3 2 y y 2 2 2/3 y pic18f8627 96k 49152 3936 1024 70 16 2/3 2 y y 2 2 2/3 y pic18f8722 128k 65536 3936 1024 70 16 2/3 2 y y 2 2 2/3 y 64/80-pin, 1-mbit, enhanced flash microcontrollers with 10-bit a/d and nanowatt technology
pic18f8722 family ds39646b-page 2 preliminary ? 2004 microchip technology inc. pin diagrams note 1: the eccp2/p2a pin placement is determined by the ccp2mx configuration bit. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 38 37 36 35 34 33 50 49 17 18 19 20 21 22 23 24 25 26 re2/cs /p2b re3/p3c re4/p3b re5/p1c re6/p1b re7/eccp2 (1) /p2a (1) rd0/psp0 v dd v ss rd1/psp1 rd2/psp2 rd3/psp3 rd4/psp4/sdo2 rd5/psp5/sdi2/sda2 rd6/psp6/sck2/scl2 rd7/psp7/ss2 re1/wr /p2c re0/rd /p2d rg0/eccp3/p3a rg1/tx2/ck2 rg2/rx2/dt2 rg3/ccp4/p3d rg5/mclr /v pp rg4/ccp5/p1d v ss v dd rf7/ss1 rf6/an11 rf5/an10/cv ref rf4/an9 rf3/an8 rf2/an7/c1out rb0/int0 rb1/int1 rb2/int2 rb3/int3 rb4/kbi0 rb5/kbi1/pgm rb6/kbi2/pgc v ss osc2/clko/ra6 osc1/clki/ra7 v dd rb7/kbi3/pgd rc4/sdi1/sda1 rc3/sck1/scl1 rc2/eccp1/p1a rf0/an5 rf1/an6/c2out av dd av ss ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 v ss v dd ra4/t0cki ra5/an4/hlvdin rc1/t1osi/eccp2 (1) /p2a (1) rc0/t1oso/t13cki rc7/rx1/dt1 rc6/tx1/ck1 rc5/sdo1 15 16 31 40 39 27 28 29 30 32 48 47 46 45 44 43 42 41 54 53 52 51 58 57 56 55 60 59 64 63 62 61 64-pin tqfp pic18f6527 pic18f6622 pic18f6627 pic18f6722
? 2004 microchip technology inc. preliminary ds39646b-page 3 pic18f8722 family pin diagrams (continued) pic18f8527 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 re2/ad10/cs /p2b re3/ad11/p3c (2) re4/ad12/p3b (2) re5/ad13/p1c (2) re6/ad14/p1b (2) re7/ad15/eccp2 (1) /p2a (1) rd0/ad0/psp0 v dd v ss rd1/ad1/psp1 rd2/ad2/psp2 rd3/ad3/psp3 rd4/ad4/psp4/sdo2 rd5/ad5/psp5/sdi2/sda2 rd6/ad6/psp6/sck2/scl2 rd7/ad7/psp7/ss2 re1/ad9/wr /p2c re0/ad8/rd /p2d rg0/eccp3/p3a rg1/tx2/ck2 rg2/rx2/dt2 rg3/ccp4/p3d rg5/mclr /v pp rg4/ccp5/p1d v ss v dd rf7/ss1 rb0/int0 rb1/int1 rb2/int2 rb3/int3/eccp2 (1) /p2a (1) rb4/kbi0 rb5/kbi1/pgm rb6/kbi2/pgc v ss osc2/clko/ra6 osc1/clki/ra7 v dd rb7/kbi3/pgd rc4/sdi1/sda1 rc3/sck1/scl1 rc2/eccp1/p1a rf0/an5 rf1/an6/c2out av dd av ss ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 v ss v dd ra4/t0cki ra5/an4/hlvdin rc1/t1osi/eccp2 (1) /p2a (1) rc0/t1oso/t13cki rc7/rx1/dt1 rc6/tx1/ck1 rc5/sdo1 rj0/ale rj1/oe rh1/a17 rh0/a16 1 2 rh2/a18 rh3/a19 17 18 rh7/an15/p1b (2) rh6/an14/p1c (2) rh5/an13/p3b (2) rh4/an12/p3c (2) rj5/ce rj4/ba0 37 rj7/ub rj6/lb 50 49 rj2/wrl rj3/wrh 19 20 33 34 35 36 38 58 57 56 55 54 53 52 51 60 59 68 67 66 65 72 71 70 69 74 73 78 77 76 75 79 80 80-pin tqfp note 1: the eccp2/p2a pin placement is determined by the ccp2mx configuration bit and processor mode settings. 2: p1b, p1c, p3b and p3c pin placement is determined by the eccpmx configuration bit. rf5/an10/cv ref rf4/an9 rf3/an8 rf2/an7/c1out rf6/an11 pic18f8622 pic18f8627 pic18f8722
pic18f8722 family ds39646b-page 4 preliminary ? 2004 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ............................................................. 7 2.0 oscillator configurations ................................................................................................... ......................................................... 31 3.0 power-managed modes ......................................................................................................... .................................................... 41 4.0 reset ....................................................................................................................... ................................................................... 49 5.0 memory organization ......................................................................................................... ........................................................ 63 6.0 flash program memory........................................................................................................ ...................................................... 87 7.0 external memory bus ......................................................................................................... ........................................................ 97 8.0 data eeprom memory .......................................................................................................... ................................................. 111 9.0 8 x 8 hardware multiplier................................................................................................... ....................................................... 117 10.0 interrupts ................................................................................................................. ................................................................. 119 11.0 i/o ports .................................................................................................................. ................................................................. 135 12.0 timer0 module .............................................................................................................. ........................................................... 161 13.0 timer1 module .............................................................................................................. ........................................................... 165 14.0 timer2 module .............................................................................................................. ........................................................... 171 15.0 timer3 module .............................................................................................................. ........................................................... 173 16.0 timer4 module .............................................................................................................. ........................................................... 177 17.0 capture/compare/pwm (ccp) modules .......................................................................................... ....................................... 179 18.0 enhanced capture/compare/pwm (eccp) module................................................................................. ............................... 187 19.0 master synchronous serial port (mssp) module ............................................................................... ..................................... 205 20.0 enhanced universal synchronous receiver tr ansmitter (eusart) ............................................................... ........................ 247 21.0 10-bit analog-to-digital converter (a/d) module ............................................................................ ......................................... 271 22.0 comparator module.......................................................................................................... ........................................................ 281 23.0 comparator voltage reference module ........................................................................................ ........................................... 287 24.0 high/low-voltage detect (hlvd)............................................................................................. ................................................ 291 25.0 special features of the cpu ................................................................................................ .................................................... 297 26.0 instruction set summary .................................................................................................... ...................................................... 321 27.0 development support........................................................................................................ ....................................................... 371 28.0 electrical characteristics ................................................................................................. ......................................................... 377 29.0 dc and ac characteristics graphs and tables ................................................................................ ....................................... 421 30.0 packaging information...................................................................................................... ........................................................ 423 appendix a: revision history................................................................................................... .......................................................... 427 appendix b: device differences................................................................................................. ........................................................ 427 appendix c: conversion considerations .......................................................................................... ................................................. 428 appendix d: migration from baseline to enhanced devices........................................................................ ..................................... 428 appendix e: migration from mid-range to enhanced devices ....................................................................... .................................. 429 appendix f: migration from high-end to enhanced devices........................................................................ .................................... 429 index .......................................................................................................................... ........................................................................ 431 on-line support................................................................................................................ ................................................................. 443 systems information and upgrade hot line ....................................................................................... ............................................... 443 reader response ................................................................................................................ .............................................................. 444 pic18f8722 family product identification system................................................................................ ............................................ 445
? 2004 microchip technology inc. preliminary ds39646b-page 5 pic18f8722 family to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@.microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/doc umentation issues become known to us, we will publis h an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particul ar device, please check with one of the following: microchip?s worldwide web site; http://www.microchip.com your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
pic18f8722 family ds39646b-page 6 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39646b-page 7 pic18f8722 family 1.0 device overview this document contains device specific information for the following devices: this family offers the advantages of all pic18 micro- controllers ? namely, high computational performance at an economical price ? with the addition of high- endurance, enhanced flash program memory. on top of these features, the pic18f8722 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive applications. 1.1 new core features 1.1.1 nanowatt technology all of the devices in the pic18f8722 family incorporate a range of features that can significantly reduce power consumption during operation. key items include: alternate run modes: by clocking the controller from the timer1 source or the internal oscillator block, power consumption during code execution can be significantly reduced. multiple idle modes: the controller can also run with its cpu core disabled but the peripherals still active. in these states, power consumption can be reduced even further. on-the-fly mode switching: the power- managed modes are invoked by user code during operation, allowing the user to incorporate power- saving ideas into their application?s software design. low consumption in key modules: the power requirements for both timer1 and the watchdog timer are minimized. see section 28.0 ?electrical characteristics? for values. 1.1.2 expanded memory the pic18f8722 family provides ample room for application code and includes members with 48, 64, 96 or 128 kbytes of code space. data ram and data eeprom: the pic18f8722 family also provides plenty of room for application data. the devices have 3936 bytes of data ram, as well as 1024 bytes of data eeprom, for long term retention of nonvolatile data. memory endurance: the enhanced flash cells for both program memory and data eeprom are rated to last for many thousands of erase/write cycles, up to 100,000 for program memory and 1,000,000 for eeprom. data retention without refresh is conservatively estimated to be greater than 40 years. 1.1.3 multiple oscillator options and features all of the devices in the pic18f8722 family offer ten different oscillator options, allowing users a wide range of choices in developing application hardware. these include: four crystal modes, using crystals or ceramic resonators two external clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general i/o) two external rc oscillator modes with the same pin options as the external clock modes an internal oscillator block which provides an 8 mhz clock and an intrc source (approxi- mately 31 khz), as well as a range of 6 user selectable clock frequencies, between 125 khz to 4 mhz, for a total of 8 clock frequencies. this option frees the two oscillator pins for use as additional general purpose i/o. a phase lock loop (pll) frequency multiplier, available to both the high-speed crystal and inter- nal oscillator modes, which allows clock speeds of up to 40 mhz. used with the internal oscillator, the pll gives users a complete selection of clock speeds, from 31 khz to 32 mhz ? all without using an external crystal or clock circuit. pic18f6527 pic18lf6527 pic18f6622 pic18lf6622 pic18f6627 pic18lf6627 pic18f6722 pic18lf6722 pic18f8527 pic18lf8527 pic18f8622 pic18lf8622 pic18f8627 pic18lf8627 pic18f8722 pic18lf8722
pic18f8722 family ds39646b-page 8 preliminary ? 2004 microchip technology inc. besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: fail-safe clock monitor: this option constantly monitors the main clock source against a reference signal provided by the internal oscillator. if a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued low-speed operation or a safe application shutdown. two-speed start-up: this option allows the internal oscillator to serve as the clock source from power-on reset, or wake-up from sleep mode, until the primary clock source is available. 1.1.4 external memory interface in the unlikely event that 128 kbytes of program memory is inadequate for an application, the pic18f8527/8622/8627/8722 members of the family also implement an external memory interface. this allows the controller?s internal program counter to address a memory space of up to 2 mbytes, permitting a level of data access that few 8-bit devices can claim. with the addition of new operating modes, the external memory interface offers many new options, including: operating the microcontroller entirely from external memory using combinations of on-chip and external memory, up to the 2-mbyte limit using external flash memory for reprogrammable application code or large data tables using external ram devices for storing large amounts of variable data 1.1.5 easy migration regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. the consistent pinout scheme used throughout the entire family also aids in migrating to the next larger device. this is true when moving between the 64-pin members, between the 80-pin members, or even jumping from 64-pin to 80-pin devices. 1.2 other special features communications: the pic18f8722 family incorporates a range of serial communication peripherals, including 2 independent enhanced usarts and 2 master ssp modules capable of both spi and i 2 c (master and slave) modes of operation. also, one of the general purpose i/o ports can be reconfigured as an 8-bit parallel slave port for direct processor-to-processor communications. ccp modules: all devices in the family incorporate two capture/compare/pwm (ccp) modules and three enhanced ccp (eccp) modules to maximize flexibility in control applications. up to four different time bases may be used to perform several different operations at once. each of the three eccp modules offer up to four pwm outputs, allowing for a total of 12 pwms. the eccps also offer many beneficial features, including polarity selection, programmable dead-time, auto-shutdown and restart and half-bridge and full-bridge output modes. self-programmability: these devices can write to their own program memory spaces under internal software control. by using a bootloader routine located in the protected boot block at the top of program memory, it becomes possible to create an application that can update itself in the field. extended instruction set: the pic18f8722 family introduces an optional extension to the pic18 instruction set, which adds 8 new instruc- tions and an indexed addressing mode. this extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as c. 10-bit a/d converter: this module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. extended watchdog timer (wdt): this enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. see section 28.0 ?electrical characteristics? for time-out periods.
? 2004 microchip technology inc. preliminary ds39646b-page 9 pic18f8722 family 1.3 details on individual family members devices in the pic18f8722 family are available in 64-pin and 80-pin packages. block diagrams for the two groups are shown in figure 1-1 and figure 1-2. the devices are differentiated from each other in five ways: 1. flash program memory (48 kbytes for pic18f6527/8527 devices, 64 kbytes for pic18f6622/8622 devices, 96 kbytes for pic18f6627/8627 devices and 128 kbytes for pic18f6722/8722). 2. a/d channels (12 for 64-pin devices, 16 for 80-pin devices). 3. i/o ports (7 bidirectional ports on 64-pin devices, 9 bidirectional ports on 80-pin devices). 4. external memory bus, configurable for 8 and 16-bit operation, is available on pic18f8527/ 8622/8627/8722 devices. all other features for devices in this family are identical. these are summarized in table 1-2 and table 1-2. the pinouts for all devices are listed in table 1-3 and table 1-4. like all microchip pic18 devices, members of the pic18f8722 family are available as both standard and low-voltage devices. standard devices with enhanced flash memory, designated with an ?f? in the part number (such as pic18 f 6627), accommodate an operating v dd range of 4.2v to 5.5v. low-voltage parts, designated by ?lf? (such as pic18 lf 6627), function over an extended v dd range of 2.0v to 5.5v. table 1-1: device features (pic18f6527/6622/6627/6722) features pic18f6527 pic18f6622 pic18f6627 pic18f6722 operating frequency dc ? 40 mhz dc ? 40 mhz dc ? 40 mhz dc ? 40 mhz program memory (bytes) 48k 64k 96k 128k program memory (instructions) 24576 32768 49152 65536 data memory (bytes) 3936 3936 3936 3936 data eeprom memory (bytes) 1024 1024 1024 1024 interrupt sources 28282828 i/o ports ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g timers 5 5 5 5 capture/compare/pwm modules 2222 enhanced capture/compare/ pwm modules 3333 enhanced usart 2 2 2 2 serial communications mssp, enhanced usart mssp, enhanced usart mssp, enhanced usart mssp, enhanced usart parallel communications (psp) yes yes yes yes 10-bit analog-to-digital module 12 input channels 12 input channels 12 input channels 12 input channels resets (and delays) por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt programmable high/low-voltage detect yes yes yes yes programmable brown-out reset yes yes yes yes instruction set 75 instructions; 83 with extended instruction set enabled 75 instructions; 83 with extended instruction set enabled 75 instructions; 83 with extended instruction set enabled 75 instructions; 83 with extended instruction set enabled packages 64-pin tqfp 64-pin tqfp 64-pin tqfp 64-pin tqfp
pic18f8722 family ds39646b-page 10 preliminary ? 2004 microchip technology inc. table 1-2: device features (pic18f8527/8622/8627/8722) features pic18f8527 pic18f8622 pic18f8627 pic18f8722 operating frequency dc ? 40 mhz dc ? 40 mhz dc ? 40 mhz dc ? 40 mhz program memory (bytes) 48k 64k 96k 128k program memory (instructions) 24576 32768 49152 65536 data memory (bytes) 3936 3936 3936 3936 data eeprom memory (bytes) 1024 1024 1024 1024 interrupt sources 29 29 29 29 i/o ports ports a, b, c, d, e, f, g, h , j ports a, b, c, d, e, f, g, h, j ports a, b, c, d, e, f, g, h , j ports a, b, c, d, e, f, g, h, j timers 5 5 5 5 capture/compare/pwm modules 2222 enhanced capture/compare/ pwm modules 3333 enhanced usart 2 2 2 2 serial communications mssp, enhanced usart mssp, enhanced usart mssp, enhanced usart mssp, enhanced usart parallel communications (psp) yes yes yes yes 10-bit analog-to-digital module 16 input channels 16 input channels 16 input channels 16 input channels resets (and delays) por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt programmable high/low-voltage detect yes yes yes yes programmable brown-out reset yes yes yes yes instruction set 75 instructions; 83 with extended instruction set enabled 75 instructions; 83 with extended instruction set enabled 75 instructions; 83 with extended instruction set enabled 75 instructions; 83 with extended instruction set enabled packages 80-pin tqfp 80-pin tqfp 80-pin tqfp 80-pin tqfp
? 2004 microchip technology inc. preliminary ds39646b-page 11 pic18f8722 family figure 1-1: pic18f6527/6622/6627/6722 (64-pin) block diagram instruction decode and control porta data latch data memory (3.9 kbytes) address latch data address<12> 12 access bsr fsr0 fsr1 fsr2 inc/dec logic address 4 12 4 pch pcl pclath 8 31 level stack program counter prodl prodh 8 x 8 multiply 8 bitop 8 8 alu<8> address latch program memory (48/64/96/128 data latch 20 8 8 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 3 pclatu pcu note 1: see table 1-3 for i/o port pin descriptions. 2: rg5 is only available when m clr functionality is disabled. 3: osc1/clki and osc2/clko are only available in select oscillator modes and when these pins are not being used as digital i/o. refer to section 2.0 ?oscillator configurations? for additional information. eusart1 comparators mssp1 timer2 timer1 timer3 timer0 hlvd eccp1 bor adc 10-bit w instruction bus <16> stkptr bank 8 state machine control signals decode 8 8 power-up timer oscillator start-up timer power-on reset watchdog timer osc1 (3) osc2 (3) v dd , brown-out reset internal oscillator fail-safe clock monitor precision reference band gap v ss m clr (2) block intrc oscillator 8 mhz oscillator single-supply programming in-circuit debugger t1osi t1oso eusart2 eccp2 rom latch eccp3 mssp2 ccp4 ccp5 portc portd porte portf portg ra0:ra7 (1) rc0:rc7 (1) rd0:rd7 (1) re0:re7 (1) rf0:rf7 (1) rg0:rg5 (1) portb rb0:rb7 (1) timer4 kbytes)
pic18f8722 family ds39646b-page 12 preliminary ? 2004 microchip technology inc. figure 1-2: pic18f8527/8622/8627/8722 (80-pin) block diagram prodl prodh 8 x 8 multiply 8 bitop 8 8 alu<8> 8 8 3 w 8 8 8 power-up timer oscillator start-up timer power-on reset watchdog timer osc1 (3) osc2 (3) v dd , brown-out reset internal oscillator fail-safe clock monitor precision reference band gap v ss mclr (2) block intrc oscillator 8 mhz oscillator single-supply programming in-circuit debugger t1osi t1oso instruction decode & control data latch data memory (3.9 kbytes) address latch data address<12> 12 access bsr fsr0 fsr1 fsr2 inc/dec logic address 4124 pch pcl pclath 8 31 level stack program counter address latch program memory (48/64/96/128 data latch 20 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 rom latch pclatu pcu instruction bus <16> stkptr bank state machine control signals decode system bus interface ad15:ad0, a19:a16 (multiplexed with portd, porte and porth) porta portc portd porte portf portg ra0:ra7 (1) rc0:rc7 (1) rd0:rd7 (1) re0:re7 (1) rf0:rf7 (1) rg0:rg5 (1) portb rb0:rb7 (1) porth rh0:rh7 (1) portj rj0:rj7 (1) eusart1 comparators mssp1 timer2 timer1 timer3 timer0 hlvd eccp1 bor adc 10-bit eusart2 eccp2 eccp3 mssp2 ccp4 ccp5 timer4 note 1: see table 1-4 for i/o port pin descriptions. 2: rg5 is only available when mclr functionality is disabled. 3: osc1/clki and osc2/clko are only available in select oscillator modes and when these pins are not being used as digital i/o. refer to section 2.0 ?oscillator configurations? for additional information. kbytes)
? 2004 microchip technology inc. preliminary ds39646b-page 13 pic18f8722 family table 1-3: pic18f6527/6622/6627/6722 pinout i/o descriptions pin name pin number pin type buffer type description tqfp rg5/mclr /v pp rg5 mclr v pp 7 i i p st st master clear (input) or programming voltage (input). digital input. master clear (reset) input. this pin is an active-low reset to the device. programming voltage input. osc1/clki/ra7 osc1 clki ra7 39 i i i/o st cmos ttl oscillator crystal or external clock input. oscillator crystal input or external clock source input. st buffer when configured in rc mode, cmos otherwise. external clock source input. always associated with pin function osc1. (see related osc1/clki, osc2/clko pins.) general purpose i/o pin. osc2/clko/ra6 osc2 clko ra6 40 o o i/o ? ? ttl oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clko, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. general purpose i/o pin. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c? = i 2 c/smbus input buffer note 1: default assignment for eccp2 when configuration bit ccp2mx is set. 2: alternate assignment for eccp2 when configuration bit ccp2mx is cleared.
pic18f8722 family ds39646b-page 14 preliminary ? 2004 microchip technology inc. porta is a bidirectional i/o port. ra0/an0 ra0 an0 24 i/o i ttl analog digital i/o. analog input 0. ra1/an1 ra1 an1 23 i/o i ttl analog digital i/o. analog input 1. ra2/an2/v ref - ra2 an2 v ref - 22 i/o i i ttl analog analog digital i/o. analog input 2. a/d reference voltage (low) input. ra3/an3/v ref + ra3 an3 v ref + 21 i/o i i ttl analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki ra4 t0cki 28 i/o i st st digital i/o. timer0 external clock input. ra5/an4/hlvdin ra5 an4 hlvdin 27 i/o i i ttl analog analog digital i/o. analog input 4. high/low-voltage detect input. ra6 see the osc2/clko/ra6 pin. ra7 see the osc1/clki/ra7 pin. table 1-3: pic18f6527/6622/6627/6722 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c? = i 2 c/smbus input buffer note 1: default assignment for eccp2 when configuration bit ccp2mx is set. 2: alternate assignment for eccp2 when configuration bit ccp2mx is cleared.
? 2004 microchip technology inc. preliminary ds39646b-page 15 pic18f8722 family portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0/flt0 rb0 int0 flt0 48 i/o i i ttl st st digital i/o. external interrupt 0. pwm fault input for eccpx. rb1/int1 rb1 int1 47 i/o i ttl st digital i/o. external interrupt 1. rb2/int2 rb2 int2 46 i/o i ttl st digital i/o. external interrupt 2. rb3/int3 rb3 int3 45 i/o i ttl st digital i/o. external interrupt 3. rb4/kbi0 rb4 kbi0 44 i/o i ttl ttl digital i/o. interrupt-on-change pin. rb5/kbi1/pgm rb5 kbi1 pgm 43 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. low-voltage icsp? programming enable pin. rb6/kbi2/pgc rb6 kbi2 pgc 42 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming clock pin. rb7/kbi3/pgd rb7 kbi3 pgd 37 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming data pin. table 1-3: pic18f6527/6622/6627/6722 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c? = i 2 c/smbus input buffer note 1: default assignment for eccp2 when configuration bit ccp2mx is set. 2: alternate assignment for eccp2 when configuration bit ccp2mx is cleared.
pic18f8722 family ds39646b-page 16 preliminary ? 2004 microchip technology inc. portc is a bidirectional i/o port. rc0/t1oso/t13cki rc0 t1oso t13cki 30 i/o o i st ? st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi/eccp2/p2a rc1 t1osi eccp2 (1) p2a (1) 29 i/o i i/o o st cmos st ? digital i/o. timer1 oscillator input. enhanced capture 2 input/compare 2 output/ pwm 2 output. eccp2 pwm output a. rc2/eccp1/p1a rc2 eccp1 p1a 33 i/o i/o o st st ? digital i/o. enhanced capture 1 input/compare 1 output/ pwm 1 output. eccp1 pwm output a. rc3/sck1/scl1 rc3 sck1 scl1 34 i/o i/o i/o st st st digital i/o. synchronous serial clock input/output for spi? mode. synchronous serial clock input/output for i 2 c? mode. rc4/sdi1/sda1 rc4 sdi1 sda1 35 i/o i i/o st st st digital i/o. spi data in. i 2 c data i/o. rc5/sdo1 rc5 sdo1 36 i/o o st ? digital i/o. spi data out. rc6/tx1/ck1 rc6 tx1 ck1 31 i/o o i/o st ? st digital i/o. eusart1 asynchronous transmit. eusart1 synchronous clock (see related rx1/dt1). rc7/rx1/dt1 rc7 rx1 dt1 32 i/o i i/o st st st digital i/o. eusart1 asynchronous receive. eusart1 synchronous data (see related tx1/ck1). table 1-3: pic18f6527/6622/6627/6722 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c? = i 2 c/smbus input buffer note 1: default assignment for eccp2 when configuration bit ccp2mx is set. 2: alternate assignment for eccp2 when configuration bit ccp2mx is cleared.
? 2004 microchip technology inc. preliminary ds39646b-page 17 pic18f8722 family portd is a bidirectional i/o port. rd0/psp0 rd0 psp0 58 i/o i/o st ttl digital i/o. parallel slave port data. rd1/psp1 rd1 psp1 55 i/o i/o st ttl digital i/o. parallel slave port data. rd2/psp2 rd2 psp2 54 i/o i/o st ttl digital i/o. parallel slave port data. rd3/psp3 rd3 psp3 53 i/o i/o st ttl digital i/o. parallel slave port data. rd4/psp4/sdo2 rd4 psp4 sdo2 52 i/o i/o o st ttl ? digital i/o. parallel slave port data. spi data out. rd5/psp5/sdi2/sda2 rd5 psp5 sdi2 sda2 51 i/o i/o i i/o st ttl st i 2 c/smb digital i/o. parallel slave port data. spi? data in. i 2 c? data i/o. rd6/psp6/sck2/scl2 rd6 psp6 sck2 scl2 50 i/o i/o i/o i/o st ttl st i 2 c/smb digital i/o. parallel slave port data. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c mode. rd7/psp7/ss2 rd7 psp7 ss2 49 i/o i/o i st ttl ttl digital i/o. parallel slave port data. spi slave select input. table 1-3: pic18f6527/6622/6627/6722 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c? = i 2 c/smbus input buffer note 1: default assignment for eccp2 when configuration bit ccp2mx is set. 2: alternate assignment for eccp2 when configuration bit ccp2mx is cleared.
pic18f8722 family ds39646b-page 18 preliminary ? 2004 microchip technology inc. porte is a bidirectional i/o port. re0/rd /p2d re0 rd p2d 2 i/o i o st ttl ? digital i/o. read control for parallel slave port. eccp2 pwm output d. re1/wr /p2c re1 wr p2c 1 i/o i o st ttl ? digital i/o. write control for parallel slave port. eccp2 pwm output c. re2/cs /p2b re2 cs p2b 64 i/o i o st ttl ? digital i/o. chip select control for parallel slave port. eccp2 pwm output b. re3/p3c re3 p3c 63 i/o o st ? digital i/o. eccp3 pwm output c. re4/p3b re4 p3b 62 i/o o st ? digital i/o. eccp3 pwm output b. re5/p1c re5 p1c 61 i/o o st ? digital i/o. eccp1 pwm output c. re6/p1b re6 p1b 60 i/o o st ? digital i/o. eccp1 pwm output b. re7/eccp2/p2a re7 eccp2 (2) p2a (2) 59 i/o i/o o st st ? digital i/o. enhanced capture 2 input/compare 2 output/ pwm 2 output. eccp2 pwm output a. table 1-3: pic18f6527/6622/6627/6722 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c? = i 2 c/smbus input buffer note 1: default assignment for eccp2 when configuration bit ccp2mx is set. 2: alternate assignment for eccp2 when configuration bit ccp2mx is cleared.
? 2004 microchip technology inc. preliminary ds39646b-page 19 pic18f8722 family portf is a bidirectional i/o port. rf0/an5 rf0 an5 18 i/o i st analog digital i/o. analog input 5. rf1/an6/c2out rf1 an6 c2out 17 i/o i o st analog ? digital i/o. analog input 6. comparator 2 output. rf2/an7/c1out rf2 an7 c1out 16 i/o i o st analog ? digital i/o. analog input 7. comparator 1 output. rf3/an8 rf3 an8 15 i/o i st analog digital i/o. analog input 8. rf4/an9 rf4 an9 14 i/o i st analog digital i/o. analog input 9. rf5/an10/cv ref rf5 an10 cv ref 13 i/o i o st analog analog digital i/o. analog input 10. comparator reference voltage output. rf6/an11 rf6 an11 12 i/o i st analog digital i/o. analog input 11. rf7/ss 1 rf7 ss 1 11 i/o i st ttl digital i/o. spi? slave select input. table 1-3: pic18f6527/6622/6627/6722 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c? = i 2 c/smbus input buffer note 1: default assignment for eccp2 when configuration bit ccp2mx is set. 2: alternate assignment for eccp2 when configuration bit ccp2mx is cleared.
pic18f8722 family ds39646b-page 20 preliminary ? 2004 microchip technology inc. portg is a bidirectional i/o port. rg0/eccp3/p3a rg0 eccp3 p3a 3 i/o i/o o st st ? digital i/o. enhanced capture 3 input/compare 3 output/ pwm 3 output. eccp3 pwm output a. rg1/tx2/ck2 rg1 tx2 ck2 4 i/o o i/o st ? st digital i/o. eusart2 asynchronous transmit. eusart2 synchronous clock (see related rx2/dt2). rg2/rx2/dt2 rg2 rx2 dt2 5 i/o i i/o st st st digital i/o. eusart2 asynchronous receive. eusart2 synchronous data (see related tx2/ck2). rg3/ccp4/p3d rg3 ccp4 p3d 6 i/o i/o o st st ? digital i/o. capture 4 input/compare 4 output/pwm 4 output. eccp3 pwm output d. rg4/ccp5/p1d rg4 ccp5 p1d 8 i/o i/o o st st ? digital i/o. capture 5 input/compare 5 output/pwm 5 output. eccp1 pwm output d. rg5 see rg5/mclr /v pp pin. v ss 9, 25, 41, 56 p ? ground reference for logic and i/o pins. v dd 10, 26, 38, 57 p ? positive supply for logic and i/o pins. av ss 20 p ? ground reference for analog modules. av dd 19 p ? positive supply for analog modules. table 1-3: pic18f6527/6622/6627/6722 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c? = i 2 c/smbus input buffer note 1: default assignment for eccp2 when configuration bit ccp2mx is set. 2: alternate assignment for eccp2 when configuration bit ccp2mx is cleared.
? 2004 microchip technology inc. preliminary ds39646b-page 21 pic18f8722 family table 1-4: pic18f8527/8622/8627/8722 pinout i/o descriptions pin name pin number pin type buffer type description tqfp rg5/mclr /v pp rg5 mclr v pp 9 i i p st st master clear (input) or programming voltage (input). digital input. master clear (reset) input. this pin is an active-low reset to the device. programming voltage input. osc1/clki/ra7 osc1 clki ra7 49 i i i/o st cmos ttl oscillator crystal or external clock input. oscillator crystal input or external clock source input. st buffer when configured in rc mode, cmos otherwise. external clock source input. always associated with pin function osc1. (see related osc1/clki, osc2/clko pins.) general purpose i/o pin. osc2/clko/ra6 osc2 clko ra6 50 o o i/o ? ? ttl oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clko, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. general purpose i/o pin. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c?/smb = i 2 c/smbus input buffer note 1: alternate assignment for eccp2 when configuration bit ccp2mx is cleared (all operating modes except microcontroller mode). 2: default assignment for eccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for eccp2 when ccp2mx is cleared (microcontroller mode only). 4: default assignment for p1b/p1c/p3b/p3c (eccpmx is set). 5: alternate assignment for p1b/p1c/p3b/p3c (eccpmx is clear).
pic18f8722 family ds39646b-page 22 preliminary ? 2004 microchip technology inc. porta is a bidirectional i/o port. ra0/an0 ra0 an0 30 i/o i ttl analog digital i/o. analog input 0. ra1/an1 ra1 an1 29 i/o i ttl analog digital i/o. analog input 1. ra2/an2/v ref - ra2 an2 v ref - 28 i/o i i ttl analog analog digital i/o. analog input 2. a/d reference voltage (low) input. ra3/an3/v ref + ra3 an3 v ref + 27 i/o i i ttl analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki ra4 t0cki 34 i/o i st/od st digital i/o. open-drain when configured as output. timer0 external clock input. ra5/an4/hlvdin ra5 an4 hlvdin 33 i/o i i ttl analog analog digital i/o. analog input 4. high/low-voltage detect input. ra6 see the osc2/clko/ra6 pin. ra7 see the osc1/clki/ra7 pin. table 1-4: pic18f8527/8622/8627/8722 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c?/smb = i 2 c/smbus input buffer note 1: alternate assignment for eccp2 when configuration bit ccp2mx is cleared (all operating modes except microcontroller mode). 2: default assignment for eccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for eccp2 when ccp2mx is cleared (microcontroller mode only). 4: default assignment for p1b/p1c/p3b/p3c (eccpmx is set). 5: alternate assignment for p1b/p1c/p3b/p3c (eccpmx is clear).
? 2004 microchip technology inc. preliminary ds39646b-page 23 pic18f8722 family portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0/flt0 rb0 int0 flt0 58 i/o i i ttl st st digital i/o. external interrupt 0. pwm fault input for eccpx. rb1/int1 rb1 int1 57 i/o i ttl st digital i/o. external interrupt 1. rb2/int2 rb2 int2 56 i/o i ttl st digital i/o. external interrupt 2. rb3/int3/eccp2/p2a rb3 int3 eccp2 (1) p2a (1) 55 i/o i o o ttl st ? ? digital i/o. external interrupt 3. enhanced capture 2 input/compare 2 output/ pwm 2 output. eccp2 pwm output a. rb4/kbi0 rb4 kbi0 54 i/o i ttl ttl digital i/o. interrupt-on-change pin. rb5/kbi1/pgm rb5 kbi1 pgm 53 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. low-voltage icsp? programming enable pin. rb6/kbi2/pgc rb6 kbi2 pgc 52 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp? programming clock pin. rb7/kbi3/pgd rb7 kbi3 pgd 47 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming data pin. table 1-4: pic18f8527/8622/8627/8722 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c?/smb = i 2 c/smbus input buffer note 1: alternate assignment for eccp2 when configuration bit ccp2mx is cleared (all operating modes except microcontroller mode). 2: default assignment for eccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for eccp2 when ccp2mx is cleared (microcontroller mode only). 4: default assignment for p1b/p1c/p3b/p3c (eccpmx is set). 5: alternate assignment for p1b/p1c/p3b/p3c (eccpmx is clear).
pic18f8722 family ds39646b-page 24 preliminary ? 2004 microchip technology inc. portc is a bidirectional i/o port. rc0/t1oso/t13cki rc0 t1oso t13cki 36 i/o o i st ? st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi/eccp2/p2a rc1 t1osi eccp2 (2) p2a (2) 35 i/o i i/o o st cmos st ? digital i/o. timer1 oscillator input. enhanced capture 2 input/compare 2 output/ pwm 2 output. eccp2 pwm output a. rc2/eccp1/p1a rc2 eccp1 p1a 43 i/o i/o o st st ? digital i/o. enhanced capture 1 input/compare 1 output/ pwm 1 output. eccp1 pwm output a. rc3/sck1/scl1 rc3 sck1 scl1 44 i/o i/o i/o st st st digital i/o. synchronous serial clock input/output for spi? mode. synchronous serial clock input/output for i 2 c? mode. rc4/sdi1/sda1 rc4 sdi1 sda1 45 i/o i i/o st st st digital i/o. spi data in. i 2 c data i/o. rc5/sdo1 rc5 sdo1 46 i/o o st ? digital i/o. spi data out. rc6/tx1/ck1 rc6 tx1 ck1 37 i/o o i/o st ? st digital i/o. eusart1 asynchronous transmit. eusart1 synchronous clock (see related rx1/dt1). rc7/rx1/dt1 rc7 rx1 dt1 38 i/o i i/o st st st digital i/o. eusart1 asynchronous receive. eusart1 synchronous data (see related tx1/ck1). table 1-4: pic18f8527/8622/8627/8722 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c?/smb = i 2 c/smbus input buffer note 1: alternate assignment for eccp2 when configuration bit ccp2mx is cleared (all operating modes except microcontroller mode). 2: default assignment for eccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for eccp2 when ccp2mx is cleared (microcontroller mode only). 4: default assignment for p1b/p1c/p3b/p3c (eccpmx is set). 5: alternate assignment for p1b/p1c/p3b/p3c (eccpmx is clear).
? 2004 microchip technology inc. preliminary ds39646b-page 25 pic18f8722 family portd is a bidirectional i/o port. rd0/ad0/psp0 rd0 ad0 psp0 72 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 0. parallel slave port data. rd1/ad1/psp1 rd1 ad1 psp1 69 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 1. parallel slave port data. rd2/ad2/psp2 rd2 ad2 psp2 68 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 2. parallel slave port data. rd3/ad3/psp3 rd3 ad3 psp3 67 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 3. parallel slave port data. rd4/ad4/psp4/sdo2 rd4 ad4 psp4 sdo2 66 i/o i/o i/o o st ttl ttl ? digital i/o. external memory address/data 4. parallel slave port data. spi? data out. rd5/ad5/psp5/ sdi2/sda2 rd5 ad5 psp5 sdi2 sda2 65 i/o i/o i/o i i/o st ttl ttl st i 2 c/smb digital i/o. external memory address/data 5. parallel slave port data. spi data in. i 2 c? data i/o. rd6/ad6/psp6/ sck2/scl2 rd6 ad6 psp6 sck2 scl2 64 i/o i/o i/o i/o i/o st ttl ttl st i 2 c/smb digital i/o. external memory address/data 6. parallel slave port data. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c mode. rd7/ad7/psp7/ss2 rd7 ad7 psp7 ss2 63 i/o i/o i/o i st ttl ttl ttl digital i/o. external memory address/data 7. parallel slave port data. spi slave select input. table 1-4: pic18f8527/8622/8627/8722 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c?/smb = i 2 c/smbus input buffer note 1: alternate assignment for eccp2 when configuration bit ccp2mx is cleared (all operating modes except microcontroller mode). 2: default assignment for eccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for eccp2 when ccp2mx is cleared (microcontroller mode only). 4: default assignment for p1b/p1c/p3b/p3c (eccpmx is set). 5: alternate assignment for p1b/p1c/p3b/p3c (eccpmx is clear).
pic18f8722 family ds39646b-page 26 preliminary ? 2004 microchip technology inc. porte is a bidirectional i/o port. re0/ad8/rd /p2d re0 ad8 rd p2d 4 i/o i/o i o st ttl ttl ? digital i/o. external memory address/data 8. read control for parallel slave port. eccp2 pwm output d. re1/ad9/wr /p2c re1 ad9 wr p2c 3 i/o i/o i o st ttl ttl ? digital i/o. external memory address/data 9. write control for parallel slave port. eccp2 pwm output c. re2/ad10/cs /p2b re2 ad10 cs p2b 78 i/o i/o i o st ttl ttl ? digital i/o. external memory address/data 10. chip select control for parallel slave port. eccp2 pwm output b. re3/ad11/p3c re3 ad11 p3c (4) 77 i/o i/o o st ttl ? digital i/o. external memory address/data 11. eccp3 pwm output c. re4/ad12/p3b re4 ad12 p3b (4) 76 i/o i/o o st ttl ? digital i/o. external memory address/data 12. eccp3 pwm output b. re5/ad13/p1c re5 ad13 p1c (4) 75 i/o i/o o st ttl ? digital i/o. external memory address/data 13. eccp1 pwm output c. re6/ad14/p1b re6 ad14 p1b (4) 74 i/o i/o o st ttl ? digital i/o. external memory address/data 14. eccp1 pwm output b. re7/ad15/eccp2/p2a re7 ad15 eccp2 (3) p2a (3) 73 i/o i/o i/o o st ttl st ? digital i/o. external memory address/data 15. enhanced capture 2 input/compare 2 output/ pwm 2 output. eccp2 pwm output a. table 1-4: pic18f8527/8622/8627/8722 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c?/smb = i 2 c/smbus input buffer note 1: alternate assignment for eccp2 when configuration bit ccp2mx is cleared (all operating modes except microcontroller mode). 2: default assignment for eccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for eccp2 when ccp2mx is cleared (microcontroller mode only). 4: default assignment for p1b/p1c/p3b/p3c (eccpmx is set). 5: alternate assignment for p1b/p1c/p3b/p3c (eccpmx is clear).
? 2004 microchip technology inc. preliminary ds39646b-page 27 pic18f8722 family portf is a bidirectional i/o port. rf0/an5 rf0 an5 24 i/o i st analog digital i/o. analog input 5. rf1/an6/c2out rf1 an6 c2out 23 i/o i o st analog ? digital i/o. analog input 6. comparator 2 output. rf2/an7/c1out rf2 an7 c1out 18 i/o i o st analog ? digital i/o. analog input 7. comparator 1 output. rf3/an8 rf3 an8 17 i/o i st analog digital i/o. analog input 8. rf4/an9 rf4 an9 16 i/o i st analog digital i/o. analog input 9. rf5/an10/cv ref rf5 an10 cv ref 15 i/o i o st analog analog digital i/o. analog input 10. comparator reference voltage output. rf6/an11 rf6 an11 14 i/o i st analog digital i/o. analog input 11. rf7/ss 1 rf7 ss 1 13 i/o i st ttl digital i/o. spi? slave select input. table 1-4: pic18f8527/8622/8627/8722 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c?/smb = i 2 c/smbus input buffer note 1: alternate assignment for eccp2 when configuration bit ccp2mx is cleared (all operating modes except microcontroller mode). 2: default assignment for eccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for eccp2 when ccp2mx is cleared (microcontroller mode only). 4: default assignment for p1b/p1c/p3b/p3c (eccpmx is set). 5: alternate assignment for p1b/p1c/p3b/p3c (eccpmx is clear).
pic18f8722 family ds39646b-page 28 preliminary ? 2004 microchip technology inc. portg is a bidirectional i/o port. rg0/eccp3/p3a rg0 eccp3 p3a 5 i/o i/o o st st ? digital i/o. enhanced capture 3 input/compare 3 output/ pwm 3 output. eccp3 pwm output a. rg1/tx2/ck2 rg1 tx2 ck2 6 i/o o i/o st ? st digital i/o. eusart2 asynchronous transmit. eusart2 synchronous clock (see related rx2/dt2). rg2/rx2/dt2 rg2 rx2 dt2 7 i/o i i/o st st st digital i/o. eusart2 asynchronous receive. eusart2 synchronous data (see related tx2/ck2). rg3/ccp4/p3d rg3 ccp4 p3d 8 i/o i/o o st st ? digital i/o. capture 4 input/compare 4 output/pwm 4 output. eccp3 pwm output d. rg4/ccp5/p1d rg4 ccp5 p1d 10 i/o i/o o st st ? digital i/o. capture 5 input/compare 5 output/pwm 5 output. eccp1 pwm output d. rg5 see rg5/mclr /v pp pin. table 1-4: pic18f8527/8622/8627/8722 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c?/smb = i 2 c/smbus input buffer note 1: alternate assignment for eccp2 when configuration bit ccp2mx is cleared (all operating modes except microcontroller mode). 2: default assignment for eccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for eccp2 when ccp2mx is cleared (microcontroller mode only). 4: default assignment for p1b/p1c/p3b/p3c (eccpmx is set). 5: alternate assignment for p1b/p1c/p3b/p3c (eccpmx is clear).
? 2004 microchip technology inc. preliminary ds39646b-page 29 pic18f8722 family porth is a bidirectional i/o port. rh0/a16 rh0 a16 79 i/o i/o st ttl digital i/o. external memory address/data 16. rh1/a17 rh1 a17 80 i/o i/o st ttl digital i/o. external memory address/data 17. rh2/a18 rh2 a18 1 i/o i/o st ttl digital i/o. external memory address/data 18. rh3/a19 rh3 a19 2 i/o i/o st ttl digital i/o. external memory address/data 19. rh4/an12/p3c rh4 an12 p3c (5) 22 i/o i o st analog ? digital i/o. analog input 12. eccp3 pwm output c. rh5/an13/p3b rh5 an13 p3b (5) 21 i/o i o st analog ? digital i/o. analog input 13. eccp3 pwm output b. rh6/an14/p1c rh6 an14 p1c (5) 20 i/o i o st analog ? digital i/o. analog input 14. eccp1 pwm output c. rh7/an15/p1b rh7 an15 p1b (5) 19 i/o i o st analog ? digital i/o. analog input 15. eccp1 pwm output b. table 1-4: pic18f8527/8622/8627/8722 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c?/smb = i 2 c/smbus input buffer note 1: alternate assignment for eccp2 when configuration bit ccp2mx is cleared (all operating modes except microcontroller mode). 2: default assignment for eccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for eccp2 when ccp2mx is cleared (microcontroller mode only). 4: default assignment for p1b/p1c/p3b/p3c (eccpmx is set). 5: alternate assignment for p1b/p1c/p3b/p3c (eccpmx is clear).
pic18f8722 family ds39646b-page 30 preliminary ? 2004 microchip technology inc. portj is a bidirectional i/o port. rj0/ale rj0 ale 62 i/o o st ? digital i/o. external memory address latch enable. rj1/oe rj1 oe 61 i/o o st ? digital i/o. external memory output enable. rj2/wrl rj2 wrl 60 i/o o st ? digital i/o. external memory write low control. rj3/wrh rj3 wrh 59 i/o o st ? digital i/o. external memory write high control. rj4/ba0 rj4 ba0 39 i/o o st ? digital i/o. external memory byte address 0 control. rj5/ce rj4 ce 40 i/o o st ? digital i/o external memory chip enable control. rj6/lb rj6 lb 41 i/o o st ? digital i/o. external memory low byte control. rj7/ub rj7 ub 42 i/o o st ? digital i/o. external memory high byte control. v ss 11, 31, 51, 70 p ? ground reference for logic and i/o pins. v dd 12, 32, 48, 71 p ? positive supply for logic and i/o pins. av ss 26 p ? ground reference for analog modules. av dd 25 p ? positive supply for analog modules. table 1-4: pic18f8527/8622/8627/8722 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c?/smb = i 2 c/smbus input buffer note 1: alternate assignment for eccp2 when configuration bit ccp2mx is cleared (all operating modes except microcontroller mode). 2: default assignment for eccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for eccp2 when ccp2mx is cleared (microcontroller mode only). 4: default assignment for p1b/p1c/p3b/p3c (eccpmx is set). 5: alternate assignment for p1b/p1c/p3b/p3c (eccpmx is clear).
? 2004 microchip technology inc. preliminary ds39646b-page 31 pic18f8722 family 2.0 oscillator configurations 2.1 oscillator types the pic18f8722 family of devices can be operated in ten different oscillator modes. the user can program the configuration bits, fosc3:fosc0, in configuration register 1h to select one of these ten modes: 1. lp low-power crystal 2. xt crystal/resonator 3. hs high-speed crystal/resonator 4. hspll high-speed crystal/resonator with pll enabled 5. rc external resistor/capacitor with f osc /4 output on ra6 6. rcio external resistor/capacitor with i/o on ra6 7. intio1 internal oscillator with f osc /4 output on ra6 and i/o on ra7 8. intio2 internal oscillator with i/o on ra6 and ra7 9. ec external clock with f osc /4 output 10. ecio external clock with i/o on ra6 2.2 crystal oscillator/ceramic resonators in xt, lp, hs or hspll oscillator modes, a crystal or ceramic resonator is connected to the osc1 and osc2 pins to establish oscillation. figure 2-1 shows the pin connections. the oscillator design requires the use of a parallel cut crystal. figure 2-1: crystal/ceramic resonator operation (xt, lp, hs or hspll configuration) table 2-1: capacitor selection for ceramic resonators note: use of a series cut crystal may give a frequency out of the crystal manufacturer?s specifications. typical capacitor values used: mode freq osc1 osc2 xt 3.58 mhz 22 pf 22 pf capacitor values are for design guidance only. different capacitor values may be required to produce acceptable oscillator operation. the user should test the performance of the oscillator over the expected v dd and temperature range for the application. refer to the following application notes for oscillator specific information: an588 ? picmicro ? microcontroller oscillator design guide an826 ? crystal oscillator basics and crystal selection for rfpic? and picmicro ? devices an849 ? basic picmicro ? oscillator design an943 ? practical picmicro ? oscillator analysis and design an949 ? making your oscillator work see the notes following table 2-2 for additional information. note: when using resonators with frequencies above 3.5 mhz, the use of hs mode, rather than xt mode, is recommended. hs mode may be used at any v dd for which the controller is rated. if hs is selected, it is possible that the gain of the oscillator will overdrive the resonator. therefore, a series resistor may be placed between the osc2 pin and the resonator. as a good starting point, the recommended value of r s is 330 ? . note 1: see table 2-1 and table 2-2 for initial values of c1 and c2. 2: a series resistor (r s ) may be required for at strip cut crystals. 3: r f varies with the oscillator mode chosen. c1 (1) c2 (1) xtal osc2 osc1 r f (3) sleep to logic pic18fxxxx r s (2) internal
pic18f8722 family ds39646b-page 32 preliminary ? 2004 microchip technology inc. table 2-2: capacitor selection for quartz crystals an external clock source may also be connected to the osc1 pin in the hs mode, as shown in figure 2-2. when operated in this mode, parameters d033 and d043 apply. figure 2-2: external clock input operation (hs osc configuration) 2.3 external clock input the ec and ecio oscillator modes require an external clock source to be connected to the osc1 pin. there is no oscillator start-up time required after a power-on reset or after an exit from sleep mode. in the ec oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes or to synchronize other logic. figure 2-3 shows the pin connections for the ec oscillator mode. figure 2-3: external clock input operation (ec configuration) the ecio oscillator mode functions like the ec mode, except that the osc2 pin becomes an additional general purpose i/o pin. the i/o pin becomes bit 6 of porta (ra6). figure 2-4 shows the pin connections for the ecio oscillator mode. when operated in this mode, parameters d033a and d043a apply. figure 2-4: external clock input operation (ecio configuration) osc type crystal freq typical capacitor values tested: c1 c2 lp 32 khz 22 pf 22 pf xt 1 mhz 4 mhz 22 pf 22 pf 22 pf 22 pf hs 4 mhz 10 mhz 20 mhz 25 mhz 22 pf 22 pf 22 pf 22 pf 22 pf 22 pf 22 pf 22 pf capacitor values are for design guidance only. different capacitor values may be required to produce acceptable oscillator operation. the user should test the performance of the oscillator over the expected v dd and temperature range for the application. refer to the following application notes for oscillator specific information: an588 ? picmicro ? microcontroller oscillator design guide an826 ? crystal oscillator basics and crystal selection for rfpic? and picmicro ? devices an849 ? basic picmicro ? oscillator design an943 ? practical picmicro ? oscillator analysis and design an949 ? making your oscillator work see the notes following this table for additional information. note 1: higher capacitance increases the stability of the oscillator but also increases the start-up time. 2: when operating below 3v v dd , or when using certain ceramic resonators at any voltage, it may be necessary to use the hs mode or switch to a crystal oscillator. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: rs may be required to avoid overdriving crystals with low drive level specification. 5: always verify oscillator performance over the v dd and temperature range that is expected for the application. osc1 osc2 open clock from ext. system pic18fxxxx (hs mode) osc1/clki osc2/clko f osc /4 clock from ext. system pic18fxxxx osc1/clki i/o (osc2) ra6 clock from ext. system pic18fxxxx
? 2004 microchip technology inc. preliminary ds39646b-page 33 pic18f8722 family 2.4 rc oscillator for timing insensitive applications, the rc and rcio oscillator modes offer additional cost savings. the actual oscillator frequency is a function of several factors: supply voltage values of the external resistor (r ext ) and capacitor (c ext ) operating temperature given the same device, operating voltage and tempera- ture and component values, there will also be unit-to-unit frequency variations. these are due to factors such as: normal manufacturing variation difference in lead frame capacitance between package types (especially for low c ext values) variations within the tolerance of limits of r ext and c ext in the rc oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes or to synchronize other logic. figure 2-5 shows how the r/c combination is connected. figure 2-5: rc oscillator mode the rcio oscillator mode (figure 2-6) functions like the rc mode, except that the osc2 pin becomes an additional general purpose i/o pin. the i/o pin becomes bit 6 of porta (ra6). figure 2-6: rcio oscillator mode 2.5 pll frequency multiplier a phase locked loop (pll) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator. this may be useful for customers who are concerned with emi due to high-frequency crystals or users who require higher clock speeds from an internal oscillator. 2.5.1 hspll oscillator mode the hspll mode makes use of the hs mode oscillator for frequencies up to 10 mhz. a pll then multiplies the oscillator output frequency by 4 to produce an internal clock frequency up to 40 mhz. the pllen bit is not available when this mode is configured as the primary clock source. the pll is only available to the crystal oscillator when the fosc3:fosc0 configuration bits are programmed for hspll mode (= 0110 ). figure 2-7: hspll block diagram 2.5.2 pll and intosc the pll is also available to the internal oscillator block when the internal oscillator block is configured as the primary clock source. in this configuration, the pll is enabled in software and generates a clock output of up to 32 mhz. the operation of intosc with the pll is described in section 2.6.4 ?pll in intosc modes? . osc2/clko c ext r ext pic18fxxxx osc1 f osc /4 internal clock v dd v ss recommended values: 3 k ? r ext 100 k ? 20 pf c ext 300 pf c ext r ext pic18fxxxx osc1 internal clock v dd v ss recommended values: 3 k ? r ext 100 k ? 20 pf c ext 300 pf i/o (osc2) ra6 mux vco loop filter crystal osc osc2 osc1 pll enable f in f out sysclk phase comparator hs oscillator enable 4 (from configuration register 1h) hs mode
pic18f8722 family ds39646b-page 34 preliminary ? 2004 microchip technology inc. 2.6 internal oscillator block the pic18f8722 family of devices includes an internal oscillator block which generates two different clock signals; either can be used as the microcontroller?s clock source. this may eliminate the need for external oscillator circuits on the osc1 and/or osc2 pins. the main output (intosc) is an 8 mhz clock source, which can be used to directly drive the device clock. it also drives a postscaler, which can provide a range of clock frequencies from 31 khz to 4 mhz. the intosc output is enabled when a clock frequency from 125 khz to 8 mhz is selected. the intosc output can also be enabled when 31 khz is selected, depending on the intsrc bit (osctune<7>). the other clock source is the internal rc oscillator (intrc), which provides a nominal 31 khz output. intrc is enabled if it is selected as the device clock source; it is also enabled automatically when any of the following are enabled: power-up timer fail-safe clock monitor watchdog timer two-speed start-up these features are discussed in greater detail in section 25.0 ?special features of the cpu? . the clock source frequency (intosc direct, intrc direct or intosc postscaler) is selected by configuring the ircf bits of the osccon register (page 39). 2.6.1 intio modes using the internal oscillator as the clock source elimi- nates the need for up to two external oscillator pins, which can then be used for digital i/o. two distinct configurations are available: in intio1 mode, the osc2 pin outputs f osc /4, while osc1 functions as ra7 (see figure 2-8) for digital input and output. in intio2 mode, osc1 functions as ra7 and osc2 functions as ra6 (see figure 2-9), both for digital input and output. figure 2-8: intio1 oscillator mode figure 2-9: intio2 oscillator mode 2.6.2 intosc output frequency the internal oscillator block is calibrated at the factory to produce an intosc output frequency of 8 mhz. the intrc oscillator operates independently of the intosc source. any changes in intosc across voltage and temperature are not necessarily reflected by changes in intrc or vice versa. 2.6.3 osctune register the intosc output has been calibrated at the factory but can be adjusted in the user?s application. this is done by writing to tun4:tun0 (osctune<4:0>) in the osctune register (register 2-1). when the osctune register is modified, the intosc frequency will begin shifting to the new frequency. the intosc clock will stabilize within 1 ms. code execu- tion continues during this shift. there is no indication that the shift has occurred. the intrc is not affected by osctune. the osctune register also implements the intsrc (osctune<7>) and pllen (osctune<6>) bits, which control certain features of the internal oscillator block. the intsrc bit allows users to select which internal oscillator provides the clock source when the 31 khz frequency option is selected. this is covered in greater detail in section 2.7.1 ?oscillator control register? . the pllen bit controls the operation of the phase locked loop (pll) in internal oscillator modes (see figure 2-10). figure 2-10: intosc and pll block diagram pic18fxxxx osc2 f osc /4 i/o (osc1) ra7 pic18fxxxx i/o (osc2) ra6 i/o (osc1) ra7 mux vco loop filter osc2 pllen f in f out sysclk phase comparator 8 or 4 mhz 4 (osctune<6>) mux ra6 clko intosc
? 2004 microchip technology inc. preliminary ds39646b-page 35 pic18f8722 family 2.6.4 pll in intosc modes the 4x phase locked loop (pll) can be used with the internal oscillator block to produce faster device clock speeds than are normally possible with the internal oscillator sources. when enabled, the pll produces a clock speed of 16 mhz or 32 mhz. unlike hspll mode, the pll is controlled through software. the control bit, pllen (osctune<6>), is used to enable or disable its operation. the pll is available when the device is configured to use the internal oscillator block as its primary clock source (fosc3:fosc0 = 1001 or 1000 ). additionally, the pll will only function when the selected output fre- quency is either 4 mhz or 8 mhz (osccon<6:4> = 111 or 110 ). if both of these conditions are not met, the pll is disabled and the pllen bit remains clear (writes are ignored). 2.6.5 intosc frequency drift the factory calibrates the internal oscillator block output (intosc) for 8 mhz. however, this frequency may drift as v dd or temperature changes and can affect the controller operation in a variety of ways. it is possible to adjust the intosc frequency by modifying the value in the osctune register. depending on the device, this may have no effect on the intrc clock source frequency. tuning the intosc source requires knowing when to make the adjustment, in which direction it should be made and in some cases, how large a change is needed. three compensation techniques are discussed in section 2.6.5.1 ?compensating with the eusart? , section 2.6.5.2 ?compensating with the timers? and section 2.6.5.3 ?compensating with the ccp module in capture mode? but other techniques may be used. register 2-1: osctune: oscillator tuning register r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 intsrc pllen (1) ? tun4 tun3 tun2 tun1 tun0 bit 7 bit 0 bit 7 intsrc: internal oscillator low-frequency source select bit 1 = 31.25 khz device clock derived from 8 mhz intosc source (divide-by-256 enabled) 0 = 31 khz device clock derived directly from intrc internal oscillator bit 6 pllen: frequency multiplier pll for intosc enable bit (1) 1 = pll enabled for intosc (4 mhz and 8 mhz only) 0 = pll disabled note 1: available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as ? 0 ?. see section 2.6.4 ?pll in intosc modes? for details. bit 5 unimplemented: read as ? 0 ? bit 4-0 tun4:tun0: frequency tuning bits 01111 = maximum frequency 00001 00000 = center frequency. oscillator module is running at the calibrated frequency. 11111 10000 = minimum frequency legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 36 preliminary ? 2004 microchip technology inc. 2.6.5.1 compensating with the eusart an adjustment may be required when the eusart begins to generate framing errors or receives data with errors while in asynchronous mode. framing errors indicate that the device clock frequency is too high. to adjust for this, decrement the value in osctune to reduce the clock frequency. on the other hand, errors in data may suggest that the clock speed is too low. to compensate, increment osctune to increase the clock frequency. 2.6.5.2 compensating with the timers this technique compares device clock speed to some reference clock. two timers may be used; one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the timer1 oscillator. both timers are cleared, but the timer clocked by the reference generates interrupts. when an interrupt occurs, the internally clocked timer is read and both timers are cleared. if the internally clocked timer value is much greater than expected, then the internal oscillator block is running too fast. to adjust for this, decrement the osctune register. 2.6.5.3 compensating with the ccp module in capture mode a ccp module can use free running timer1 (or timer3), clocked by the internal oscillator block and an external event with a known period (i.e., ac power frequency). the time of the first event is captured in the ccprxh:ccprxl registers and is recorded for use later. when the second event causes a capture, the time of the first event is subtracted from the time of the second event. since the period of the external event is known, the time difference between events can be calculated. if the measured time is much greater than the calculated time, the internal oscillator block is running too fast. to compensate, decrement the osctune register. if the measured time is much less than the calculated time, the internal oscillator block is running too slow. to compensate, increment the osctune register.
? 2004 microchip technology inc. preliminary ds39646b-page 37 pic18f8722 family 2.7 clock sources and oscillator switching the pic18f8722 family of devices includes a feature that allows the device clock source to be switched from the main oscillator to an alternate clock source. these devices also offer two alternate clock sources. when an alternate clock source is enabled, the various power-managed operating modes are available. essentially, there are three clock sources for these devices: primary oscillators secondary oscillators internal oscillator block the primary oscillators include the external crystal and resonator modes, the external rc modes, the external clock modes and the internal oscillator block. the particular mode is defined by the fosc3:fosc0 configuration bits. the details of these modes are covered earlier in this chapter. the secondary oscillators are those external sources not connected to the osc1 or osc2 pins. these sources may continue to operate even after the controller is placed in a power-managed mode. the pic18f8722 family of devices offers the timer1 oscillator as a secondary oscillator. this oscillator, in all power-managed modes, is often the time base for functions such as a real-time clock. most often, a 32.768 khz watch crystal is connected between the rc0/t1oso/t13cki and rc1/t1osi pins. like the lp mode oscillator circuit, loading capacitors are also connected from each pin to ground. the timer1 oscillator is discussed in greater detail in section 13.3 ?timer1 oscillator? . in addition to being a primary clock source, the internal oscillator block is available as a power-managed mode clock source. the intrc source is also used as the clock source for several special features, such as the wdt and fail-safe clock monitor. the clock sources for the pic18f8722 family of devices are shown in figure 2-11. see section 25.0 ?special features of the cpu? for configuration register details. figure 2-11: pic18f8722 family clock diagram pic18f6527/6622/6627/6722/8527/8622/8627/8722 4 x pll fosc3:fosc0 secondary oscillator t1oscen enable oscillator t1oso t1osi clock source option for other modules osc1 osc2 sleep hspll, intosc/pll lp, xt, hs, rc, ec t1osc cpu peripherals idlen postscaler mux mux 8 mhz 4 mhz 2 mhz 1 mhz 500 khz 125 khz 250 khz osccon<6:4> 111 110 101 100 011 010 001 000 31 khz intrc source internal oscillator block wdt, pwrt, fscm 8 mhz internal oscillator (intosc) osccon<6:4> clock control osccon<1:0> source 8 mhz 31 khz (intrc) osctune<6> 0 1 osctune<7> and two-speed start-up primary oscillator
pic18f8722 family ds39646b-page 38 preliminary ? 2004 microchip technology inc. 2.7.1 oscillator control register the osccon register (register 2-2) controls several aspects of the device clock?s operation, both in full power operation and in power-managed modes. the system clock select bits, scs1:scs0, select the clock source. the available clock sources are the primary clock (defined by the fosc3:fosc0 configu- ration bits), the secondary clock (timer1 oscillator) and the internal oscillator block. the clock source changes immediately after either of the scsi:scso bits are changed, following a brief clock transition interval. the scs bits are reset on all forms of reset. the internal oscillator frequency select bits (ircf2:ircf0) select the frequency output of the internal oscillator block to drive the device clock. the choices are the intrc source (31 khz), the intosc source (8 mhz) or one of the frequencies derived from the intosc postscaler (31.25 khz to 4 mhz). if the internal oscillator block is supplying the device clock, changing the states of these bits will have an immedi- ate change on the internal oscillator?s output. on device resets, the default output frequency of the internal oscillator block is set at 1 mhz. when a nominal output frequency of 31 khz is selected (ircf2:ircf0 = 000 ), users may choose which internal oscillator acts as the source. this is done with the intsrc bit in the osctune register (osctune<7>). setting this bit selects intosc as a 31.25 khz clock source derived from the intosc postscaler. clearing intsrc selects intrc (nominally 31 khz) as the clock source and disables the intosc to reduce current consumption. this option allows users to select the tunable and more precise intosc as a clock source, while maintaining power savings with a very low clock speed. addition- ally, the intosc source will already be stable should a switch to a higher frequency be needed quickly. regardless of the setting of intsrc, intrc always remains the clock source for features such as the watchdog timer and the fail-safe clock monitor. the osts, iofs and t1run bits indicate which clock source is currently providing the device clock. the osts bit indicates that the oscillator start-up timer and pll start-up timer (if enabled) have timed out and the primary clock is providing the device clock in primary clock modes. the iofs bit indicates when the internal oscillator block has stabilized and is providing the device clock in rc clock modes. the t1run bit (t1con<6>) indicates when the timer1 oscillator is providing the device clock in secondary clock modes. in power-managed modes, only one of these three bits will be set at any time. if none of these bits are set, the intrc is providing the clock or the internal oscillator block has just started and is not yet stable. the idlen bit controls whether the device goes into sleep mode or one of the idle modes when the sleep instruction is executed. the use of the flag and control bits in the osccon register is discussed in more detail in section 3.0 ?power-managed modes? . 2.7.2 oscillator transitions the pic18f8722 family of devices contains circuitry to prevent clock ?glitches? when switching between clock sources. a short pause in the device clock occurs dur- ing the clock switch. the length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. this formula assumes that the new clock source is stable. clock transitions are discussed in greater detail in section 3.1.2 ?entering power-managed modes? . note 1: the timer1 oscillator must be enabled to select the secondary clock source. the timer1 oscillator is enabled by setting the t1oscen bit in the timer1 control regis- ter (t1con<3>). if the timer1 oscillator is not enabled, then any attempt to select a secondary clock source will be ignored. 2: it is recommended that the timer1 oscillator be operating and stable before selecting the secondary clock source or a very long delay may occur while the timer1 oscillator starts.
? 2004 microchip technology inc. preliminary ds39646b-page 39 pic18f8722 family register 2-2: osccon: oscillator control register r/w-0 r/w-1 r/w-0 r/w-0 r (1) r-0 r/w-0 r/w-0 idlen ircf2 ircf1 ircf0 osts iofs scs1 scs0 bit 7 bit 0 bit 7 idlen: idle enable bit 1 = device enters an idle mode when a sleep instruction is executed 0 = device enters sleep mode when a sleep instruction is executed bit 6-4 ircf2:ircf0: internal oscillator frequency select bits (5) 111 = 8 mhz (intosc drives clock directly) 110 = 4 mhz 101 = 2 mhz 100 = 1 mhz (3) 011 = 500 khz 010 = 250 khz 001 = 125 khz 000 = 31 khz (from either intosc/256 or intrc directly) (2) bit 3 osts: oscillator start-up time-out status bit (1) 1 = oscillator start-up timer (ost) time-out has expired; primary oscillator is running 0 = oscillator start-up timer (ost) time-out is running; primary oscillator is not ready bit 2 iofs: intosc frequency stable bit 1 = intosc frequency is stable 0 = intosc frequency is not stable bit 1-0 scs1:scs0: system clock select bits (4) 1x = internal oscillator block 01 = secondary (timer1) oscillator 00 = primary oscillator note 1: reset state depends on state of the ieso configuration bit. 2: source selected by the intsrc bit (osctune<7>), see text. 3: default output frequency of intosc on reset. 4: modifying the scsi:scso bits will cause an immediate clock source switch. 5: modifying the ircf3:ircf0 bits will cause an immediate clock frequency switch if the internal oscillator is providing the device clocks. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 40 preliminary ? 2004 microchip technology inc. 2.8 effects of power-managed modes on the various clock sources when pri_idle mode is selected, the configured oscillator continues to run without interruption. for all other power-managed modes, the oscillator using the osc1 pin is disabled. the osc1 pin (and osc2 pin in crystal oscillator modes) will stop oscillating. in secondary clock modes (sec_run and sec_idle), the timer1 oscillator is operating and providing the device clock. the timer1 oscillator may also run in all power-managed modes if required to clock timer1 or timer3. in internal oscillator modes (rc_run and rc_idle), the internal oscillator block provides the device clock source. the 31 khz intrc output can be used directly to provide the clock and may be enabled to support various special features, regardless of the power- managed mode (see section 25.2 ?watchdog timer (wdt)? and section 25.4 ?fail-safe clock monitor? for more information). the intosc output at 8 mhz may be used directly to clock the device or may be divided down by the postscaler. the intosc output is disabled if the clock is provided directly from the intrc output. the intosc output is also enabled for two- speed start-up at 1 mhz after resets and when configured for wake from sleep mode. if the sleep mode is selected, all clock sources are stopped. since all the transistor switching currents have been stopped, sleep mode achieves the lowest current consumption of the device (only leakage currents). enabling any on-chip feature that will operate during sleep will increase the current consumed during sleep. the intrc is required to support wdt operation. the timer1 oscillator may be operating to support a real- time clock. other features may be operating that do not require a device clock source (i.e., ssp slave, psp, intn pins and others). peripherals that may add significant current consumption are listed in section 28.2 ?dc characteristics?. 2.9 power-up delays power-up delays are controlled by two or three timers, so that no external reset circuitry is required for most applications. the delays ensure that the device is kept in reset until the device power supply is stable under normal circumstances and the primary clock is operat- ing and stable. for additional information on power-up delays, see section 4.5 ?device reset timers? . the first timer is the power-up timer (pwrt) which provides a fixed delay on power-up (parameter 33, table 28-12). it is enabled by clearing (= 0 ) the pwrten configuration bit (config2l<0>). 2.9.1 delays for power-up and return to primary clock the second timer is the oscillator start-up timer (ost), intended to delay execution until the crystal oscillator is stable (lp, xt and hs modes). the ost does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. when the hspll oscillator mode is selected, a third timer delays execution for an additional 2 ms following the hs mode ost delay, so the pll can lock to the incoming clock frequency. at the end of these delays, the osts bit (osccon<3>) is set. there is a delay of interval t csd (parameter 38, table 28-12), once execution is allowed to start, when the controller becomes ready to execute instructions. this delay runs concurrently with any other delays. this may be the only delay that occurs when any of the ec, rc or intio modes are used as the primary clock source. table 2-3: osc1 and osc2 pin states in sleep mode osc mode osc1 pin osc2 pin rc, intio1 floating, external resistor pulls high at logic low (clock/4 output) rcio floating, external resistor pulls high configured as porta, bit 6 intio2 configured as porta, bit 7 configured as porta, bit 6 ecio floating, driven by external clock configured as porta, bit 6 ec floating, driven by external clock at logic low (clock/4 output) lp, xt and hs feedback inverter disabled at quiescent voltage level feedback inverter disabled at quiescent voltage level note: see table 4-2 in section 4.0 ?reset? for time-outs due to sleep and mclr reset.
? 2004 microchip technology inc. preliminary ds39646b-page 41 pic18f8722 family 3.0 power-managed modes the pic18f8722 family of devices offers a total of seven operating modes for more efficient power man- agement. these modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). there are three categories of power-managed modes: run modes idle modes sleep mode these categories define which portions of the device are clocked and sometimes, what speed. the run and idle modes may use any of the three available clock sources (primary, secondary or internal oscillator block); the sleep mode does not use a clock source. the power-managed modes include several power- saving features offered on previous picmicro devices. one is the clock switching feature, offered in other pic18 devices, allowing the controller to use the timer1 oscillator in place of the primary oscillator. also included is the sleep mode, offered by all picmicro devices, where all device clocks are stopped. 3.1 selecting power-managed modes selecting a power-managed mode requires two decisions: if the cpu is to be clocked or not and the selection of a clock source. the idlen bit (osccon<7>) controls cpu clocking, while the scs1:scs0 bits (osccon<1:0>) select the clock source. the individual modes, bit settings, clock sources and affected modules are summarized in table 3-1. 3.1.1 clock sources the scs1:scs0 bits allow the selection of one of three clock sources for power-managed modes. they are: the primary clock, as defined by the fosc3:fosc0 configuration bits the secondary clock (the timer1 oscillator) the internal oscillator block (for intosc modes) 3.1.2 entering power-managed modes switching from one power-managed mode to another begins by loading the osccon register. the scs1:scs0 bits select the clock source and determine which run or idle mode is to be used. changing these bits causes an immediate switch to the new clock source, assuming that it is running. the switch may also be subject to clock transition delays. these are discussed in section 3.1.3 ?clock transitions and status indicators? and subsequent sections. entry to the power-managed idle or sleep modes is triggered by the execution of a sleep instruction. the actual mode that results depends on the status of the idlen bit. depending on the current mode and the mode being switched to, a change to a power-managed mode does not always require setting all of these bits. many transitions may be done by changing the oscillator select bits, or changing the idlen bit, prior to issuing a sleep instruction. if the idlen bit is already configured correctly, it may only be necessary to perform a sleep instruction to switch to the desired mode. table 3-1: power-managed modes mode osccon bits module clocking available clock and oscillator source idlen<7> (1) scs<1:0> cpu peripherals sleep 0 n/a off off none ? all clocks are disabled pri_run n/a 00 clocked clocked primary ? lp, xt, hs, hspll, rc, ec and internal oscillator block (2) . this is the normal full power execution mode. sec_run n/a 01 clocked clocked secondary ? timer1 oscillator rc_run n/a 1x clocked clocked internal oscillator block (2) pri_idle 100 off clocked primary ? lp, xt, hs, hspll, rc, ec sec_idle 101 off clocked secondary ? timer1 oscillator rc_idle 11x off clocked internal oscillator block (2) note 1: idlen reflects its value when the sleep instruction is executed. 2: includes intosc and intosc postscaler, as well as the intrc source.
pic18f8722 family ds39646b-page 42 preliminary ? 2004 microchip technology inc. 3.1.3 clock transitions and status indicators the length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. this formula assumes that the new clock source is stable. three bits indicate the current clock source and its status. they are: osts (osccon<3>) iofs (osccon<2>) t1run (t1con<6>) in general, only one of these bits will be set while in a given power-managed mode. when the osts bit is set, the primary clock is providing the device clock. when the iofs bit is set, the intosc output is providing a stable 8 mhz clock source to a divider that actually drives the device clock. when the t1run bit is set, the timer1 oscillator is providing the clock. if none of these bits are set, then either the intrc clock source is clocking the device, or the intosc source is not yet stable. if the internal oscillator block is configured as the pri- mary clock source by the fosc3:fosc0 configuration bits, then both the osts and iofs bits may be set when in pri_run or pri_idle modes. this indicates that the primary clock (intosc output) is generating a stable 8 mhz output. entering another intosc power- managed mode at the same frequency would clear the osts bit. 3.1.4 multiple sleep commands the power-managed mode that is invoked with the sleep instruction is determined by the setting of the idlen bit at the time the instruction is executed. if another sleep instruction is executed, the device will enter the power-managed mode specified by idlen at that time. if idlen has changed, the device will enter the new power-managed mode specified by the new setting. 3.2 run modes in the run modes, clocks to both the core and peripherals are active. the difference between these modes is the clock source. 3.2.1 pri_run mode the pri_run mode is the normal, full power execution mode of the microcontroller. this is also the default mode upon a device reset, unless two-speed start-up is enabled (see section 25.3 ?two-speed start-up? for details). in this mode, the osts bit is set. the iofs bit may be set if the internal oscillator block is the primary clock source (see section 2.7.1 ?oscillator control register? ). 3.2.2 sec_run mode the sec_run mode is the compatible mode to the ?clock switching? feature offered in other pic18 devices. in this mode, the cpu and peripherals are clocked from the timer1 oscillator. this gives users the option of lower power consumption while still using a high accuracy clock source. sec_run mode is entered by setting the scs1:scs0 bits to ? 01 ?. the device clock source is switched to the timer1 oscillator (see figure 3-1), the primary oscilla- tor is shut down, the t1run bit (t1con<6>) is set and the osts bit is cleared. on transitions from sec_run mode to pri_run, the peripherals and cpu continue to be clocked from the timer1 oscillator while the primary clock is started. when the primary clock becomes ready, a clock switch back to the primary clock occurs (see figure 3-2). when the clock switch is complete, the t1run bit is cleared, the osts bit is set and the primary clock is providing the clock. the idlen and scs bits are not affected by the wake-up; the timer1 oscillator continues to run. note 1: caution should be used when modifying a single ircf bit. if v dd is less than 3v, it is possible to select a higher clock speed than is supported by the low v dd . improper device operation may result if the v dd /f osc specifications are violated. 2: executing a sleep instruction does not necessarily place the device into sleep mode. it acts as the trigger to place the controller into either the sleep mode or one of the idle modes, depending on the setting of the idlen bit. note: the timer1 oscillator should already be running prior to entering sec_run mode. if the t1oscen bit is not set when the scs1:scs0 bits are set to ? 01 ?, entry to sec_run mode will not occur. if the timer1 oscillator is enabled, but not yet running, device clocks will be delayed until the oscillator has started; in such situa- tions, initial oscillator operation is far from stable and unpredictable operation may result.
? 2004 microchip technology inc. preliminary ds39646b-page 43 pic18f8722 family figure 3-1: transition timing for entry to sec_run mode figure 3-2: transition timing from sec_run mode to pri_run mode (hspll) 3.2.3 rc_run mode in rc_run mode, the cpu and peripherals are clocked from the internal oscillator block using the intosc multiplexer. in this mode, the primary clock is shut down. when using the intrc source, this mode provides the best power conservation of all the run modes, while still executing code. it works well for user applications which are not highly timing sensitive or do not require high-speed clocks at all times. if the primary clock source is the internal oscillator block (either intrc or intosc), there are no distin- guishable differences between pri_run and rc_run modes during execution. however, a clock switch delay will occur during entry to and exit from rc_run mode. therefore, if the primary clock source is the internal oscillator block, the use of rc_run mode is not recommended. this mode is entered by setting the scs1 bit to ? 1 ?. although it is ignored, it is recommended that the scs0 bit also be cleared; this is to maintain software compat- ibility with future devices. when the clock source is switched to the intosc multiplexer (see figure 3-3), the primary oscillator is shut down and the osts bit is cleared. the ircf bits may be modified at any time to immediately change the clock speed. q4 q3 q2 osc1 peripheral program q1 t1osi q1 counter clock cpu clock pc + 2 pc 123 n-1n clock transition (1) q4 q3 q2 q1 q3 q2 pc + 4 note 1: clock transition typically occurs within 2-4 t osc . q1 q3 q4 osc1 peripheral program pc t1osi pll clock q1 pc + 4 q2 output q3 q4 q1 cpu clock pc + 2 clock counter q2 q2 q3 note1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. 2: clock transition typically occurs within 2-4 t osc . scs1:scs0 bits changed t pll (1) 12 n-1n clock osts bit set transition (2) t ost (1) note: caution should be used when modifying a single ircf bit. if v dd is less than 3v, it is possible to select a higher clock speed than is supported by the low v dd . improper device operation may result if the v dd /f osc specifications are violated.
pic18f8722 family ds39646b-page 44 preliminary ? 2004 microchip technology inc. if the ircf bits and the intsrc bit are all clear, the intosc output is not enabled and the iofs bit will remain clear; there will be no indication of the current clock source. the intrc source is providing the device clocks. if the ircf bits are changed from all clear (thus, enabling the intosc output) or if intsrc is set, the iofs bit becomes set after the intosc output becomes stable. clocks to the device continue while the intosc source stabilizes after an interval of t iobst (parameter 39, table 28-12). if the ircf bits were previously at a non-zero value, or if intsrc was set before setting scs1 and the intosc source was already stable, the iofs bit will remain set. on transitions from rc_run mode to pri_run mode, the device continues to be clocked from the intosc multiplexer while the primary clock is started. when the primary clock becomes ready, a clock switch to the primary clock occurs (see figure 3-4). when the clock switch is complete, the iofs bit is cleared, the osts bit is set and the primary clock is providing the device clock. the idlen and scs bits are not affected by the switch. the intrc source will continue to run if either the wdt or the fail-safe clock monitor is enabled. figure 3-3: transition timing to rc_run mode figure 3-4: transition timing fr om rc_run mode to pri_run mode q4 q3 q2 osc1 peripheral program q1 intrc q1 counter clock cpu clock pc + 2 pc 123 n-1n clock transition (1) q4 q3 q2 q1 q3 q2 pc + 4 note 1: clock transition typically occurs within 2-4 t osc . q1 q3 q4 osc1 peripheral program pc intosc pll clock q1 pc + 4 q2 output q3 q4 q1 cpu clock pc + 2 clock counter q2 q2 q3 note1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. 2: clock transition typically occurs within 2-4 t osc . scs1:scs0 bits changed t pll (1) 12 n-1n clock osts bit set transition (2) multiplexer t ost (1)
? 2004 microchip technology inc. preliminary ds39646b-page 45 pic18f8722 family 3.3 sleep mode the power-managed sleep mode in the pic18f8722 family of devices is identical to the legacy sleep mode offered in all other picmicro devices. it is entered by clearing the idlen bit (the default state on device reset) and executing the sleep instruction. this shuts down the selected oscillator (figure 3-5). all clock source status bits are cleared. entering the sleep mode from any other mode does not require a clock switch. this is because no clocks are needed once the controller has entered sleep. if the wdt is selected, the intrc source will continue to operate. if the timer1 oscillator is enabled, it will also continue to run. when a wake event occurs in sleep mode (by interrupt, reset or wdt time-out), the device will not be clocked until the clock source selected by the scs1:scs0 bits becomes ready (see figure 3-6), or it will be clocked from the internal oscillator block if either the two- speed start-up or the fail-safe clock monitor are enabled (see section 25.0 ?special features of the cpu? ). in either case, the osts bit is set when the primary clock is providing the device clocks. the idlen and scs bits are not affected by the wake-up. 3.4 idle modes the idle modes allow the controller?s cpu to be selectively shut down while the peripherals continue to operate. selecting a particular idle mode allows users to further manage power consumption. if the idlen bit is set to a ? 1 ? when a sleep instruction is executed, the peripherals will be clocked from the clock source selected using the scs1:scs0 bits; however, the cpu will not be clocked. the clock source status bits are not affected. setting idlen and executing a sleep instruction provides a quick method of switching from a given run mode to its corresponding idle mode. if the wdt is selected, the intrc source will continue to operate. if the timer1 oscillator is enabled, it will also continue to run. since the cpu is not executing instructions, the only exits from any of the idle modes are by interrupt, wdt time-out or a reset. when a wake event occurs, cpu execution is delayed by an interval of t csd (parameter 38, table 28-12) while it becomes ready to execute code. when the cpu begins executing code, it resumes with the same clock source for the current idle mode. for example, when waking from rc_idle mode, the internal oscillator block will clock the cpu and peripherals (in other words, rc_run mode). the idlen and scs bits are not affected by the wake-up. while in any idle mode or the sleep mode, a wdt time-out will result in a wdt wake-up to the run mode currently specified by the scs1:scs0 bits. figure 3-5: transition timing for entry to sleep mode figure 3-6: transition timing for wake from sleep (hspll) q4 q3 q2 osc1 peripheral sleep program q1 q1 counter clock cpu clock pc + 2 pc q3 q4 q1 q2 osc1 peripheral program pc pll clock q3 q4 output cpu clock q1 q2 q3 q4 q1 q2 clock counter pc + 6 pc + 4 q1 q2 q3 q4 wake event note1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. t ost (1) t pll (1) osts bit set pc + 2
pic18f8722 family ds39646b-page 46 preliminary ? 2004 microchip technology inc. 3.4.1 pri_idle mode this mode is unique among the three low-power idle modes, in that it does not disable the primary device clock. for timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to ?warm-up? or transition from another oscillator. pri_idle mode is entered from pri_run mode by setting the idlen bit and executing a sleep instruc- tion. if the device is in another run mode, set idlen first, then clear the scs bits and execute sleep . although the cpu is disabled, the peripherals continue to be clocked from the primary clock source specified by the fosc3:fosc0 configuration bits. the osts bit remains set (see figure 3-7). when a wake event occurs, the cpu is clocked from the primary clock source. a delay of interval t csd (parameter 39, table 28-12) is required between the wake event and when code execution starts. this is required to allow the cpu to become ready to execute instructions. after the wake-up, the osts bit remains set. the idlen and scs bits are not affected by the wake-up (see figure 3-8). 3.4.2 sec_idle mode in sec_idle mode, the cpu is disabled but the peripherals continue to be clocked from the timer1 oscillator. this mode is entered from sec_run by set- ting the idlen bit and executing a sleep instruction. if the device is in another run mode, set the idlen bit first, then set the scs1:scs0 bits to ? 01 ? and execute sleep . when the clock source is switched to the timer1 oscillator, the primary oscillator is shut down, the osts bit is cleared and the t1run bit is set. when a wake event occurs, the peripherals continue to be clocked from the timer1 oscillator. after an interval of t csd following the wake event, the cpu begins exe- cuting code being clocked by the timer1 oscillator. the idlen and scs bits are not affected by the wake-up; the timer1 oscillator continues to run (see figure 3-8). figure 3-7: transition timing for entry to idle mode figure 3-8: transition timing for wake from idle to run mode note: the timer1 oscillator should already be running prior to entering sec_idle mode. if the t1oscen bit is not set when the sleep instruction is executed, the sleep instruction will be ignored and entry to sec_idle mode will not occur. if the timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started. in such situations, initial oscillator operation is far from stable and unpredictable operation may result. q1 peripheral program pc pc + 2 osc1 q3 q4 q1 cpu clock clock counter q2 osc1 peripheral program pc cpu clock q1 q3 q4 clock counter q2 wake event t csd
? 2004 microchip technology inc. preliminary ds39646b-page 47 pic18f8722 family 3.4.3 rc_idle mode in rc_idle mode, the cpu is disabled but the periph- erals continue to be clocked from the internal oscillator block using the intosc multiplexer. this mode allows for controllable power conservation during idle periods. from rc_run, this mode is entered by setting the idlen bit and executing a sleep instruction. if the device is in another run mode, first set idlen, then set the scs1 bit and execute sleep . although its value is ignored, it is recommended that scs0 also be cleared; this is to maintain software compatibility with future devices. the intosc multiplexer may be used to select a higher clock frequency by modifying the ircf bits before executing the sleep instruction. when the clock source is switched to the intosc multiplexer, the primary oscillator is shut down and the osts bit is cleared. if the ircf bits are set to any non-zero value, or the intsrc bit is set, the intosc output is enabled. the iofs bit becomes set, after the intosc output becomes stable, after an interval of t iobst (parameter 39, table 28-12). clocks to the peripherals continue while the intosc source stabilizes. if the ircf bits were previously at a non-zero value, or intsrc was set before the sleep instruction was exe- cuted and the intosc source was already stable, the iofs bit will remain set. if the ircf bits and intsrc are all clear, the intosc output will not be enabled, the iofs bit will remain clear and there will be no indication of the current clock source. when a wake event occurs, the peripherals continue to be clocked from the intosc multiplexer. after a delay of t csd (parameter 38, table 28-12) following the wake event, the cpu begins executing code being clocked by the intosc multiplexer. the idlen and scs bits are not affected by the wake-up. the intrc source will continue to run if either the wdt or the fail-safe clock monitor is enabled. 3.5 exiting idle and sleep modes an exit from sleep mode or any of the idle modes is triggered by an interrupt, a reset or a wdt time-out. this section discusses the triggers that cause exits from power-managed modes. the clocking subsystem actions are discussed in each of the power-managed modes (see section 3.2 ?run modes?, section 3.3 ?sleep mode? and section 3.4 ?idle modes? ). 3.5.1 exit by interrupt any of the available interrupt sources can cause the device to exit from an idle mode or the sleep mode to a run mode. to enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the intcon or pie registers. the exit sequence is initiated when the corresponding interrupt flag bit is set. on all exits from idle or sleep modes by interrupt, code execution branches to the interrupt vector if the gie/ gieh bit (intcon<7>) is set. otherwise, code execu- tion continues or resumes without branching (see section 10.0 ?interrupts? ). a fixed delay of interval t csd following the wake event is required when leaving sleep and idle modes. this delay is required for the cpu to prepare for execution. instruction execution resumes on the first clock cycle following this delay. 3.5.2 exit by wdt time-out a wdt time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs. if the device is not executing code (all idle modes and sleep mode), the time-out will result in an exit from the power-managed mode (see section 3.2 ?run modes? and section 3.3 ?sleep mode? ). if the device is executing code (all run modes), the time-out will result in a wdt reset (see section 25.2 ?watchdog timer (wdt)? ). the wdt timer and postscaler are cleared by executing a sleep or clrwdt instruction, the loss of a currently selected clock source (if the fail-safe clock monitor is enabled) and modifying the ircf bits in the osccon register if the internal oscillator block is the device clock source. 3.5.3 exit by reset normally, the device is held in reset by the oscillator start-up timer (ost) until the primary clock becomes ready. at that time, the osts bit is set and the device begins executing code. if the internal oscillator block is the new clock source, the iofs bit is set instead. the exit delay time from reset to the start of code execution depends on both the clock sources before and after the wake-up and the type of oscillator if the new clock source is the primary clock. exit delays are summarized in table 3-2. code execution can begin before the primary clock becomes ready. if either the two-speed start-up (see section 25.3 ?two-speed start-up? ) or fail-safe clock monitor (see section 25.4 ?fail-safe clock monitor? ) is enabled, the device may begin execution as soon as the reset source has cleared. execution is clocked by the intosc multiplexer driven by the inter- nal oscillator block. execution is clocked by the internal oscillator block until either the primary clock becomes ready or a power-managed mode is entered before the primary clock becomes ready; the primary clock is then shut down.
pic18f8722 family ds39646b-page 48 preliminary ? 2004 microchip technology inc. 3.5.4 exit without an oscillator start-up delay certain exits from power-managed modes do not invoke the ost at all. there are two cases: pri_idle mode, where the primary clock source is not stopped and the primary clock source is not any of the lp, xt, hs or hspll modes. in these instances, the primary clock source either does not require an oscillator start-up delay since it is already running (pri_idle), or normally does not require an oscillator start-up delay (rc, ec and intio oscillator modes). however, a fixed delay of interval t csd following the wake event is still required when leaving sleep and idle modes to allow the cpu to prepare for execution. instruction execution resumes on the first clock cycle following this delay. table 3-2: exit delay on wake-up by reset from sleep mode or any idle mode (by clock sources) clock source before wake-up clock source after wake-up exit delay clock ready status bit (osccon) primary device clock (pri_idle mode) lp, xt, hs t csd (1) osts hspll ec, rc intosc (2) iofs t1osc or intrc lp, xt, hs t ost (3) osts hspll t ost + t rc (3) ec, rc t csd (1) intosc (2) t iobst (4) iofs intosc (2) lp, xt, hs t ost (4) osts hspll t ost + t rc (3) ec, rc t csd (1) intosc (2) none iofs none (sleep mode) lp, xt, hs t ost (3) osts hspll t ost + t rc (3) ec, rc t csd (1) intosc (2) t iobst (4) iofs note 1: t csd (parameter 38, table 28-12) is a required delay when waking from sleep and all idle modes and runs concurrently with any other required delays (see section 3.4 ?idle modes? ). 2: includes both the intosc 8 mhz source and postscaler derived frequencies. on reset, intosc defaults to 1 mhz. 3: t ost is the oscillator start-up timer (parameter 32, table 28-12). t rc is the pll lock-out timer (parameter f12, table 28-7); it is also designated as t pll . 4: execution continues during t iobst (parameter 39, table 28-12), the intosc stabilization period.
? 2004 microchip technology inc. preliminary ds39646b-page 49 pic18f8722 family 4.0 reset the pic18f8722 family of devices differentiates between various kinds of reset: a) power-on reset (por) b) mclr reset during normal operation c) mclr reset during power-managed modes d) watchdog timer (wdt) reset (during execution) e) programmable brown-out reset (bor) f) reset instruction g) stack full reset h) stack underflow reset this section discusses resets generated by mclr , por and bor and covers the operation of the various start-up timers. stack reset events are covered in section 5.1.3.4 ?stack full and underflow resets? . wdt resets are covered in section 25.2 ?watchdog timer (wdt)? . a simplified block diagram of the on-chip reset circuit is shown in figure 4-1. 4.1 rcon register device reset events are tracked through the rcon register (register 4-1). the lower five bits of the regis- ter indicate that a specific reset event has occurred. in most cases, these bits can only be cleared by the event and must be set by the application after the event. the state of these flag bits, taken together, can be read to indicate the type of reset that just occurred. this is described in more detail in section 4.6 ?reset state of registers? . the rcon register also has control bits for setting interrupt priority (ipen) and software control of the bor (sboren). interrupt priority is discussed in section 10.0 ?interrupts? . bor is covered in section 4.4 ?brown-out reset (bor)? . figure 4-1: simplified block diagram of on-chip reset circuit external reset mclr v dd osc1 wdt time-out v dd rise detect ost/pwrt intrc (1) por pulse ost 10-bit ripple counter pwrt 11-bit ripple counter enable ost (2) enable pwrt note 1: this is the intrc source from the internal oscillator bl ock and is separate from the rc oscillator of the clki pin. 2: see table 4-2 for time-out situations. brown-out reset boren reset instruction stack pointer stack full/underflow reset sleep ( )_idle 1024 cycles 64 ms 31 s mclre s r q chip_reset
pic18f8722 family ds39646b-page 50 preliminary ? 2004 microchip technology inc. register 4-1: rcon: reset control re gister r/w-0 r/w-1 (1) u-0 r/w-1 r-1 r-1 r/w-0 (2) r/w-0 ipen sboren ?ri to pd por bor bit 7 bit 0 bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (pic16cxxx compatibility mode) bit 6 sboren: bor software enable bit (1) if boren1:boren0 = 0 1 : 1 = bor is enabled 0 = bor is disabled if boren1:boren0 = 00 , 10 or 11 : bit is disabled and read as ? 0 ?. bit 5 unimplemented: read as ? 0 ? bit 4 ri : reset instruction flag bit 1 = the reset instruction was not executed (set by firmware only) 0 = the reset instruction was executed causing a device reset (must be set in software after a brown-out reset occurs) bit 3 to : watchdog time-out flag bit 1 = set by power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 2 pd : power-down detection flag bit 1 = set by power-up or by the clrwdt instruction 0 = set by execution of the sleep instruction bit 1 por : power-on reset status bit (2) 1 = a power-on reset has not occurred (set by firmware only) 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = a brown-out reset has not occurred (set by firmware only) 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) note 1: if sboren is enabled, its reset state is ? 1 ?; otherwise, it is ? 0 ?. 2: the actual reset value of por is determined by the type of device reset. see the notes following this register and section 4.6 ?reset state of registers? for additional information. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown note 1: it is recommended that the por bit be set after a power-on reset has been detected so that subsequent power-on resets may be detected. 2: brown-out reset is said to have occurred when bor is ? 0 ? and por is ? 1 ? (assuming that por was set to ? 1 ? by software immediately after por).
? 2004 microchip technology inc. preliminary ds39646b-page 51 pic18f8722 family 4.2 master clear (mclr ) the mclr pin provides a method for triggering an external reset of the device. a reset is generated by holding the pin low. these devices have a noise filter in the mclr reset path which detects and ignores small pulses. the mclr pin is not driven low by any internal resets, including the wdt. in the pic18f8722 family of devices, the mclr input can be disabled with the mclre configuration bit. when mclr is disabled, the pin becomes a digital input. see section 11.5 ?porte, trise and late registers? for more information. 4.3 power-on reset (por) a power-on reset pulse is generated on-chip whenever v dd rises above a certain threshold. this allows the device to start in the initialized state when v dd is adequate for operation. to take advantage of the por circuitry, tie the mclr pin through a resistor (1 k ? to 10 k ? ) to v dd . this will eliminate external rc components usually needed to create a power-on reset delay. a minimum rise rate for v dd is specified (parameter d004, ?section 28.2 ?dc characteristics: power-down and supply current? ). for a slow rise time, see figure 4-2. when the device starts normal operation (i.e., exits the reset condition), device operating parameters (volt- age, frequency, temperature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. por events are captured by the por bit (rcon<1>). the state of the bit is set to ? 0 ? whenever a por occurs; it does not change for any other reset event. por is not reset to ? 1 ? by any hardware event. to capture multiple events, the user manually resets the bit to ? 1 ? in software following any por. figure 4-2: external power-on reset circuit (for slow v dd power-up) (1) note 1: external power-on reset circuit is required only if the v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k ? is recommended to make sure that the voltage drop across r does not violate the device?s electric al specification. 3: r1 1 k ? will limit any current flowing into mclr from external capacitor c, in the event of mclr /v pp pin breakdown, due to electrostatic discharge (esd) or electrical overstress (eos). c r1 (3) r (2) d v dd mclr pic18fxxxx v dd
pic18f8722 family ds39646b-page 52 preliminary ? 2004 microchip technology inc. 4.4 brown-out reset (bor) the pic18f8722 family of devices implements a bor circuit that provides the user with a number of con- figuration and power-saving options. the bor is con- trolled by the borv1:borv0 and boren1:boren0 configuration bits. there are a total of four bor configurations which are summarized in table 4-1. the bor threshold is set by the borv1:borv0 bits. if bor is enabled (any values of boren1:boren0, except ? 00 ?), any drop of v dd below v bor (parameter d005, section 28.1 ?dc characteristics? ) for greater than t bor (parameter 35, table 28-12) will reset the device. a reset may or may not occur if v dd falls below v bor for less than t bor . the chip will remain in brown-out reset until v dd rises above v bor . if the power-up timer is enabled, it will be invoked after v dd rises above v bor ; it then will keep the chip in reset for an additional time delay, t pwrt (parameter 33, table 28-12). if v dd drops below v bor while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be initialized. once v dd rises above v bor , the power-up timer will execute the additional time delay. bor and the power-on timer (pwrt) are independently configured. enabling bor reset does not automatically enable the pwrt. 4.4.1 software enabled bor when boren1:boren0 = 01 , the bor can be enabled or disabled by the user in software. this is done with the control bit, sboren (rcon<6>). setting sboren enables the bor to function as previously described. clearing sboren disables the bor entirely. the sboren bit operates only in this mode; otherwise it is read as ? 0 ?. placing the bor under software control gives the user the additional flexibility of tailoring the application to its environment without having to reprogram the device to change the bor configuration. it also allows the user to tailor device power consumption in software by eliminating the incremental current that the bor con- sumes. while the bor current is typically very small, it may have some impact in low-power applications. 4.4.2 detecting bor when bor is enabled, the bor bit always resets to ? 0 ? on any bor or por event. this makes it difficult to determine if a bor event has occurred just by reading the state of bor alone. a more reliable method is to simultaneously check the state of both por and bor . this assumes that the por bit is reset to ? 1 ? in software immediately after any por event. if bor is ? 0 ? while por is ? 1 ?, it can be reliably assumed that a bor event has occurred. 4.4.3 disabling bor in sleep mode when boren1:boren0 = 10 , the bor remains under hardware control and operates as previously described. whenever the device enters sleep mode, however, the bor is automatically disabled. when the device returns to any other operating mode, bor is automatically re-enabled. this mode allows for applications to recover from brown-out situations, while actively executing code, when the device requires bor protection the most. at the same time, it saves additional power in sleep mode by eliminating the small incremental bor current. table 4-1: bor configurations note: even when bor is under software control, the bor reset voltage level is still set by the borv1:borv0 configuration bits. it cannot be changed in software. bor configuration status of sboren (rcon<6>) bor operation boren1 boren0 00 unavailable bor disabled; must be enabled by reprogramming the configuration bits. 01 available bor enabled in software; operation controlled by sboren. 10 unavailable bor enabled in hardware in run and idle modes, disabled during sleep mode. 11 unavailable bor enabled in hardware; must be disabled by reprogramming the configuration bits.
? 2004 microchip technology inc. preliminary ds39646b-page 53 pic18f8722 family 4.5 device reset timers the pic18f8722 family of devices incorporates three separate on-chip timers that help regulate the power-on reset process. their main function is to ensure that the device clock is stable before code is executed. these timers are: power-up timer (pwrt) oscillator start-up timer (ost) pll lock time-out 4.5.1 power-up timer (pwrt) the power-up timer (pwrt) of the pic18f8722 family of devices is an 11-bit counter which uses the intrc source as the clock input. while the pwrt is counting, the device is held in reset. the power-up time delay depends on the intrc clock and will vary from chip-to-chip due to temperature and process variation. see dc parameter 33 in table 28-12 for details. the pwrt is enabled by clearing the pwrten configuration bit. 4.5.2 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides a 1024 oscillator cycle (from osc1 input) delay after the pwrt delay is over (parameter 33, table 28-12). this ensures that the crystal oscillator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp, hs and hspll modes and only on power-on reset, or on exit from most power-managed modes. 4.5.3 pll lock time-out with the pll enabled in its pll mode, the time-out sequence following a power-on reset is slightly differ- ent from other oscillator modes. a separate timer is used to provide a fixed time-out that is sufficient for the pll to lock to the main oscillator frequency. this pll lock time-out (t pll ) is typically 2 ms and follows the oscillator start-up time-out. 4.5.4 time-out sequence on power-up, the time-out sequence is as follows: 1. after the por pulse has cleared, pwrt time-out is invoked (if enabled). 2. then, the ost is activated. the total time-out will vary based on oscillator configu- ration and the status of the pwrt. figure 4-3, figure 4-4, figure 4-5, figure 4-6 and figure 4-7 all depict time-out sequences on power-up, with the power-up timer enabled and the device operating in hs oscillator mode. figures 4-3 through 4-6 also apply to devices operating in xt or lp modes. for devices in rc mode and with the pwrt disabled, on the other hand, there will be no time-out at all. since the time-outs occur from the por pulse, if mclr is kept low long enough, all time-outs will expire. bring- ing mclr high will begin execution immediately (figure 4-5). this is useful for testing purposes or to synchronize more than one pic18f8722 family device operating in parallel. table 4-2: time-out in various situations oscillator configuration power-up (2) and brown-out exit from power-managed mode pwrten = 0 pwrten = 1 hspll t pwrt (1) + 1024 t osc + t pll (2) 1024 t osc + t pll (2) 1024 t osc + t pll (2) hs, xt, lp t pwrt (1) + 1024 t osc 1024 t osc 1024 t osc ec, ecio t pwrt (1) ?? rc, rcio t pwrt (1) ?? intio1, intio2 t pwrt (1) ?? note 1: see parameter 33, table 28-12. 2: 2 ms is the nominal time required for the pll to lock.
pic18f8722 family ds39646b-page 54 preliminary ? 2004 microchip technology inc. figure 4-3: time-out sequence on power-up (mclr tied to v dd , v dd rise < t pwrt ) figure 4-4: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 4-5: time-out sequence on power-up (mclr not tied to v dd ): case 2 t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost
? 2004 microchip technology inc. preliminary ds39646b-page 55 pic18f8722 family figure 4-6: slow rise time (mclr tied to v dd , v dd rise > t pwrt ) figure 4-7: time-out sequence on por w/pll enabled (mclr tied to v dd ) v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset pll time-out t pll note: t ost = 1024 clock cycles. t pll 2 ms is the nominal time required for the pll to lock.
pic18f8722 family ds39646b-page 56 preliminary ? 2004 microchip technology inc. 4.6 reset state of registers most registers are unaffected by a reset. their status is unknown on por and unchanged by all other resets. all other registers are forced to a ?reset state? depending on the type of reset that occurred. most registers are not affected by a wdt wake-up, since this is viewed as the resumption of normal oper- ation. status bits from the rcon register, ri , to , pd , por and bor , are set or cleared differently in different reset situations, as indicated in table 4-3. these bits are used in software to determine the nature of the reset. table 4-4 describes the reset states for all of the special function registers. these are categorized by power-on and brown-out resets, master clear and wdt resets and wdt wake-ups. table 4-3: status bits, their significance and the initialization condition for rcon register condition program counter rcon register stkptr register sboren ri to pd por bor stkful stkunf power-on reset 0000h 1 11100 0 0 reset instruction 0000h u (2) 0uuuu u u brown-out reset 0000h u (2) 111u0 u u mclr during power-managed run modes 0000h u (2) u1uuu u u mclr during power-managed idle modes and sleep mode 0000h u (2) u10uu u u wdt time-out during full power or power-managed run mode 0000h u (2) u0uuu u u mclr during full power execution 0000h u (2) uuuuu u u stack full reset (stvren = 1 ) 0000h u (2) uuuuu 1 u stack underflow reset (stvren = 1 ) 0000h u (2) uuuuu u 1 stack underflow error (not an actual reset, stvren = 0 ) 0000h u (2) uuuuu u 1 wdt time-out during power-managed idle or sleep modes pc + 2 u (2) u00uu u u interrupt exit from power-managed modes pc + 2 (1) u (2) uu0uu u u legend: u = unchanged note 1: when the wake-up is due to an interrupt and the gieh or giel bits are set, the pc is loaded with the interrupt vector (008h or 0018h). 2: reset state is ? 1 ? for por and unchanged for all other resets when software bor is enabled (boren1:boren0 configuration bits = 01 and sboren = 1 ). otherwise, the reset state is ? 0 ?.
? 2004 microchip technology inc. preliminary ds39646b-page 57 pic18f8722 family table 4-4: initialization conditions for all registers register applicable devices power-on reset, brown-out reset mclr resets, wdt reset, reset instruction, stack resets wake-up via wdt or interrupt tosu 6x27 6x22 8x27 8x22 ---0 0000 ---0 0000 ---0 uuuu (3) tosh 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu (3) tosl 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu (3) stkptr 6x27 6x22 8x27 8x22 00-0 0000 uu-u uuuu uu-u uuuu (3) pclatu 6x27 6x22 8x27 8x22 ---0 0000 ---0 0000 ---u uuuu pclath 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu pcl 6x27 6x22 8x27 8x22 0000 0000 0000 0000 pc + 2 (2) tblptru 6x27 6x22 8x27 8x22 --00 0000 --00 0000 --uu uuuu tblptrh 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu tblptrl 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu tablat 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu prodh 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu prodl 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu intcon 6x27 6x22 8x27 8x22 0000 000x 0000 000u uuuu uuuu (1) intcon2 6x27 6x22 8x27 8x22 1111 1111 1111 1111 uuuu uuuu (1) intcon3 6x27 6x22 8x27 8x22 1100 0000 1100 0000 uuuu uuuu (1) indf0 6x27 6x22 8x27 8x22 n/a n/a n/a postinc0 6x27 6x22 8x27 8x22 n/a n/a n/a postdec0 6x27 6x22 8x27 8x22 n/a n/a n/a preinc0 6x27 6x22 8x27 8x22 n/a n/a n/a plusw0 6x27 6x22 8x27 8x22 n/a n/a n/a fsr0h 6x27 6x22 8x27 8x22 ---- 0000 ---- 0000 ---- uuuu fsr0l 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu wreg 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu indf1 6x27 6x22 8x27 8x22 n/a n/a n/a postinc1 6x27 6x22 8x27 8x22 n/a n/a n/a postdec1 6x27 6x22 8x27 8x22 n/a n/a n/a preinc1 6x27 6x22 8x27 8x22 n/a n/a n/a plusw1 6x27 6x22 8x27 8x22 n/a n/a n/a legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gi eh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 4-3 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled, depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read ? 0 ?.
pic18f8722 family ds39646b-page 58 preliminary ? 2004 microchip technology inc. fsr1h 6x27 6x22 8x27 8x22 ---- 0000 ---- 0000 ---- uuuu fsr1l 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu bsr 6x27 6x22 8x27 8x22 ---- 0000 ---- 0000 ---- uuuu indf2 6x27 6x22 8x27 8x22 n/a n/a n/a postinc2 6x27 6x22 8x27 8x22 n/a n/a n/a postdec2 6x27 6x22 8x27 8x22 n/a n/a n/a preinc2 6x27 6x22 8x27 8x22 n/a n/a n/a plusw2 6x27 6x22 8x27 8x22 n/a n/a n/a fsr2h 6x27 6x22 8x27 8x22 ---- 0000 ---- 0000 ---- uuuu fsr2l 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu status 6x27 6x22 8x27 8x22 ---x xxxx ---u uuuu ---u uuuu tmr0h 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu tmr0l 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu t0con 6x27 6x22 8x27 8x22 1111 1111 1111 1111 uuuu uuuu osccon 6x27 6x22 8x27 8x22 0100 q000 0100 q000 uuuu uuqu hlvdcon 6x27 6x22 8x27 8x22 0-00 0101 0-00 0101 u-uu uuuu wdtcon 6x27 6x22 8x27 8x22 ---- ---0 ---- ---0 ---- ---u rcon (4) 6x27 6x22 8x27 8x22 0q-1 11q0 0q-q qquu uq-u qquu tmr1h 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu tmr1l 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu t1con 6x27 6x22 8x27 8x22 0000 0000 u0uu uuuu uuuu uuuu tmr2 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu pr2 6x27 6x22 8x27 8x22 1111 1111 uuuu uuuu uuuu uuuu t2con 6x27 6x22 8x27 8x22 -000 0000 -000 0000 -uuu uuuu ssp1buf 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu ssp1add 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu ssp1stat 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu ssp1con1 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu ssp1con2 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu table 4-4: initialization conditi ons for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets, wdt reset, reset instruction, stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gi eh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 4-3 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled, depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read ? 0 ?.
? 2004 microchip technology inc. preliminary ds39646b-page 59 pic18f8722 family adresh 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu adresl 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu adcon0 6x27 6x22 8x27 8x22 --00 0000 --00 0000 --uu uuuu adcon1 6x27 6x22 8x27 8x22 --00 0000 --00 0000 --uu uuuu adcon2 6x27 6x22 8x27 8x22 0-00 0000 0-00 0000 u-uu uuuu ccpr1h 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu ccpr1l 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu ccp1con 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu ccpr2h 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu ccpr2l 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu ccp2con 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu ccpr3h 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu ccpr3l 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu ccp3con 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu eccp1as 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu cvrcon 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu cmcon 6x27 6x22 8x27 8x22 0000 0111 0000 0111 uuuu uuuu tmr3h 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu tmr3l 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu t3con 6x27 6x22 8x27 8x22 0000 0000 uuuu uuuu uuuu uuuu pspcon 6x27 6x22 8x27 8x22 0000 ---- 0000 ---- uuuu ---- spbrg1 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu rcreg1 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu txreg1 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu txsta1 6x27 6x22 8x27 8x22 0000 0010 0000 0010 uuuu uuuu rcsta1 6x27 6x22 8x27 8x22 0000 000x 0000 000x uuuu uuuu eeadrh 6x27 6x22 8x27 8x22 ---- --00 ---- --00 ---- --uu eeadr 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu eedata 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu eecon2 6x27 6x22 8x27 8x22 0000 0000 0000 0000 0000 0000 eecon1 6x27 6x22 8x27 8x22 xx-0 x000 uu-0 u000 uu-u uuuu table 4-4: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets, wdt reset, reset instruction, stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gi eh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 4-3 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled, depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read ? 0 ?.
pic18f8722 family ds39646b-page 60 preliminary ? 2004 microchip technology inc. ipr3 6x27 6x22 8x27 8x22 1111 1111 1111 1111 uuuu uuuu pir3 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu (1) pie3 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu ipr2 6x27 6x22 8x27 8x22 11-1 1111 11-1 1111 uu-u uuuu pir2 6x27 6x22 8x27 8x22 00-0 0000 00-0 0000 uu-u uuuu (1) pie2 6x27 6x22 8x27 8x22 00-0 0000 00-0 0000 uu-u uuuu ipr1 6x27 6x22 8x27 8x22 1111 1111 1111 1111 uuuu uuuu pir1 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu (1) pie1 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu memcon 6x27 6x22 8x27 8x22 0-00 --00 0-00 --00 u-uu --uu osctune 6x27 6x22 8x27 8x22 00-0 0000 00-0 0000 uu-u uuuu trisj 6x27 6x22 8x27 8x22 1111 1111 1111 1111 uuuu uuuu trish 6x27 6x22 8x27 8x22 1111 1111 1111 1111 uuuu uuuu trisg 6x27 6x22 8x27 8x22 ---1 1111 ---1 1111 ---u uuuu trisf 6x27 6x22 8x27 8x22 1111 1111 1111 1111 uuuu uuuu trise 6x27 6x22 8x27 8x22 1111 1111 1111 1111 uuuu uuuu trisd 6x27 6x22 8x27 8x22 1111 1111 1111 1111 uuuu uuuu trisc 6x27 6x22 8x27 8x22 1111 1111 1111 1111 uuuu uuuu trisb 6x27 6x22 8x27 8x22 1111 1111 1111 1111 uuuu uuuu trisa (5) 6x27 6x22 8x27 8x22 1111 1111 (5) 1111 1111 (5) uuuu uuuu (5) latj 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu lath 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu latg 6x27 6x22 8x27 8x22 --xx xxxx --uu uuuu --uu uuuu latf 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu late 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu latd 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu latc 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu latb 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu lata (5) 6x27 6x22 8x27 8x22 xxxx xxxx (5) uuuu uuuu (5) uuuu uuuu (5) portj 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu porth 6x27 6x22 8x27 8x22 0000 xxxx uuuu uuuu uuuu uuuu portg 6x27 6x22 8x27 8x22 --xx xxxx --uu uuuu --uu uuuu portf 6x27 6x22 8x27 8x22 x000 0000 u000 0000 uuuu uuuu porte 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu portd 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu portc 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu portb 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu table 4-4: initialization conditi ons for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets, wdt reset, reset instruction, stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gi eh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 4-3 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled, depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read ? 0 ?.
? 2004 microchip technology inc. preliminary ds39646b-page 61 pic18f8722 family porta (5) 6x27 6x22 8x27 8x22 xx0x 0000 (5) uu0u 0000 (5) uuuu uuuu (5) spbrgh1 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu baudcon1 6x27 6x22 8x27 8x22 01-0 0-00 01-0 0-00 uu-u u-uu spbrgh2 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu baudcon2 6x27 6x22 8x27 8x22 01-0 0-00 01-0 0-00 uu-u u-uu eccp1del 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu tmr4 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu pr4 6x27 6x22 8x27 8x22 1111 1111 uuuu uuuu uuuu uuuu t4con 6x27 6x22 8x27 8x22 -000 0000 -000 0000 -uuu uuuu ccpr4h 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu ccpr4l 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu ccp4con 6x27 6x22 8x27 8x22 --00 0000 --00 0000 --uu uuuu ccpr5h 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu ccpr5l 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu ccp5con 6x27 6x22 8x27 8x22 --00 0000 --00 0000 --uu uuuu spbrg2 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu rcreg2 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu txreg2 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu txsta2 6x27 6x22 8x27 8x22 0000 0010 0000 0010 uuuu uuuu rcsta2 6x27 6x22 8x27 8x22 0000 000x 0000 000x uuuu uuuu eccp3as 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu eccp3del 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu eccp2as 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu eccp2del 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu ssp2buf 6x27 6x22 8x27 8x22 xxxx xxxx uuuu uuuu uuuu uuuu ssp2add 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu ssp2stat 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu ssp2con1 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu ssp2con2 6x27 6x22 8x27 8x22 0000 0000 0000 0000 uuuu uuuu table 4-4: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets, wdt reset, reset instruction, stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gi eh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 4-3 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled, depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read ? 0 ?.
pic18f8722 family ds39646b-page 62 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39646b-page 63 pic18f8722 family 5.0 memory organization there are three types of memory in pic18 enhanced microcontroller devices: program memory data ram data eeprom as harvard architecture devices, the data and program memories use separate busses; this allows for concur- rent access of the two memory spaces. the data eeprom, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed through a set of control registers. additional detailed information on the operation of the flash program memory is provided in section 6.0 ?flash program memory? . data eeprom is discussed separately in section 8.0 ?data eeprom memory? . 5.1 program memory organization pic18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-mbyte program memory space. accessing a location between the upper boundary of the physically implemented memory and the 2-mbyte address will return all ? 0 ?s (a nop instruction). the pic18f6527 and pic18f8527 each have 48 kbytes of flash memory and can store up to 24,576 single-word instructions. the pic18f6622 and pic18f8622 each have 64 kbytes of flash memory and can store up to 32,768 single-word instructions. the pic18f6627 and pic18f8627 each have 96 kbytes of flash memory and can store up to 49,152 single-word instructions. the pic18f6722 and pic18f8722 each have 128 kbytes of flash memory and can store up to 65,536 single-word instructions. pic18 devices have two interrupt vectors. the reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. the program memory map for the pic18f8722 family of devices is shown in figure 5-1. 5.1.1 pic18f8527/8622/8627/8722 program memory modes pic18f8527/8622/8627/8722 devices differ signifi- cantly from their pic18 predecessors in their utilization of program memory. in addition to available on-chip flash program memory, these controllers can also address up to 2 mbytes of external program memory through the external memory interface. there are four distinct operating modes available to the controllers: microprocessor (mp) microprocessor with boot block (mpbb) extended microcontroller (emc) microcontroller (mc) the program memory mode is determined by setting the two least significant bits of the configuration register 3l (config3l) as shown in register 25-4 (see section 25.1 ?configuration bits? for additional details on the device configuration bits). the program memory modes operate as follows: the microprocessor mode permits access only to external program memory; the contents of the on-chip flash memory are ignored. the 21-bit program counter permits access to a 2-mbyte linear program memory space. the microprocessor with boot block mode accesses on-chip flash memory from the boot block. above this, external program memory is accessed all the way up to the 2-mbyte limit. program execution automatically switches between the two memories as required. the boot block is configurable to 1, 2 or 4 kbytes. the microcontroller mode accesses only on-chip flash memory. attempts to read above the physical limit of the on-chip flash (0bfffh for the pic18f8527, 0ffffh for the pic18f8622, 17fffh for the pic18f8627, 1ffffh for the pic18f8722) causes a read of all ? 0 ?s (a nop instruction). the microcontroller mode is also the only operating mode available to pic18f6527/6622/6627/6722 devices. the extended microcontroller mode allows access to both internal and external program memories as a single block. the device can access its entire on-chip flash memory; above this, the device accesses external program memory up to the 2-mbyte program space limit. as with boot block mode, execution automatically switches between the two memories as required. in all modes, the microcontroller has complete access to data ram and eeprom. figure 5-2 compares the memory maps of the different program memory modes. the differences between on-chip and external memory access limitations are more fully explained in table 5-1.
pic18f8722 family ds39646b-page 64 preliminary ? 2004 microchip technology inc. figure 5-1: program memory map and stack for pic18f8722 family devices table 5-1: memory access for pic18f8527/8622/8627/8722 program memory modes pc<20:0> stack level 1 ? stack level 31 reset vector ? ? call,rcall,return retfie,retlw 21 0000h 0018h on-chip program memory high priority interrupt vector 0008h user memory space 01ffffh 018000h 017fffh 1fffffh pic18fx627 pic18fx722 on-chip program memory read ? 0 ? on-chip program memory 0c000h 0bfffh pic18fx527 pic18fx622 on-chip program memory read ? 0 ? low priority interrupt vector read ? 0 ? 10000h 0ffffh operating mode internal program memory external program memory execution from table read from table write to execution from table read from table write to microprocessor no access no access no access yes yes yes microprocessor w/ boot block ye s yes yes yes yes yes microcontroller yes yes yes no access no access no access extended microcontroller ye s yes yes yes yes yes
? 2004 microchip technology inc. preliminary ds39646b-page 65 pic18f8722 family figure 5-2: memory maps for pic18f8722 family program memory modes microprocessor mode 000000h 1fffffh external program memory external program memory 1fffffh 000000h on-chip program memory extended microcontroller mode microcontroller mode (5) 000000h external on-chip program space execution on-chip program memory 1fffffh reads 000800h (6) or 1fffffh 0007ffh (6) or microprocessor with boot block mode 000000h on-chip program memory external program memory memory flash on-chip program memory (no access) ? 0 ?s external on-chip memory flash on-chip flash external on-chip memory flash 0ffffh (2) 0bfffh (1) 01ffffh (4) 017fffh (3) note 1: pic18f6527 and pic18f8527. 2: pic18f6622 and pic18f8622. 3: pic18f6627 and pic18f8627. 4: pic18f6722 and pic18f8722. 5: this is the only mode available on pic18f6527/6622/6627/6722 devices. 6: boot block size is determined by the bbsiz<1:0> bits in config4l. 000fffh (6) or 001fffh (6) 001000h (6) or 002000h (6) 010000h (2) 0c000h (1) 020000h (4) 018000h (3) 0ffffh (2) 0bfffh (1) 01ffffh (4) 017fffh (3) 010000h (2) 0c000h (1) 020000h (4) 018000h (3)
pic18f8722 family ds39646b-page 66 preliminary ? 2004 microchip technology inc. 5.1.2 program counter the program counter (pc) specifies the address of the instruction to fetch for execution. the pc is 21 bits wide and is contained in three separate 8-bit registers. the low byte, known as the pcl register, is both readable and writable. the high byte, or pch register, contains the pc<15:8> bits; it is not directly readable or writable. updates to the pch register are performed through the pclath register. the upper byte is called pcu. this register contains the pc<20:16> bits; it is also not directly readable or writable. updates to the pcu register are performed through the pclatu register. the contents of pclath and pclatu are transferred to the program counter by any operation that writes pcl. similarly, the upper two bytes of the program counter are transferred to pclath and pclatu by an operation that reads pcl. this is useful for computed offsets to the pc (see section 5.1.5.1 ?computed goto? ). the pc addresses bytes in the program memory. to prevent the pc from becoming misaligned with word instructions, the least significant bit of pcl is fixed to a value of ? 0 ?. the pc increments by 2 to address sequential instructions in the program memory. the call , rcall , goto and program branch instructions write to the program counter directly. for these instructions, the contents of pclath and pclatu are not transferred to the program counter. 5.1.3 return address stack the return address stack allows any combination of up to 31 program calls and interrupts to occur. the pc is pushed onto the stack when a call or rcall instruc- tion is executed or an interrupt is acknowledged. the pc value is pulled off the stack on a return, retlw or a retfie instruction. pclatu and pclath are not affected by any of the return or call instructions. the stack operates as a 31-word by 21-bit ram and a 5-bit stack pointer, stkptr. the stack space is not part of either program or data space. the stack pointer is readable and writable and the address on the top of the stack is readable and writable through the top-of- stack special file registers. data can also be pushed to, or popped from the stack, using these registers. a call type instruction causes a push onto the stack; the stack pointer is first incremented and the location pointed to by the stack pointer is written with the contents of the pc (already pointing to the instruction following the call ). a return type instruction causes a pop from the stack; the contents of the location pointed to by the stkptr are transferred to the pc and then the stack pointer is decremented. the stack pointer is initialized to ? 00000 ? after all resets. there is no ram associated with the location corresponding to a stack pointer value of ? 00000 ?; this is only a reset value. status bits indicate if the stack is full or has overflowed or has underflowed. 5.1.3.1 top-of-stack access only the top of the return address stack (tos) is readable and writable. a set of three registers, tosu:tosh:tosl, hold the contents of the stack loca- tion pointed to by the stkptr register (figure 5-3). this allows users to implement a software stack if necessary. after a call, rcall or interrupt, the software can read the pushed value by reading the tosu:tosh:tosl registers. these values can be placed on a user defined software stack. at return time, the software can return these values to tosu:tosh:tosl and do a return. the user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. figure 5-3: return address stack and associated registers 00011 001a34h 11111 11110 11101 00010 00001 00000 00010 return address stack <20:0> to p - o f - st a c k 000d58h tosl tosh tosu 34h 1ah 00h stkptr<4:0> top-of-stack registers stack pointer
? 2004 microchip technology inc. preliminary ds39646b-page 67 pic18f8722 family 5.1.3.2 return stack pointer (stkptr) the stkptr register (register 5-1) contains the stack pointer value, the stkful (stack full) status bit and the stkunf (stack underflow) status bits. the value of the stack pointer can be 0 through 31. the stack pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. on reset, the stack pointer value will be zero. the user may read and write the stack pointer value. this feature can be used by a real-time operating system (rtos) for return stack maintenance. after the pc is pushed onto the stack 31 times (without popping any values off the stack), the stkful bit is set. the stkful bit is cleared by software or by a por. the action that takes place when the stack becomes full depends on the state of the stvren (stack over- flow reset enable) configuration bit. (refer to section 25.1 ?configuration bits? for a description of the device configuration bits.) if stvren is set (default), the 31st push will push the (pc + 2) value onto the stack, set the stkful bit and reset the device. the stkful bit will remain set and the stack pointer will be set to zero. if stvren is cleared, the stkful bit will be set on the 31st push and the stack pointer will increment to 31. any additional pushes will not overwrite the 31st push and stkptr will remain at 31. when the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the pc and set the stkunf bit, while the stack pointer remains at zero. the stkunf bit will remain set until cleared by software or until a por occurs. 5.1.3.3 push and pop instructions since the top-of-stack is readable and writable, the ability to push values onto the stack and pull values off the stack without disturbing normal program execution is a desirable feature. the pic18 instruction set includes two instructions, push and pop , that permit the tos to be manipulated under software control. tosu, tosh and tosl can be modified to place data or a return address on the stack. the push instruction places the current pc value onto the stack. this increments the stack pointer and loads the current pc value onto the stack. the pop instruction discards the current tos by decre- menting the stack pointer. the previous value pushed onto the stack then becomes the tos value. register 5-1: stkptr: stack pointer register note: returning a value of zero to the pc on an underflow has the effect of vectoring the program to the reset vector, where the stack conditions can be verified and appropriate actions can be taken. this is not the same as a reset, as the contents of the sfrs are not affected. r/c-0 r/c-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stkful (1) stkunf (1) ? sp4 sp3 sp2 sp1 sp0 bit 7 bit 0 bit 7 stkful: stack full flag bit (1) 1 = stack became full or overflowed 0 = stack has not become full or overflowed bit 6 stkunf: stack underflow flag bit (1) 1 = stack underflow occurred 0 = stack underflow did not occur bit 5 unimplemented: read as ? 0 ? bit 4-0 sp4:sp0: stack pointer location bits note 1: bit 7 and bit 6 are cleared by user software or by a por. legend: r = readable bit w = writable bit u = unimplemented c = clearable only bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 68 preliminary ? 2004 microchip technology inc. 5.1.3.4 stack full and underflow resets device resets on stack overflow and stack underflow conditions are enabled by setting the stvren bit in configuration register 4l. when stvren is set, a full or underflow will set the appropriate stkful or stkunf bit and then cause a device reset. when stvren is cleared, a full or underflow condition will set the appropriate stkful or stkunf bit, but not cause a device reset. the stkful or stkunf bits are cleared by the user software or a power-on reset. 5.1.4 fast register stack a fast register stack is provided for the status, wreg and bsr registers, to provide a ?fast return? option for interrupts. the stack for each register is only one level deep and is neither readable nor writable. it is loaded with the current value of the corresponding register when the processor vectors for an interrupt. all inter- rupt sources will push values into the stack registers. the values in the registers are then loaded back into their associated registers if the retfie, fast instruction is used to return from the interrupt. if both low and high priority interrupts are enabled, the stack registers cannot be used reliably to return from low priority interrupts. if a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. in these cases, users must save the key registers in software during a low priority interrupt. if interrupt priority is not used, all interrupts may use the fast register stack for returns from interrupt. if no inter- rupts are used, the fast register stack can be used to restore the status, wreg and bsr registers at the end of a subroutine call. to use the fast register stack for a subroutine call, a call label , fast instruction must be executed to save the status, wreg and bsr registers to the fast register stack. a return , fast instruction is then executed to restore these registers from the fast register stack. example 5-1 shows a source code example that uses the fast register stack during a subroutine call and return. example 5-1: fast register stack code example 5.1.5 look-up tables in program memory there may be programming situations that require the creation of data structures, or look-up tables, in program memory. for pic18 devices, look-up tables can be implemented in two ways: computed goto table reads 5.1.5.1 computed goto a computed goto is accomplished by adding an offset to the program counter. an example is shown in example 5-2. a look-up table can be formed with an addwf pcl instruction and a group of retlw nn instructions. the w register is loaded with an offset into the table before exe- cuting a call to that table. the first instruction of the called routine is the addwf pcl instruction. the next instruction executed will be one of the retlw nn instructions that returns the value ? nn ? to the calling function. the offset value (in wreg) specifies the number of bytes that the program counter should advance and should be multiples of 2 (lsb = 0 ). in this method, only one data byte may be stored in each instruction location and room on the return address stack is required. example 5-2: computed goto using an offset value note: the ? addwf pcl ? instruction does not update the pclath and pclatu registers. a read operation on pcl must be performed to update pclath and pclatu. call sub1, fast ;status, wreg, bsr ;saved in fast register ;stack ? ? sub1 ? ? return, fast ;restore values saved ;in fast register stack main: org 0x0000 movlw 0x00 call table ? org 0x8000 table movf pcl, f ; a simple read of pcl will update pclath, pclatu rlncf w, w ; multiply by 2 to get correct offset in table addwf pcl ; add the modified offset to force jump into table retlw ?a? retlw ?b? retlw ?c? retlw ?d? retlw ?e? end
? 2004 microchip technology inc. preliminary ds39646b-page 69 pic18f8722 family 5.1.5.2 table reads and table writes a better method of storing data in program memory allows two bytes of data to be stored in each instruction location. look-up table data may be stored two bytes per pro- gram word by using table reads and writes. the table pointer (tblptr) register specifies the byte address and the table latch (tablat) register contains the data that is read from or written to program memory. data is transferred to or from program memory one byte at a time. table read and table write operations are discussed further in section 6.1 ?table reads and table writes? . 5.2 pic18 instruction cycle 5.2.1 clocking scheme the microcontroller clock input, whether from an internal or external source, is internally divided by four to gener- ate four non-overlapping quadr ature clocks (q1, q2, q3 and q4). internally, the program counter is incremented on every q1; the instruction is fetched from the program memory and latched into the instruction register during q4. the instruction is decoded and executed during the following q1 through q4. the clocks and instruction execution flow are shown in figure 5-4. 5.2.2 instruction flow/pipelining an ?instruction cycle? consists of four q cycles: q1 through q4. the instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. however, due to the pipe- lining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ), then two cycles are required to complete the instruction (example 5-3). a fetch cycle begins with the program counter incrementing in q1. in the execution cycle, the fetched instruction is latched into the instruction register (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3 and q4 cycles. data memory is read during q2 figure 5-4: clock/ instruction cycle example 5-3: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clko (rc mode) pc pc + 2 pc + 4 fetch inst (pc) execute inst (pc ? 2) fetch inst (pc + 2) execute inst (pc) fetch inst (pc + 4) execute inst (pc + 2) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles since the fetch instruction is ?flushed? from the pipeline while the new instruction is being fetched and then executed. t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. bra sub_1 fetch 3 execute 3 4. bsf porta, bit3 (forced nop) fetch 4 flush ( nop ) 5. instruction @ address sub_1 fetch sub_1 execute sub_1
pic18f8722 family ds39646b-page 70 preliminary ? 2004 microchip technology inc. 5.2.3 instructions in program memory the program memory is addressed in bytes. instruc- tions are stored as two bytes or four bytes in program memory. the least significant byte of an instruction word is always stored in a program memory location with an even address (lsb = 0 ). to maintain alignment with instruction boundaries, the pc increments in steps of 2 and the lsb will always read ? 0 ? (see section 5.1.2 ?program counter? ). figure 5-5 shows an example of how instruction words are stored in the program memory. the call and goto instructions have the absolute pro- gram memory address embedded into the instruction. since instructions are always stored on word bound- aries, the data contained in the instruction is a word address. the word address is written to pc<20:1>, which accesses the desired byte address in program memory. instruction #2 in figure 5-5 shows how the instruction goto 0006h is encoded in the program memory. program branch instructions, which encode a relative address offset, operate in the same manner. the offset value stored in a br anch instruction represents the number of single-word instructions that the pc will be offset by. section 26.0 ?instruction set summary? provides further details of the instruction set. figure 5-5: instructions in program memory word address lsb = 1 lsb = 0 program memory byte locations 000000h 000002h 000004h 000006h instruction 1: movlw 055h 0fh 55h 000008h instruction 2: goto 0006h efh 03h 00000ah f0h 00h 00000ch instruction 3: movff 123h, 456h c1h 23h 00000eh f4h 56h 000010h 000012h 000014h
? 2004 microchip technology inc. preliminary ds39646b-page 71 pic18f8722 family 5.2.4 two-word instructions the standard pic18 instruction set has 8 two-word instructions: call , movff , goto , lsfr, addulnk, callw, movss and subulnk . in all cases, the second word of the instructions always has ? 1111 ? as its four most significant bits; the other 12 bits are literal data, usually a data memory address. the use of ? 1111 ? in the 4 msbs of an instruction spec- ifies a special form of nop . if the instruction is executed in proper sequence ? immediately after the first word ? the data in the second word is accessed and used by the instruction sequence. if the first word is skipped for some reason and the second word is executed by itself, a nop is executed instead. this is necessary for cases when the two-word instruction is preceded by a condi- tional instruction that changes the pc. example 5-4 shows how this works. example 5-4: two-word instructions note: see section 5.6 ?pic18 instruction execution and the extended instruc- tion set? for information on two-word instructions in the extended instruction set. case 1: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; no, skip this word 1111 0100 0101 0110 ; execute this word as a nop 0010 0100 0000 0000 addwf reg3 ; continue code case 2: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 addwf reg3 ; continue code
pic18f8722 family ds39646b-page 72 preliminary ? 2004 microchip technology inc. 5.3 data memory organization the data memory in pic18 devices is implemented as static ram. each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. the memory space is divided into as many as 16 banks that contain 256 bytes each; the pic18f8722 family of devices implements all 16 banks. figure 5-6 shows the data memory organization for the pic18f8722 family of devices. the data memory contains special function registers (sfrs) and general purpose registers (gprs). the sfrs are used for control and status of the controller and peripheral functions, while gprs are used for data storage and scratchpad operations in the user?s application. any read of an unimplemented location will read as ? 0 ?s. the instruction set and architecture allow operations across all banks. the entire data memory may be accessed by direct, indirect or indexed addressing modes. addressing modes are discussed later in this subsection. to ensure that commonly used registers (sfrs and select gprs) can be accessed in a single cycle, pic18 devices implement an access bank. this is a 256-byte memory space that provides fast access to sfrs and the lower portion of gpr bank 0 without using the bsr. section 5.3.2 ?access bank? provides a detailed description of the access ram. 5.3.1 bank select register (bsr) large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. ideally, this means that an entire address does not need to be provided for each read or write operation. for pic18 devices, this is accom- plished with a ram banking scheme. this divides the memory space into 16 contiguous banks of 256 bytes. depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit bank pointer. most instructions in the pic18 instruction set make use of the bank pointer, known as the bank select register (bsr). this sfr holds the 4 most significant bits of a location?s address; the instruction itself includes the 8 least significant bits. only the four lower bits of the bsr are implemented (bsr3:bsr0). the upper four bits are unused; they will always read ? 0 ? and cannot be written to. the bsr can be loaded directly by using the movlb instruction. the value of the bsr indicates the bank in data memory; the 8 bits in the instruction show the location in the bank and can be thought of as an offset from the bank?s lower boundary. the relationship between the bsr?s value and the bank division in data memory is shown in figure 5-7. since up to 16 registers may share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. for example, writing what should be program data to an 8-bit address of f9h while the bsr is 0fh will end up resetting the program counter. while any bank can be selected, only those banks that are actually implemented can be read or written to. writes to unimplemented banks are ignored, while reads from unimplemented banks will return ? 0 ?s. even so, the status register will still be affected as if the operation was successful. the data memory map in figure 5-6 indicates which banks are implemented. in the core pic18 instruction set, only the movff instruction fully specifies the 12-bit address of the source and target registers. this instruction ignores the bsr completely when it executes. all other instructions include only the low-order address as an operand and must use either the bsr or the access bank to locate their target registers. note: the operation of some aspects of data memory are changed when the pic18 extended instruction set is enabled. see section 5.5 ?data memory and the extended instruction set? for more information.
? 2004 microchip technology inc. preliminary ds39646b-page 73 pic18f8722 family figure 5-6: data memory map for the pic18f8722 family of devices bank 0 bank 1 bank 14 bank 15 data memory map bsr<3:0> = 0000 = 0001 = 1111 060h 05fh f60h fffh 00h 5fh 60h ffh access bank when ?a? = 0 : the bsr is ignored and the access bank is used. the first 96 bytes are general purpose ram (from bank 0). the second 160 bytes are special function registers (from bank 15). when ?a? = 1 : the bsr specifies the bank used by the instruction. f5fh f00h effh 1ffh 100h 0ffh 000h access ram ffh 00h ffh 00h ffh 00h gpr gpr sfr access ram high access ram low bank 2 = 0110 = 0010 (sfrs) 2ffh 200h 3ffh 300h 4ffh 400h 5ffh 500h 6ffh 600h 7ffh 700h 8ffh 800h 9ffh 900h affh a00h bffh b00h cffh c00h dffh d00h e00h bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 bank 9 bank 10 bank 11 bank 12 bank 13 ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h gpr ffh 00h = 0011 = 0100 = 0101 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 gpr gpr gpr gpr gpr gpr gpr gpr gpr gpr gpr gpr gpr
pic18f8722 family ds39646b-page 74 preliminary ? 2004 microchip technology inc. figure 5-7: use of the bank select register (direct addressing) 5.3.2 access bank while the use of the bsr with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. otherwise, data may be read from or written to the wrong location. this can be disastrous if a gpr is the intended target of an operation, but an sfr is written to instead. verifying and/or changing the bsr for each read or write to data memory can become very inefficient. to streamline access for the most commonly used data memory locations, the data memory is configured with an access bank, which allows users to access a mapped block of memory without specifying a bsr. the access bank consists of the first 96 bytes of memory (00h-5fh) in bank 0 and the last 160 bytes of memory (60h-ffh) in block 15. the lower half is known as the ?access ram? and is composed of gprs. this upper half is also where the device?s sfrs are mapped. these two areas are mapped contiguously in the access bank and can be addressed in a linear fashion by an 8-bit address (figure 5-6). the access bank is used by core pic18 instructions that include the access ram bit (the ?a? parameter in the instruction). when ?a? is equal to ? 1 ?, the instruction uses the bsr and the 8-bit address included in the opcode for the data memory address. when ?a? is ? 0 ?, however, the instruction is forced to use the access bank address map; the current value of the bsr is ignored entirely. using this ?forced? addressing allows the instruction to operate on a data address in a single cycle, without updating the bsr first. for 8-bit addresses of 60h and above, this means that users can evaluate and operate on sfrs more efficiently. the access ram below 60h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. access ram also allows for faster and more code efficient context saving and switching of variables. the mapping of the access bank is slightly different when the extended instruction set is enabled (xinst configuration bit = 1 ). this is discussed in more detail in section 5.5.3 ?mapping the access bank in indexed literal offset mode? . 5.3.3 general purpose register file pic18 devices may have banked memory in the gpr area. this is data ram, which is available for use by all instructions. gprs start at the bottom of bank 0 (address 000h) and grow upwards towards the bottom of the sfr area. gprs are not initialized by a power-on reset and are unchanged on all other resets. note 1: the access ram bit of the instruction can be used to force an override of the selected bank (bsr<3:0>) to the registers of the access bank. 2: the movff instruction embeds the entire 12-bit address in the instruction. data memory bank select (2) 7 0 from opcode (2) 0000 000h 100h 200h 300h f00h e00h fffh bank 0 bank 1 bank 2 bank 14 bank 15 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh bank 3 through bank 13 0011 11111111 7 0 bsr (1)
? 2004 microchip technology inc. preliminary ds39646b-page 75 pic18f8722 family 5.3.4 special function registers the special function registers (sfrs) are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. sfrs start at the top of data memory (fffh) and extend downward to occupy the top half of bank 15 (f60h to fffh). a list of these registers is given in table 5-2 and table 5-3. the sfrs can be classified into two sets: those associated with the ?core? device functionality (alu, resets and interrupts) and those related to the peripheral functions. the reset and interrupt registers are described in their respective chapters, while the alu?s status register is described later in this sec- tion. registers related to the operation of a peripheral feature are described in the chapter for that peripheral. the sfrs are typically distributed among the peripherals whose functions they control. unused sfr locations are unimplemented and read as ? 0 ?s. table 5-2: special function register map for the pic18f8722 family of devices address name address name address name address name address name fffh tosu fdfh indf2 (1) fbfh ccpr1h f9fh ipr1 f7fh spbrgh1 ffeh tosh fdeh postinc2 (1) fbeh ccpr1l f9eh pir1 f7eh baudcon1 ffdh tosl fddh postdec2 (1) fbdh ccp1con f9dh pie1 f7dh spbrgh2 ffch stkptr fdch preinc2 (1) fbch ccpr2h f9ch memcon f7ch baudcon2 ffbh pclatu fdbh plusw2 (1) fbbh ccpr2l f9bh osctune f7bh ? (2) ffah pclath fdah fsr2h fbah ccp2con f9ah trisj (3) f7ah ? (2) ff9h pcl fd9h fsr2l fb9h ccpr3h f99h trish (3) f79h eccp1del ff8h tblptru fd8h status fb8h ccpr3l f98h trisg f78h tmr4 ff7h tblptrh fd7h tmr0h fb7h ccp3con f97h trisf f77h pr4 ff6h tblptrl fd6h tmr0l fb6h eccp1as f96h trise f76h t4con ff5h tablat fd5h t0con fb5h cvrcon f95h trisd f75h ccpr4h ff4h prodh fd4h ? (2) fb4h cmcon f94h trisc f74h ccpr4l ff3h prodl fd3h osccon fb3h tmr3h f93h trisb f73h ccp4con ff2h intcon fd2h hlvdcon fb2h tmr3l f92h trisa f72h ccpr5h ff1h intcon2 fd1h wdtcon fb1h t3con f91h latj (3) f71h ccpr5l ff0h intcon3 fd0h rcon fb0h pspcon f90h lath (3) f70h ccp5con fefh indf0 (1) fcfh tmr1h fafh spbrg1 f8fh latg f6fh spbrg2 feeh postinc0 (1) fceh tmr1l faeh rcreg1 f8eh latf f6eh rcreg2 fedh postdec0 (1) fcdh t1con fadh txreg1 f8dh late f6dh txreg2 fech preinc0 (1) fcch tmr2 fach txsta1 f8ch latd f6ch txsta2 febh plusw0 (1) fcbh pr2 fabh rcsta1 f8bh latc f6bh rcsta2 feah fsr0h fcah t2con faah eeadrh f8ah latb f6ah eccp3as fe9h fsr0l fc9h ssp1buf fa9h eeadr f89h lata f69h eccp3del fe8h wreg fc8h ssp1add fa8h eedata f88h portj (3) f68h eccp2as fe7h indf1 (1) fc7h ssp1stat fa7h eecon2 (1) f87h porth (3) f67h eccp2del fe6h postinc1 (1) fc6h ssp1con1 fa6h eecon1 f86h portg f66h ssp2buf fe5h postdec1 (1) fc5h ssp1con2 fa5h ipr3 f85h portf f65h ssp2add fe4h preinc1 (1) fc4h adresh fa4h pir3 f84h porte f64h ssp2stat fe3h plusw1 (1) fc3h adresl fa3h pie3 f83h portd f63h ssp2con1 fe2h fsr1h fc2h adcon0 fa2h ipr2 f82h portc f62h ssp2con2 fe1h fsr1l fc1h adcon1 fa1h pir2 f81h portb f61h ? (2) fe0h bsr fc0h adcon2 fa0h pie2 f80h porta f60h ? (2) note 1: this is not a physical register. 2: unimplemented registers are read as ? 0 ?. 3: this register is not available on 64-pin devices.
pic18f8722 family ds39646b-page 76 preliminary ? 2004 microchip technology inc. table 5-3: register file summary file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: tosu ? ? ? top-of-stack upper byte (tos<20:16>) ---0 0000 57, 66 tosh top-of-stack high byte (tos<15:8>) 0000 0000 57, 66 tosl top-of-stack low byte (tos<7:0>) 0000 0000 57, 66 stkptr stkful (6) stkunf (6) ? sp4 sp3 sp2 sp1 sp0 00-0 0000 57, 67 pclatu ? ? ? holding register for pc<20:16> ---0 0000 57, 66 pclath holding register for pc<15:8> 0000 0000 57, 66 pcl pc low byte (pc<7:0>) 0000 0000 57, 66 tblptru ? ?bit 21 (7) program memory table pointer upper byte (tblptr<20:16>) --00 0000 57, 90 tblptrh program memory table pointer high byte (tblptr<15:8>) 0000 0000 57, 90 tblptrl program memory table pointer low byte (tblptr<7:0>) 0000 0000 57, 90 tablat program memory table latch 0000 0000 57, 90 prodh product register high byte xxxx xxxx 57, 117 prodl product register low byte xxxx xxxx 57, 117 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 57, 121 intcon2 rbpu intedg0 intedg1 intedg2 intedg3 tmr0ip int3ip rbip 1111 1111 57, 122 intcon3 int2ip int1ip int3ie int2ie int1ie int3if int2if int1if 1100 0000 57, 123 indf0 uses contents of fsr0 to address data memory ? value of fsr0 not changed (not a physical register) n/a 57, 82 postinc0 uses contents of fsr0 to address data memory ? value of fsr0 post-incremented (not a physical register) n/a 57, 82 postdec0 uses contents of fsr0 to address data memory ? value of fsr0 post-decremented (not a physical register) n/a 57, 82 preinc0 uses contents of fsr0 to address data memory ? value of fsr0 pre-incremented (not a physical register) n/a 57, 82 plusw0 uses contents of fsr0 to address data memory ? value of fsr0 pre-incremented (not a physical register) ? value of fsr0 offset by w n/a 57, 82 fsr0h ? ? ? ? indirect data memory address pointer 0 high ---- 0000 57, 82 fsr0l indirect data memory address pointer 0 low byte xxxx xxxx 57, 82 wreg working register xxxx xxxx 57 indf1 uses contents of fsr1 to address data memory ? value of fsr1 not changed (not a physical register) n/a 57, 82 postinc1 uses contents of fsr1 to address data memory ? value of fsr1 post-incremented (not a physical register) n/a 57, 82 postdec1 uses contents of fsr1 to address data memory ? value of fsr1 post-decremented (not a physical register) n/a 57, 82 preinc1 uses contents of fsr1 to address data memory ? value of fsr1 pre-incremented (not a physical register) n/a 57, 82 plusw1 uses contents of fsr1 to address data memory ? value of fsr1 pre-incremented (not a physical register) ? value of fsr1 offset by w n/a 57, 82 fsr1h ? ? ? ? indirect data memory address pointer 1 high ---- 0000 58, 82 fsr1l indirect data memory address pointer 1 low byte xxxx xxxx 58, 82 bsr ? ? ? ? bank select register ---- 0000 58, 72 indf2 uses contents of fsr2 to address data memory ? value of fsr2 not changed (not a physical register) n/a 58, 82 postinc2 uses contents of fsr2 to address data memory ? value of fsr2 post-incremented (not a physical register) n/a 58, 82 postdec2 uses contents of fsr2 to address data memory ? value of fsr2 post-decremented (not a physical register) n/a 58, 82 preinc2 uses contents of fsr2 to address data memory ? value of fsr2 pre-incremented (not a physical register) n/a 58, 82 plusw2 uses contents of fsr2 to address data memory ? value of fsr2 pre-incremented (not a physical register) ? value of fsr2 offset by w n/a 58, 82 fsr2h ? ? ? ? indirect data memory address pointer 2 high ---- 0000 58, 82 fsr2l indirect data memory address pointer 2 low byte xxxx xxxx 58, 82 legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: the sboren bit is only available when the boren1:boren0 configuration bits = 01 ; otherwise, this bit reads as ? 0 ?. 2: these registers and/or bits are not implemented on 64-pin devices and are read as ? 0 ? . reset values are shown for 80-pin devices; individual unimplemented bits should be interpreted as ? - ?. 3: the pllen bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ? 0 ? . see section 2.6.4 ?pll in intosc modes? . 4: ra6/ra7 and their associated latch and direction bits are individually configured as port pins based on various primary oscilla tor modes. when disabled, these bits read as ? 0 ?. 5: rg5 and latg5 are only available when master clear is disabled (mclre configuration bit = 0 ); otherwise, rg5 and latg5 read as ? 0 ? . 6: bit 7 and bit 6 are cleared by user software or by a por. 7: bit 21 of tblptru allows access to the device configuration bits.
? 2004 microchip technology inc. preliminary ds39646b-page 77 pic18f8722 family status ? ? ?novzdcc ---x xxxx 58, 80 tmr0h timer0 register high byte 0000 0000 58, 163 tmr0l timer0 register low byte xxxx xxxx 58, 163 t0con tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 1111 1111 58, 161 osccon idlen ircf2 ircf1 ircf0 osts iofs scs1 scs0 0100 q000 39, 58 hlvdcon vdirmag ? irvst hlvden hlvdl3 hlvdl2 hlvdl1 hlvdl0 0-00 0101 58, 291 wdtcon ? ? ? ? ? ? ?swdten --- ---0 58, 313 rcon ipen sboren (1) ?ri to pd por bor 0q-1 11q0 50, 56, 58, 133 tmr1h timer1 register high byte xxxx xxxx 58, 169 tmr1l timer1 register low byte xxxx xxxx 58, 169 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 58, 165 tmr2 timer2 register 0000 0000 58, 172 pr2 timer2 period register 1111 1111 58, 172 t2con ? t2outps3 t2outps2 t2outps1 t2outps0 tmr2on t2ckps1 t2ckps0 -000 0000 58, 171 ssp1buf mssp1 receive buffer/transmit register xxxx xxxx 58, 169, 170 ssp1add mssp1 address register in i 2 c? slave mode. mssp1 baud rate reload register in i 2 c master mode. 0000 0000 58, 170 ssp1stat smp cke d/a psr/w ua bf 0000 0000 58, 162, 171 ssp1con1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 58, 163, 172 ssp1con2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 58, 173 adresh a/d result register high byte xxxx xxxx 59, 280 adresl a/d result register low byte xxxx xxxx 59, 280 adcon0 ? ? chs3 chs2 chs1 chs0 go/done adon --00 0000 59, 271 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 --00 0000 59, 272 adcon2 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 0-00 0000 59, 273 ccpr1h enhanced capture/compare/pwm register 1 high byte xxxx xxxx 59, 180 ccpr1l enhanced capture/compare/pwm register 1 low byte xxxx xxxx 59, 180 ccp1con p1m1 p1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 59, 187 ccpr2h enhanced capture/compare/pwm register 2 high byte xxxx xxxx 59, 180 ccpr2l enhanced capture/compare/pwm register 2 low byte xxxx xxxx 59, 180 ccp2con p2m1 p2m0 dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 0000 0000 59, 179 ccpr3h enhanced capture/compare/pwm register 3 high byte xxxx xxxx 59, 180 ccpr3l enhanced capture/compare/pwm register 3 low byte xxxx xxxx 59, 180 ccp3con p3m1 p3m0 dc3b1 dc3b0 ccp3m3 ccp3m2 ccp3m1 ccp3m0 0000 0000 59, 179 eccp1as eccp1ase eccp1as2 eccp1as1 eccp1as0 pss1ac1 pss1ac0 pss1bd1 pss1bd0 0000 0000 59, 201 cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 0000 0000 59, 287 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0111 59, 281 tmr3h timer3 register high byte xxxx xxxx 59, 175 tmr3l timer3 register low byte xxxx xxxx 59, 175 t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 59, 173 table 5-3: register file summary (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: the sboren bit is only available when the boren1:boren0 configuration bits = 01 ; otherwise, this bit reads as ? 0 ?. 2: these registers and/or bits are not implemented on 64-pin devices and are read as ? 0 ? . reset values are shown for 80-pin devices; individual unimplemented bits should be interpreted as ? - ?. 3: the pllen bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ? 0 ? . see section 2.6.4 ?pll in intosc modes? . 4: ra6/ra7 and their associated latch and direction bits are individually configured as port pins based on various primary oscilla tor modes. when disabled, these bits read as ? 0 ?. 5: rg5 and latg5 are only available when master clear is disabled (mclre configuration bit = 0 ); otherwise, rg5 and latg5 read as ? 0 ? . 6: bit 7 and bit 6 are cleared by user software or by a por. 7: bit 21 of tblptru allows access to the device configuration bits.
pic18f8722 family ds39646b-page 78 preliminary ? 2004 microchip technology inc. pspcon ibf obf ibov pspmode ? ? ? ? 0000 ---- 59, 252 spbrg1 eusart1 baud rate generator register low byte 0000 0000 59, 252 rcreg1 eusart1 receive register 0000 0000 59, 260 txreg1 eusart1 transmit register 0000 0000 59, 257 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 59, 248 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 0000 000x 59, 249 eeadrh ? ? ? ? ? ? eeprom address register high byte ---- --00 59, 111 eeadr eeprom address register low byte 0000 0000 59, 111 eedata eeprom data register 0000 0000 59, 111 eecon2 eeprom control register 2 (not a physical register) 0000 0000 59, 88 eecon1 eepgd cfgs ? free wrerr wren wr rd xx-0 x000 59, 89 ipr3 ssp2ip bcl2ip rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip 1111 1111 60, 131 pir3 ssp2if bcl2if rc2if tx2if tmr4if ccp5if ccp4if ccp3if 0000 0000 60, 125 pie3 ssp2ie bcl2ie rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie 0000 0000 60, 128 ipr2 oscfip cmip ? eeip bcl1ip hlvdip tmr3ip ccp2ip 11-1 1111 60, 131 pir2 oscfif cmif ? eeif bcl1if hlvdif tmr3if ccp2if 00-0 0000 60, 125 pie2 oscfie cmie ? eeie bcl1ie hlvdie tmr3ie ccp2ie 00-0 0000 60, 128 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 1111 1111 60, 130 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 0000 0000 60, 124 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 0000 0000 60, 127 memcon (2) ebdis ?wait1wait0 ? ?wm1wm0 0-00 --00 60, 96 osctune intsrc pllen (3) ? tun4 tun3 tun2 tun1 tun0 00-0 0000 35, 60 trisj (2) trisj7 trisj6 trisj5 trisj4 trisj3 trisj2 trisj1 trisj0 1111 1111 60, 157 trish (2) trish7 trish6 trish5 trish4 trish3 trish2 trish1 trish0 1111 1111 60, 155 trisg ? ? ? trisg4 trisg3 trisg2 trisg1 trisg0 ---1 1111 60, 153 trisf trisf7 trisf6 trisf5 trisf 4 trisf3 trisf2 trisf1 trisf0 1111 1111 60, 150 trise trise7 trise6 trise5 trise4 trise3 trise2 trise1 trise0 1111 1111 60, 148 trisd trisd7 trisd6 trisd5 trisd 4 trisd3 trisd2 trisd1 trisd0 1111 1111 60, 143 trisc trisc7 trisc6 trisc5 trisc 4 trisc3 trisc2 trisc1 trisc0 1111 1111 60, 140 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 1111 1111 60, 137 trisa trisa7 (4) trisa6 (4) trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 1111 1111 60, 135 latj (2) latj7latj6latj5latj4latj3latj2latj1latj0 xxxx xxxx 60, 156 lath (2) lath7 lath6 lath5 lath4 lath3 lath2 lath1 lath0 xxxx xxxx 60, 154 latg ? ?latg5 (5) latg4 latg3 latg2 latg1 latg0 --xx xxxx 60, 151 latf latf7 latf6 latf5 latf4 latf3 latf2 latf1 latf0 xxxx xxxx 60, 149 late late7 late6 late5 late4 late3 late2 late1 late0 xxxx xxxx 60, 146 latd latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 xxxx xxxx 60, 143 latc latc7 latc6 latc5 latc4 latc3 latc2 latc1 latc0 xxxx xxxx 60, 140 latb latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 xxxx xxxx 60, 137 lata lata7 (4) lata6 (4) lata5 lata4 lata3 lata2 lata1 lata0 xxxx xxxx 60, 135 table 5-3: register file summary (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: the sboren bit is only available when the boren1:boren0 configuration bits = 01 ; otherwise, this bit reads as ? 0 ?. 2: these registers and/or bits are not implemented on 64-pin devices and are read as ? 0 ? . reset values are shown for 80-pin devices; individual unimplemented bits should be interpreted as ? - ?. 3: the pllen bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ? 0 ? . see section 2.6.4 ?pll in intosc modes? . 4: ra6/ra7 and their associated latch and direction bits are individually configured as port pins based on various primary oscilla tor modes. when disabled, these bits read as ? 0 ?. 5: rg5 and latg5 are only available when master clear is disabled (mclre configuration bit = 0 ); otherwise, rg5 and latg5 read as ? 0 ? . 6: bit 7 and bit 6 are cleared by user software or by a por. 7: bit 21 of tblptru allows access to the device configuration bits.
? 2004 microchip technology inc. preliminary ds39646b-page 79 pic18f8722 family portj (2) rj7 rj6 rj5 rj4 rj3 rj2 rj1 rj0 xxxx xxxx 60, 156 porth (2) rh7 rh6 rh5 rh4 rh3 rh2 rh1 rh0 0000 xxxx 60, 154 portg ? ?rg5 (5) rg4 rg3 rg2 rg1 rg0 --xx xxxx 60, 151 portf rf7 rf6 rf5 rf4 rf3 rf2 rf1 rf0 x000 0000 60, 149 porte re7 re6 re5 re4 re3 re2 re1 re0 xxxx xxxx 60, 146 portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx 60, 143 portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx 60, 140 portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx 60, 137 porta ra7 (4) ra6 (4) ra5 ra4 ra3 ra2 ra1 ra0 xx0x 0000 61, 135 spbrgh1 eusart1 baud rate generator register high byte 0000 0000 61, 252 baudcon1 abdovf rcidl ? sckp brg16 ?wueabden 01-0 0-00 61, 250 spbrgh2 eusart2 baud rate generator register high byte 0000 0000 61, 252 baudcon2 abdovf rcidl ? sckp brg16 ?wueabden 01-0 0-00 61, 250 eccp1del p1rsen p1dc6 p1dc5 p1dc4 p1dc3 p1dc2 p1dc1 p1dc0 0000 0000 61, 200 tmr4 timer4 register 0000 0000 61, 178 pr4 timer4 period register 1111 1111 61, 178 t4con ? t4outps3 t4outps2 t4outps1 t4outps0 tmr4on t4ckps1 t4ckps0 -000 0000 61, 178 ccpr4h capture/compare/pwm register 4 high byte xxxx xxxx 61, 180 ccpr4l capture/compare/pwm register 4 low byte xxxx xxxx 61, 180 ccp4con ? ? dc4b1 dc4b0 ccp4m3 ccp4m2 ccp4m1 ccp4m0 --00 0000 61, 179 ccpr5h capture/compare/pwm register 5 high byte xxxx xxxx 61, 180 ccpr5l capture/compare/pwm register 5 low byte xxxx xxxx 61, 180 ccp5con ? ? dc5b1 dc5b0 ccp5m3 ccp5m2 ccp5m1 ccp5m0 --00 0000 61, 179 spbrg2 eusart2 baud rate generator register low byte 0000 0000 61, 252 rcreg2 eusart2 receive register 0000 0000 61, 260 txreg2 eusart2 transmit register 0000 0000 61, 257 txsta2 csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 61, 248 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 0000 000x 61, 249 eccp3as eccp3ase eccp3as2 eccp3as1 eccp3as0 pss3ac1 pss3ac0 pss3bd1 pss3bd0 0000 0000 61, 201 eccp3del p3rsen p3dc6 p3dc5 p3dc4 p3dc3 p3dc2 p3dc1 p3dc0 0000 0000 61, 200 eccp2as eccp2ase eccp2as2 eccp2as1 eccp2as0 pss2ac1 pss2ac0 pss2bd1 pss2bd0 0000 0000 61, 201 eccp2del p2rsen p2dc6 p2dc5 p2dc4 p2dc3 p2dc2 p2dc1 p2dc0 0000 0000 61, 200 ssp2buf mssp2 receive buffer/transmit register xxxx xxxx 61, 170 ssp2add mssp2 address register in i 2 c? slave mode. mssp2 baud rate reload register in i 2 c master mode. 0000 0000 61, 170 ssp2stat smp cke d/a psr/w ua bf 0000 0000 61, 216 ssp2con1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 61, 217 ssp2con2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 61, 218 table 5-3: register file summary (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: the sboren bit is only available when the boren1:boren0 configuration bits = 01 ; otherwise, this bit reads as ? 0 ?. 2: these registers and/or bits are not implemented on 64-pin devices and are read as ? 0 ? . reset values are shown for 80-pin devices; individual unimplemented bits should be interpreted as ? - ?. 3: the pllen bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ? 0 ? . see section 2.6.4 ?pll in intosc modes? . 4: ra6/ra7 and their associated latch and direction bits are individually configured as port pins based on various primary oscilla tor modes. when disabled, these bits read as ? 0 ?. 5: rg5 and latg5 are only available when master clear is disabled (mclre configuration bit = 0 ); otherwise, rg5 and latg5 read as ? 0 ? . 6: bit 7 and bit 6 are cleared by user software or by a por. 7: bit 21 of tblptru allows access to the device configuration bits.
pic18f8722 family ds39646b-page 80 preliminary ? 2004 microchip technology inc. 5.3.5 status register the status register, shown in register 5-2, contains the arithmetic status of the alu. as with any other sfr, it can be the operand for any instruction. if the status register is the destination for an instruction that affects the z, dc, c, ov or n bits, the results of the instruction are not written; instead, the status register is updated according to the instruction performed. there- fore, the result of an instruction with the status register as its destination may be different than intended. as an example, clrf status will set the z bit and leave the remaining status bits unchanged (? 000u u1uu ?). it is recommended that only bcf , bsf , swapf , movff and movwf instructions are used to alter the status register, because these instructions do not affect the z, c, dc, ov or n bits in the status register. for other instructions that do not affect status bits, see the instruction set summaries in table 26-2 and table 26-3. register 5-2: status: arithmetic status register note: the c and dc bits operate as the borrow and digit borrow bits, respectively, in subtraction. u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x ? ? ?novzdcc bit 7 bit 0 bit 7-5 unimplemented: read as ? 0 ? bit 4 n: negative bit this bit is used for signed arithmetic (2?s complement). it indicates whether the result was negative (alu msb = 1 ). 1 = result was negative 0 = result was positive bit 3 ov: overflow bit this bit is used for signed arithmetic (2?s complement). it indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7 of the result) to change state. 1 = overflow occurred for signed arithmetic (in this arithmetic operation) 0 = no overflow occurred bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/borrow bit for addwf , addlw , sublw and subwf instructions: 1 = a carry-out from the 4th low-order bit of the result occurred 0 = no carry-out from the 4th low-order bit of the result note: for borrow, the polarity is reversed. a subtraction is executed by adding the 2?s complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. bit 0 c: carry/borrow bit for addwf , addlw , sublw and subwf instructions: 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note: for borrow, the polarity is reversed. a subtraction is executed by adding the 2?s complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high or low-order bit of the source register. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39646b-page 81 pic18f8722 family 5.4 data addressing modes the data memory space can be addressed in several ways. for most instructions, the addressing mode is fixed. other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. the addressing modes are: inherent literal direct indirect an additional addressing mode, indexed literal offset, is available when the extended instruction set is enabled (xinst configuration bit = 1 ). its operation is discussed in greater detail in section 5.5.1 ?indexed addressing with literal offset? . 5.4.1 inherent and literal addressing many pic18 control instructions do not need any argu- ment at all; they either per form an operation that globally affects the device or they operate implicitly on one register. this addressing mode is known as inherent addressing. examples include sleep , reset and daw . other instructions work in a similar way but require an additional explicit argument in the opcode. this is known as literal addressing mode because they require some literal value as an argument. examples include addlw and movlw , which respectively, add or move a literal value to the w register. other examples include call and goto , which include a 20-bit program memory address. 5.4.2 direct addressing direct addressing specifies all or part of the source and/or destination address of the operation within the opcode itself. the options are specified by the arguments accompanying the instruction. in the core pic18 instruction set, bit-oriented and byte- oriented instructions use some version of direct addressing by default. all of these instructions include some 8-bit literal address as their least significant byte. this address specifies either a register address in one of the banks of data ram ( section 5.3.3 ?general purpose register file? ) or a location in the access bank ( section 5.3.2 ?access bank? ) as the data source for the instruction. the access ram bit ?a? determines how the address is interpreted. when ?a? is ? 1 ?, the contents of the bsr ( section 5.3.1 ?bank select register (bsr)? ) are used with the address to determine the complete 12-bit address of the register. when ?a? is ? 0 ?, the address is interpreted as being a register in the access bank. addressing that uses the access ram is sometimes also known as direct forced addressing mode. a few instructions, such as movff , include the entire 12-bit address (either source or destination) in their opcodes. in these cases, the bsr is ignored entirely. the destination of the operation?s results is determined by the destination bit ?d?. when ?d? is ? 1 ?, the results are stored back in the source register, overwriting its origi- nal contents. when ?d? is ? 0 ?, the results are stored in the w register. instructions without the ?d? argument have a destination that is implicit in the instruction; their destination is either the target register being operated on or the w register. 5.4.3 indirect addressing indirect addressing allows the user to access a location in data memory without giving a fixed address in the instruction. this is done by using file select registers (fsrs) as pointers to the locations to be read or written to. since the fsrs are themselves located in ram as special file registers, they can also be directly manip- ulated under program control. this makes fsrs very useful in implementing data structures, such as tables and arrays in data memory. the registers for indirect addressing are also implemented with indirect file operands (indfs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. this allows for efficient code, using loops, such as the example of clearing an entire ram bank in example 5-5. example 5-5: how to clear ram (bank 1) using indirect addressing note: the execution of some instructions in the core pic18 instruction set are changed when the pic18 extended instruction set is enabled. see section 5.5 ?data memory and the extended instruction set? for more information. lfsr fsr0, 100h ; next clrf postinc0 ; clear indf ; register then ; inc pointer btfss fsr0h, 1 ; all done with ; bank1? bra next ; no, clear next continue ; yes, continue
pic18f8722 family ds39646b-page 82 preliminary ? 2004 microchip technology inc. 5.4.3.1 fsr registers and the indf operand at the core of indirect addressing are three sets of registers: fsr0, fsr1 and fsr2. each represents a pair of 8-bit registers, fsrnh and fsrnl. the four upper bits of the fsrnh register are not used so each fsr pair holds a 12-bit value. this represents a value that can address the entire range of the data memory in a linear fashion. the fsr register pairs, then, serve as pointers to data memory locations. indirect addressing is accomplished with a set of indirect file operands, indf0 through indf2. these can be thought of as ?virtual? registers: they are mapped in the sfr space but are not physically imple- mented. reading or writing to a particular indf register actually accesses its corresponding fsr register pair. a read from indf1, for example, reads the data at the address indicated by fsr1h:fsr1l. instructions that use the indf registers as operands actually use the contents of their corresponding fsr as a pointer to the instruction?s target. the indf operand is just a convenient way of using the pointer. because indirect addressing uses a full 12-bit address, data ram banking is not necessary. thus, the current contents of the bsr and the access ram bit have no effect on determining the target address. 5.4.3.2 fsr registers and postinc, postdec, preinc and plusw in addition to the indf operand, each fsr register pair also has four additional indirect operands. like indf, these are ?virtual? registers that cannot be indirectly read or written to. accessing these registers actually accesses the associated fsr register pair, but also performs a specific action on its stored value. they are: postdec: accesses the fsr value, then automatically decrements it by 1 afterwards postinc: accesses the fsr value, then automatically increments it by 1 afterwards preinc: increments the fsr value by 1, then uses it in the operation plusw: adds the signed value of the w register (range of -127 to 128) to that of the fsr and uses the new value in the operation. in this context, accessing an indf register uses the value in the fsr registers without changing them. similarly, accessing a plusw register gives the fsr value offset by the value in the w register; neither value is actually changed in the operation. accessing the other virtual registers changes the value of the fsr registers. operations on the fsrs with postdec, postinc and preinc affect the entire register pair; that is, roll- overs of the fsrnl register from ffh to 00h carry over to the fsrnh register. on the other hand, results of these operations do not change the value of any flags in the status register (e.g., z, n, ov, etc.). figure 5-8: indirect addressing fsr1h:fsr1l 0 7 data memory 000h 100h 200h 300h f00h e00h fffh bank 0 bank 1 bank 2 bank 14 bank 15 bank 3 through bank 13 addwf, indf1, 1 0 7 using an instruction with one of the indirect addressing registers as the operand.... ...uses the 12-bit address stored in the fsr pair associated with that register.... ...to determine the data memory location to be used in that operation. in this case, the fsr1 pair contains ecch. this means the contents of location ecch will be added to that of the w register and stored back in ecch. xxxx 1110 11001100
? 2004 microchip technology inc. preliminary ds39646b-page 83 pic18f8722 family the plusw register can be used to implement a form of indexed addressing in the data memory space. by manipulating the value in the w register, users can reach addresses that are fixed offsets from pointer addresses. in some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 5.4.3.3 operations by fsrs on fsrs indirect addressing operations that target other fsrs or virtual registers represent special cases. for exam- ple, using an fsr to point to one of the virtual registers will not result in successful operations. as a specific case, assume that fsr0h:fsr0l contains fe7h, the address of indf1. attempts to read the value of the indf1 using indf0 as an operand will return 00h. attempts to write to indf1 using indf0 as the operand will result in a nop . on the other hand, using the virtual registers to write to an fsr pair may not occur as planned. in these cases, the value will be written to the fsr pair but without any incrementing or decrementing. thus, writing to indf2 or postdec2 will write the same value to the fsr2h:fsr2l. since the fsrs are physical registers mapped in the sfr space, they can be manipulated through all direct operations. users should proceed cautiously when working on these registers, particularly if their code uses indirect addressing. similarly, operations by indirect addressing are gener- ally permitted on all other sfrs. users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device. 5.5 data memory and the extended instruction set enabling the pic18 extended instruction set (xinst configuration bit = 1 ) significantly changes certain aspects of data memory and its addressing. specifi- cally, the use of the access bank for many of the core pic18 instructions is different; this is due to the introduction of a new addressing mode for the data memory space. what does not change is just as important. the size of the data memory space is unchanged, as well as its linear addressing. the sfr map remains the same. core pic18 instructions can still operate in both direct and indirect addressing mode; inherent and literal instructions do not change at all. indirect addressing with fsr0 and fsr1 also remain unchanged. 5.5.1 indexed addressing with literal offset enabling the pic18 extended instruction set changes the behavior of indirect addressing using the fsr2 register pair within access ram. under the proper conditions, instructions that use the access bank ? that is, most bit-oriented and byte-oriented instructions ? can invoke a form of indexed addressing using an offset specified in the instruction. this special address- ing mode is known as indexed addressing with literal offset, or indexed literal offset mode. when using the extended instruction set, this addressing mode requires the following: the use of the access bank is forced (?a? = 0 ) and the file address argument is less than or equal to 5fh. under these conditions, the file address of the instruc- tion is not interpreted as the lower byte of an address (used with the bsr in direct addressing), or as an 8-bit address in the access bank. instead, the value is interpreted as an offset value to an address pointer, specified by fsr2. the offset and the contents of fsr2 are added to obtain the target address of the operation. 5.5.2 instructions affected by indexed literal offset mode any of the core pic18 instructions that can use direct addressing are potentially affected by the indexed literal offset addressing mode. this includes all byte-oriented and bit-oriented instructions, or almost one-half of the standard pic18 instruction set. instructions that only use inherent or literal addressing modes are unaffected. additionally, byte-oriented and bit-oriented instructions are not affected if they do not use the access bank (access ram bit is ? 1 ?), or include a file address of 60h or above. instructions meeting these criteria will continue to execute as before. a comparison of the dif- ferent possible addressing modes when the extended instruction set is enabled in shown in figure 5-9. those who desire to use byte-oriented or bit-oriented instructions in the indexed literal offset mode should note the changes to assembler syntax for this mode. this is described in more detail in section 26.2.1 ?extended instruction syntax? .
pic18f8722 family ds39646b-page 84 preliminary ? 2004 microchip technology inc. figure 5-9: comparing addressing options for bit-oriented and byte-oriented instructions (extended instruction set enabled) example instruction: addwf, f, d, a (opcode: 0010 01da ffff ffff ) when ?a? = 0 and f 60h: the instruction executes in direct forced mode. ?f? is inter- preted as a location in the access ram between 060h and 0ffh. this is the same as locations 060h to 07fh (bank 0) and f80h to fffh (bank 15) of data memory. locations below 60h are not available in this addressing mode. when ?a? = 0 and f 5fh: the instruction executes in indexed literal offset mode. ?f? is interpreted as an offset to the address value in fsr2. the two are added together to obtain the address of the target register for the instruction. the address can be anywhere in the data memory space. note that in this mode, the correct syntax is now: addwf [k], d where ?k? is the same as ?f?. when ?a? = 1 (all values of f): the instruction executes in direct mode (also known as direct long mode). ?f? is inter- preted as a location in one of the 16 banks of the data memory space. the bank is designated by the bank select register (bsr). the address can be in any implemented bank in the data memory space. 000h 060h 100h f00h f80h fffh valid range 00h 60h 80h ffh data memory access ram bank 0 bank 1 through bank 14 bank 15 sfrs 000h 080h 100h f00h f80h fffh data memory bank 0 bank 1 through bank 14 bank 15 sfrs fsr2h fsr2l ffffffff 001001da ffffffff 001001da 000h 080h 100h f00h f80h fffh data memory bank 0 bank 1 through bank 14 bank 15 sfrs for ?f? bsr 00000000 080h
? 2004 microchip technology inc. preliminary ds39646b-page 85 pic18f8722 family 5.5.3 mapping the access bank in indexed literal offset mode the use of indexed literal offset addressing mode effectively changes how the first 96 locations of access ram (00h to 5fh) are mapped. rather than containing just the contents of the bottom half of bank 0, this mode maps the contents from bank 0 and a user defined ?window? that can be located anywhere in the data memory space. the value of fsr2 establishes the lower boundary of the addresses mapped into the window, while the upper boundary is defined by fsr2 plus 95 (5fh). addresses in the access ram above 5fh are mapped as previously described (see section 5.3.2 ?access bank? ). an example of access bank remapping in this addressing mode is shown in figure 5-10. remapping of the access bank applies only to opera- tions using the indexed literal offset mode. operations that use the bsr (access ram bit is ? 1 ?) will continue to use direct addressing as before. 5.6 pic18 instruction execution and the extended instruction set enabling the extended instruction set adds eight additional commands to the existing pic18 instruction set. these instructions are executed as described in section 26.2 ?extended instruction set? . figure 5-10: remapping the access bank with indexed literal offset addressing data memory 000h 100h 200h f80h f00h fffh bank 1 bank 15 bank 2 through bank 14 sfrs 05fh addwf f, d, a fsr2h:fsr2l = 120h locations in the region from the fsr2 pointer (120h) to the pointer plus 05fh (17fh) are mapped to the bottom of the access ram (000h-05fh). locations in bank 0 from 060h to 07fh are mapped, as usual, to the middle half of the access bank. special file registers at f80h through fffh are mapped to 80h through ffh, as usual. bank 0 addresses below 5fh can still be addressed by using the bsr. access bank 00h 80h ffh 7fh bank 0 sfrs bank 1 ?window? bank 0 bank 0 window example situation: 07fh 120h 17fh 5fh bank 1
pic18f8722 family ds39646b-page 86 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39646b-page 87 pic18f8722 family 6.0 flash program memory the flash program memory is readable, writable and erasable during normal operation over the entire v dd range. a read from program memory is executed on one byte at a time. a write to program memory is executed on blocks of 64 bytes at a time. program memory is erased in blocks of 64 bytes at a time. a bulk erase operation may not be issued from user code. writing or erasing program memory will cease instruction fetches until the operation is complete. the program memory cannot be accessed during the write or erase, therefore, code cannot execute. an internal programming timer terminates program memory writes and erases. a value written to program memory does not need to be a valid instruction. executing a program memory location that forms an invalid instruction results in a nop . 6.1 table reads and table writes in order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data ram: table read ( tblrd ) table write ( tblwt ) the program memory space is 16 bits wide, while the data ram space is 8 bits wide. table reads and table writes move data between these two memory spaces through an 8-bit register (tablat). table read operations retrieve data from program memory and place it into the data ram space. figure 6-1 shows the operation of a table read with program memory and data ram. table write operations store data from the data memory space into holding registers in program memory. the procedure to write the contents of the holding registers into program memory is detailed in section 6.5 ?writing to flash program memory? . figure 6-2 shows the operation of a table write with program memory and data ram. table operations work with byte entities. a table block containing data, rather than program instructions, is not required to be word aligned. therefore, a table block can start and end at any byte address. if a table write is being used to write executable code into program memory, program instructions will need to be word aligned. figure 6-1: table read operation table pointer (1) table latch (8-bit) program memory tblptrh tblptrl tablat tblptru instruction: tblrd * note 1: table pointer register points to a byte in program memory. program memory (tblptr)
pic18f8722 family ds39646b-page 88 preliminary ? 2004 microchip technology inc. figure 6-2: table write operation 6.2 control registers several control registers are used in conjunction with the tblrd and tblwt instructions. these include the: eecon1 register eecon2 register tablat register tblptr registers 6.2.1 eecon1 and eecon2 registers the eecon1 register (register 6-1) is the control register for memory accesses. the eecon2 register is not a physical register; it is used exclusively in the memory write and erase sequences. reading eecon2 will read all ? 0 ?s. the eepgd control bit determines if the access will be a program or data eeprom memory access. when clear, any subsequent operations will operate on the data eeprom memory. when set, any subsequent operations will operate on the program memory. the cfgs control bit determines if the access will be to the configuration/calibration registers or to program memory/data eeprom memory. when set, subsequent operations will operate on configuration registers regardless of eepgd (see section 25.0 ?special features of the cpu? ). when clear, memory selection access is determined by eepgd. the free bit, when set, will allow a program memory erase operation. when free is set, the erase operation is initiated on the next wr command. when free is clear, only writes are enabled. the wren bit, when set, will allow a write operation. on power-up, the wren bit is clear. the wrerr bit is set in hardware when the wr bit is set and cleared when the internal programming timer expires and the write operation is complete. the wr control bit initiates write operations. the bit cannot be cleared, only set, in software; it is cleared in hardware at the completion of the write operation. table pointer (1) table latch (8-bit) tblptrh tblptrl tablat program memory (tblptr) tblptru instruction: tblwt * note 1: table pointer actually points to one of 64 holding registers, the address of which is determined by tblptrl<5:0>. the process for physically writing da ta to the program memory array is discussed in section 6.5 ?writing to flash program memory? . holding registers program memory note: during normal operation, the wrerr is read as ? 1 ?. this can indicate that a write operation was prematurely terminated by a reset, or a write operation was attempted improperly. note: the eeif interrupt flag bit (pir2<4>) is set when the write is complete. it must be cleared in software.
? 2004 microchip technology inc. preliminary ds39646b-page 89 pic18f8722 family register 6-1: eecon1: eeprom control register 1 r/w-x r/w-x u-0 r/w-0 r/w-x r/w-0 r/s-0 r/s-0 eepgd cfgs ? free wrerr wren wr rd bit 7 bit 0 bit 7 eepgd: flash program or data eeprom memory select bit 1 = access flash program memory 0 = access data eeprom memory bit 6 cfgs: flash program/data eeprom or configuration select bit 1 = access configuration registers 0 = access flash program or data eeprom memory bit 5 unimplemented: read as ? 0 ? bit 4 free: flash row erase enable bit 1 = erase the program memory row addressed by tblptr on the next wr command (cleared by completion of erase operation) 0 = perform write only bit 3 wrerr: flash program/data eeprom error flag bit 1 = a write operation is prematurely terminated (any reset during self-timed programming in normal operation, or an improper write attempt) 0 = the write operation completed note: when a wrerr occurs, the eepgd and cfgs bits are not cleared. this allows tracing of the error condition. bit 2 wren: flash program/data eeprom write enable bit 1 = allows write cycles to flash program/data eeprom 0 = inhibits write cycles to flash program/data eeprom bit 1 wr: write control bit 1 = initiates a data eeprom erase/write cycle or a program memory erase cycle or write cycle. (the operation is self-timed and the bit is cleared by hardware once write is complete. the wr bit can only be set (not cleared) in software.) 0 = write cycle to the eeprom is complete bit 0 rd: read control bit 1 = initiates an eeprom read (read takes one cycle. rd is cleared in hardware. the rd bit can only be set (not cleared) in software. rd bit cannot be set when eepgd = 1 or cfgs = 1 .) 0 = does not initiate an eeprom read legend: r = readable bit w = writable bit s = bit can be set by software, but not cleared u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 90 preliminary ? 2004 microchip technology inc. 6.2.2 tablat ? table latch register the table latch (tablat) is an 8-bit register mapped into the sfr space. the table latch register is used to hold 8-bit data during data transfers between program memory and data ram. 6.2.3 tblptr ? table pointer register the table pointer (tblptr) register addresses a byte within the program memory. the tblptr is comprised of three sfr registers: table pointer upper byte, table pointer high byte and table pointer low byte (tblptru:tblptrh:tblptrl). these three regis- ters join to form a 22-bit wide pointer. the low-order 21 bits allow the device to address up to 2 mbytes of program memory space. the 22nd bit allows access to the device id, the user id and the configuration bits. the table pointer register, tblptr, is used by the tblrd and tblwt instructions. these instructions can update the tblptr in one of four ways based on the table operation. these operations are shown in table 6-1. these operations on the tblptr only affect the low-order 21 bits. 6.2.4 table pointer boundaries tblptr is used in reads, writes and erases of the flash program memory. when a tblrd is executed, all 22 bits of the tblptr determine which byte is read from program memory into tablat. when a tblwt is executed, the six lsbs of the table pointer register (tblptr<5:0>) determine which of the 64 program memory holding registers is written to. when the timed write to program memory begins (via the wr bit), the 16 msbs of the tblptr (tblptr<21:6>) determine which program memory block of 64 bytes is written to. for more detail, see section 6.5 ?writing to flash program memory? . when an erase of program memory is executed, the 16 msbs of the table pointer register (tblptr<21:6>) point to the 64-byte block that will be erased. the least significant bits (tblptr<5:0>) are ignored. figure 6-3 describes the relevant boundaries of tblptr based on flash program memory operations. table 6-1: table pointer operations with tblrd and tblwt instructions figure 6-3: table pointer boundaries based on operation example operation on table pointer tblrd* tblwt* tblptr is not modified tblrd*+ tblwt*+ tblptr is incremented after the read/write tblrd*- tblwt*- tblptr is decremented after the read/write tblrd+* tblwt+* tblptr is incremented before the read/write 21 16 15 87 0 table erase/write table write table read ? tblptr<21:0> tblptrl tblptrh tblptru tblptr<5:0> tblptr<21:6>
? 2004 microchip technology inc. preliminary ds39646b-page 91 pic18f8722 family 6.3 reading the flash program memory the tblrd instruction is used to retrieve data from program memory and places it into data ram. table reads from program memory are performed one byte at a time. tblptr points to a byte address in program space. executing tblrd places the byte pointed to into tablat. in addition, tblptr can be modified automatically for the next table read operation. the internal program memory is typically organized by words. the least significant bit of the address selects between the high and low bytes of the word. figure 6-4 shows the interface between the internal program memory and the tablat. figure 6-4: reads from flash program memory example 6-1: reading a flash program memory word (even byte address) program memory (odd byte address) tblrd tablat tblptr = xxxxx1 fetch instruction register (ir) read register tblptr = xxxxx0 movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the word movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl read_word tblrd*+ ; read into tablat and increment movf tablat, w ; get data movwf word_even tblrd*+ ; read into tablat and increment movf tablat, w ; get data movf word_odd
pic18f8722 family ds39646b-page 92 preliminary ? 2004 microchip technology inc. 6.4 erasing flash program memory the minimum erase block is 32 words or 64 bytes. only through the use of an external programmer, or through icsp control, can larger blocks of program memory be bulk erased. word erase in the flash array is not supported. when initiating an erase sequence from the micro- controller itself, a block of 64 bytes of program memory is erased. the most significant 16 bits of the tblptr<21:6> point to the block being erased. tblptr<5:0> are ignored. the eecon1 register commands the erase operation. the eepgd bit must be set to point to the flash program memory. the wren bit must be set to enable write operations. the free bit is set to select an erase operation. for protection, the write initiate sequence for eecon2 must be used. a long write is necessary for erasing the internal flash. instruction execution is halted while in a long write cycle. the long write will be terminated by the internal programming timer. 6.4.1 flash program memory erase sequence the sequence of events for erasing a block of internal program memory location is: 1. load table pointer register with address of row being erased. 2. set the eecon1 register for the erase operation: set eepgd bit to point to program memory; clear the cfgs bit to access program memory; set wren bit to enable writes; set free bit to enable the erase. 3. disable interrupts. 4. write 55h to eecon2. 5. write 0aah to eecon2. 6. set the wr bit. this will begin the row erase cycle. 7. the cpu will stall for duration of the erase for t iw (see parameter d133a). 8. re-enable interrupts. example 6-2: erasing a flash program memory row movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the memory block movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl erase_row bsf eecon1, eepgd ; point to flash program memory bcf eecon1, cfgs ; access flash program memory bsf eecon1, wren ; enable write to memory bsf eecon1, free ; enable row erase operation bcf intcon, gie ; disable interrupts required movlw 55h sequence movwf eecon2 ; write 55h movlw 0aah movwf eecon2 ; write 0aah bsf eecon1, wr ; start erase (cpu stall) bsf intcon, gie ; re-enable interrupts
? 2004 microchip technology inc. preliminary ds39646b-page 93 pic18f8722 family 6.5 writing to flash program memory the minimum programming block is 32 words or 64 bytes. word or byte programming is not supported. table writes are used internally to load the holding registers needed to program the flash memory. there are 64 holding registers used by the table writes for programming. since the table latch (tablat) is only a single byte, the tblwt instruction may need to be executed 64 times for each programming operation. all of the table write oper- ations will essentially be short writes because only the holding registers are written. at the end of updating the 64 holding registers, the eecon1 register must be written to in order to start the programming operation with a long write. the long write is necessary for programming the inter- nal flash. instruction execution is halted while in a long write cycle. the long write will be terminated by the internal programming timer. the eeprom on-chip timer controls the write time. the write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. figure 6-5: table writes to flash program memory 6.5.1 flash program memory write sequence the sequence of events for programming an internal program memory location should be: 1. read 64 bytes into ram. 2. update data values in ram as necessary. 3. load table pointer register with address being erased. 4. execute the row erase procedure. 5. load table pointer register with address of first byte being written. 6. write the 64 bytes into the holding registers with auto-increment. 7. set the eecon1 register for the write operation: set eepgd bit to point to program memory; clear the cfgs bit to access program memory; set wren to enable byte writes. 8. disable interrupts. 9. write 55h to eecon2. 10. write 0aah to eecon2. 11. set the wr bit. this will begin the write cycle. 12. the cpu will stall for duration of the write for t iw (see parameter d133a). 13. re-enable interrupts. 14. verify the memory (table read). an example of the required code is shown in example 6-3 on the following page. note: the default value of the holding registers on device resets and after write operations is ffh. a write of ffh to a holding register does not modify that byte. this means that individual bytes of program memory may be modified, provided that the change does not attempt to change any bit from a ? 0 ? to a ? 1 ?. when modifying individual bytes, it is not necessary to load all 64 holding registers before executing a write operation. tablat tblptr = xxxx3f tblptr = xxxxx1 tblptr = xxxxx0 write register tblptr = xxxxx2 program memory holding register holding register holding register holding register 8 8 8 8 note: before setting the wr bit, the table pointer address needs to be within the intended address range of the 64 bytes in the holding register.
pic18f8722 family ds39646b-page 94 preliminary ? 2004 microchip technology inc. example 6-3: writing to flash program memory movlw d'64' ; number of bytes in erase block movwf counter movlw buffer_addr_high ; point to buffer movwf fsr0h movlw buffer_addr_low movwf fsr0l movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the memory block movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl read_block tblrd*+ ; read into tablat, and inc movf tablat, w ; get data movwf postinc0 ; store data decfsz counter ; done? bra read_block ; repeat modify_word movlw data_addr_high ; point to buffer movwf fsr0h movlw data_addr_low movwf fsr0l movlw new_data_low ; update buffer word movwf postinc0 movlw new_data_high movwf indf0 erase_block movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the memory block movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl bsf eecon1, eepgd ; point to flash program memory bcf eecon1, cfgs ; access flash program memory bsf eecon1, wren ; enable write to memory bsf eecon1, free ; enable row erase operation bcf intcon, gie ; disable interrupts movlw 55h required movwf eecon2 ; write 55h sequence movlw 0aah movwf eecon2 ; write 0aah bsf eecon1, wr ; start erase (cpu stall) bsf intcon, gie ; re-enable interrupts tblrd*- ; dummy read decrement movlw buffer_addr_high ; point to buffer movwf fsr0h movlw buffer_addr_low movwf fsr0l write_buffer_back movlw d'64' ; number of bytes in holding register movwf counter write_byte_to_hregs movff postinc0, wreg ; get low byte of buffer data movwf tablat ; present data to table latch tblwt+* ; write data, perform a short write ; to internal tblwt holding register. decfsz counter ; loop until buffers are full bra write_word_to_hregs
? 2004 microchip technology inc. preliminary ds39646b-page 95 pic18f8722 family example 6-3: writing to flash program memory (continued) 6.5.2 write verify depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. this should be used in applications where excessive writes can stress bits near the specification limit. 6.5.3 unexpected termination of write operation if a write is terminated by an unplanned event, such as loss of power or an unexpected reset, the memory location just programmed should be verified and repro- grammed if needed. if the write operation is interrupted by a mclr reset or a wdt time-out reset during normal operation, the user can check the wrerr bit and rewrite the location(s) as needed. 6.5.4 protection against spurious writes to protect against spurious writes to flash program memory, the write initiate sequence must also be followed. see section 25.0 ?special features of the cpu? for more detail. 6.6 flash program operation during code protection see section 25.5 ?program verification and code protection? for details on code protection of flash program memory. table 6-2: registers associated with program flash memory program_memory bsf eecon1, eepgd ; point to flash program memory bcf eecon1, cfgs ; access flash program memory bsf eecon1, wren ; enable write to memory bcf intcon, gie ; disable interrupts movlw 55h required movwf eecon2 ; write 55h sequence movlw 0aah movwf eecon2 ; write 0aah bsf eecon1, wr ; start program (cpu stall) bsf intcon, gie ; re-enable interrupts bcf eecon1, wren ; disable write to memory name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page tblptru ? ?bit 21 (1) program memory table pointer upper byte (tblptr<20:16>) 57 tbpltrh program memory table pointer high byte (tblptr<15:8>) 57 tblptrl program memory table pointer low byte (tblptr<7:0>) 57 tablat program memory table latch 57 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 eecon2 eeprom control register 2 (not a physical register) 59 eecon1 eepgd cfgs ? free wrerr wren wr rd 59 ipr2 oscfip cmip ? eeip bcl1ip hlvdip tmr3ip ccp2ip 60 pir2 oscfif cmif ? eeif bcl1if hlvdif tmr3if ccp2if 60 pie2 oscfie cmie ? eeie bcl1ie hlvdie tmr3ie ccp2ie 60 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used during flash/eeprom access. note 1: bit 21 of tblptru allows access to the device configuration bits.
pic18f8722 family ds39646b-page 96 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39646b-page 97 pic18f8722 family 7.0 external memory bus the external memory bus allows the device to access external memory devices (such as flash, eprom, sram, etc.) as program or data memory. it supports both 8-bit and 16-bit data width modes and four address widths from 8 to 20 bits. the bus is implemented with 28 pins, multiplexed across four i/o ports. three ports (portd, porte and porth) are multiplexed with the address/data bus for a total of 20 available lines, while portj is multiplexed with the bus control signals. a list of the pins and their functions is provided in table 7-1. table 7-1: pic18f8527/8622/8627/8722 extern al bus ? i/o port functions note: the external memory bus is not imple- mented on pic18f6527/6622/6627/6722 (64-pin) devices. name port bit external memory bus function rd0/ad0 portd 0 address bit 0 or data bit 0 rd1/ad1 portd 1 address bit 1 or data bit 1 rd2/ad2 portd 2 address bit 2 or data bit 2 rd3/ad3 portd 3 address bit 3 or data bit 3 rd4/ad4 portd 4 address bit 4 or data bit 4 rd5/ad5 portd 5 address bit 5 or data bit 5 rd6/ad6 portd 6 address bit 6 or data bit 6 rd7/ad7 portd 7 address bit 7 or data bit 7 re0/ad8 porte 0 address bit 8 or data bit 8 re1/ad9 porte 1 address bit 9 or data bit 9 re2/ad10 porte 2 address bit 10 or data bit 10 re3/ad11 porte 3 address bit 11 or data bit 11 re4/ad12 porte 4 address bit 12 or data bit 12 re5/ad13 porte 5 address bit 13 or data bit 13 re6/ad14 porte 6 address bit 14 or data bit 14 re7/ad15 porte 7 address bit 15 or data bit 15 rh0/a16 porth 0 address bit 16 rh1/a17 porth 1 address bit 17 rh2/a18 porth 2 address bit 18 rh3/a19 porth 3 address bit 19 rj0/ale portj 0 address latch enable (ale) control pin rj1/oe portj 1 output enable (oe ) control pin rj2/wrl portj 2 write low (wrl ) control pin rj3/wrh portj 3 write high (wrh ) control pin rj4/ba0 portj 4 byte address bit 0 (ba0) rj5/ce portj 5 chip enable (ce ) control pin rj6/lb portj 6 lower byte enable (lb ) control pin rj7/ub portj 7 upper byte enable (ub ) control pin note: for the sake of clarity, only i/o port and external bus assignments are shown here. one or more additional multiplexed features may be available on some pins.
pic18f8722 family ds39646b-page 98 preliminary ? 2004 microchip technology inc. 7.1 external memory bus control the operation of the interface is controlled by the memcon register (register 7-1). this register is available in all program memory operating modes except microcontroller mode. in this mode, the register is disabled and cannot be written to. the ebdis bit (memcon<7>) controls the operation of the bus and related port functions. clearing ebdis enables the interface and disables the i/o functions of the ports, as well as any other functions multiplexed to those pins. setting the bit enables the i/o ports and other functions but allows the interface to override everything else on the pins when an external memory operation is required. by default, the external bus is always enabled and disables all other i/o. the operation of the ebdis bit is also influenced by the program memory mode being used. this is discussed in more detail in section 7.4 ?program memory modes and the external memory bus? . the wait bits allow for the addition of wait states to external memory operations. the use of these bits is discussed in section 7.3 ?wait states? . the wm bits select the particular operating mode used when the bus is operating in 16-bit data width mode. these are discussed in more detail in section 7.5 ?16-bit data width modes? . these bits have no effect when an 8-bit data width mode is selected. register 7-1: memcon: external memory bus control register r/w-0 u-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 ebdis ?wait1wait0 ? ?wm1wm0 bit7 bit0 bit 7 ebdis : external bus disable bit 1 = external bus enabled when microcontroller accesses external memory; otherwise, all external bus drivers are mapped as i/o ports 0 = external bus always enabled, i/o ports are disabled bit 6 unimplemented : read as ? 0 ? bit 5-4 wait1:wait0: table reads and writes bus cycle wait count bits 11 = table reads and writes will wait 0 t cy 10 = table reads and writes will wait 1 t cy 01 = table reads and writes will wait 2 t cy 00 = table reads and writes will wait 3 t cy bit 3-2 unimplemented : read as ? 0 ? bit 1-0 wm1:wm0: tblwt operation with 16-bit data bus width select bits 1x = word write mode: tablat0 and tablat1 word output, wrh active when tablat1 written 01 = byte select mode: tablat data copied on both msb and lsb, wrh and (ub or lb ) will activate 00 = byte write mode: tablat data copied on both msb and lsb, wrh or wrl will activate legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39646b-page 99 pic18f8722 family 7.2 address and data width pic18f8527/8622/8627/8722 devices can be indepen- dently configured for different address and data widths on the same memory bus. both address and data width are set by configuration bits in the config3l register. as configuration bits, this means that these options can only be configured by programming the device and are not controllable in software. the bw bit selects an 8-bit or 16-bit data bus width. setting this bit (default) selects a data width of 16 bits. the adw1:adw0 bits determine the address bus width. the available options are 20-bit (default), 16-bit, 12-bit and 8-bit. selecting any of the options other than 20-bit width makes a corresponding number of high-order lines available for i/o functions; these pins are no longer affected by the setting of the ebdis bit. for example, selecting a 16-bit address mode (adw1:adw0 = 10 ) disables a19:a16 and allows porth<3:0> to function without interruptions from the bus. using smaller address widths allows users to tailor the memory bus to the size of the external memory space for a particular design while freeing up pins for dedicated i/o operation. because the adw bits have the effect of disabling pins for memory bus operations, it is important to always select an address width at least equal to the data width. if 8-bit or 12-bit address widths are used with a 16-bit data width, the upper bits of data will not be available on the bus. all combinations of address and data widths require multiplexing of address and data information on the same lines. the address and data multiplexing, as well as i/o ports made available by the use of smaller address widths, are summarized in table 7-2. 7.2.1 21-bit addressing as an extension of 20-bit address width operation, the external memory bus can also fully address a 2 mbyte memory space. this is done by using the bus address bit 0 (ba0) control line as the least significant bit of the address. the ub and lb control signals may also be used with certain memory devices to select the upper and lower bytes within a 16-bit wide data word. this addressing mode is available in both 8-bit and certain 16-bit data width modes. additional details are provided in section 7.5.3 ?16-bit byte select mode? and section 7.6 ?8-bit data width modes? . 7.3 wait states while it may be assumed that external memory devices will operate at the microcontroller clock rate, this is often not the case. in fact, many devices require longer times to write or retrieve data than the time allowed by the execution of table read or table write operations. to compensate for this, the external memory bus can be configured to add a fixed delay to each table opera- tion using the bus. wait states are enabled by setting the wait configuration bit. when enabled, the amount of delay is set by the wait1:wait0 bits (memcon<5:4>). the delay is based on multiples of microcontroller instruction cycle time and are added following the instruction cycle when the table operation is executed. the range is from no delay to 3 t cy (default value). table 7-2: address and data lines for different address and data widths data width address width multiplexed data and address lines (and corresponding ports) address-only lines (and corresponding ports) ports available for i/o 8-bit 8-bit ad7:ad0 (portd<7:0>) ? all of porte and porth 12-bit ad11:ad8 (porte<3:0>) porte<7:4>, all of porth 16-bit ad15:ad8 (porte<7:0>) all of porth 20-bit a19:a16, ad15:ad8 (porth<3:0>, porte<7:0>) ? 16-bit 16-bit ad15:ad0 (portd<7:0>, porte<7:0>) ?all of porth 20-bit a19:a16 (porth<3:0>) ?
pic18f8722 family ds39646b-page 100 preliminary ? 2004 microchip technology inc. 7.4 program memory modes and the external memory bus pic18f8527/8622/8627/8722 devices are capable of operating in any one of four program memory modes, using combinations of on-chip and external program memory. the functions of the multiplexed port pins depends on the program memory mode selected, as well as the setting of the ebdis bit. in microcontroller mode, the bus is not active and the pins have their port functions only. writes to the memcom register are not permitted. the reset value of ebdis (? 0 ?) is ignored and emb pins behave as i/o ports. in microprocessor mode , the external bus is always active and the port pins have only the external bus function. the value of ebdis is ignored. in microprocessor with boot block or extended microcontroller mode, the external program memory bus shares i/o port functions on the pins. when the device is fetching or doing table read/table write opera- tions on the external program memory space, the pins will have the external bus function. if the device is fetching and accessing internal program memory loca- tions only, the ebdis control bit will change the pins from external memory to i/o port functions. when ebdis = 0 , the pins function as the external bus. when ebdis = 1 , the pins function as i/o ports. if the device fetches or accesses external memory while ebdis = 1 , the pins will switch from i/o to exter- nal bus. if the ebdis bit is set by a program executing from external memory, the action of setting the bit will be delayed until the program branches into the internal memory. at that time, the pins will change from external bus to i/o ports. if the device is executing out of internal memory when ebdis = 0 , the memory bus address/data and control pins will not be active. they will go to a state where the active address/data pins are tri-state; the ce , oe , wrh , wrl , ub and lb signals are ? 1 ?; and ale and ba0 are ? 0 ?. note that only those pins associated with the current address width are forced to tri-state; the other pins continue to function as i/o. in the case of 16-bit address width, for example, only ad<15:0> (portd and porte) are affected; a<19:16> (porth<3:0>) continue to function as i/o. in all external memory modes, the bus takes priority over any other peripherals that may share pins with it. this includes the parallel slave port and serial commu- nications modules which would otherwise take priority over the i/o port. 7.5 16-bit data width modes in 16-bit data width mode, the external memory bus can be connected to external memories in three different configurations: 16-bit byte write 16-bit word write 16-bit byte select the configuration to be used is determined by the wm1:wm0 bits in the memcon register (memcon<1:0>). these three different configurations allow the designer maximum flexibility in using both 8-bit and 16-bit devices with 16-bit data. for all 16-bit modes, the address latch enable (ale) pin indicates that the address bits ad<15:0> are available on the external memory interface bus. following the address latch, the output enable signal (oe ) will enable both bytes of program memory at once to form a 16-bit instruction word. the chip enable signal (ce ) is active at any time that the microcontroller accesses external memory, whether reading or writing; it is inactive (asserted high) whenever the device is in sleep mode. in byte select mode, jedec standard flash memories will require ba0 for the byte address line and one i/o line to select between byte and word mode. the other 16-bit modes do not need ba0. jedec standard static ram memories will use the ub or lb signals for byte selection.
? 2004 microchip technology inc. preliminary ds39646b-page 101 pic18f8722 family 7.5.1 16-bit byte write mode figure 7-1 shows an example of 16-bit byte write mode for pic18f8527/8622/8627/8722 devices. this mode is used for two separate 8-bit memories con- nected for 16-bit operation. this generally includes basic eprom and flash devices. it allows table writes to byte-wide external memories. during a tblwt instruction cycle, the tablat data is presented on the upper and lower bytes of the ad15:ad0 bus. the appropriate wrh or wrl control line is strobed on the lsb of the tblptr. figure 7-1: 16-bit byte write mode example ad<7:0> a<19:16> (1) ale d<15:8> 373 a d<7:0> a<19:0> a d<7:0> 373 oe wrh oe oe wr (2) wr (2) ce ce note 1: upper-order address lines are used only for 20-bit address widths. 2: this signal only applies to table writes. see section 6.1 ?table reads and table writes? . wrl d<7:0> (lsb) (msb) pic18f8x27/8x22 d<7:0> ad<15:8> address bus data bus control lines ce
pic18f8722 family ds39646b-page 102 preliminary ? 2004 microchip technology inc. 7.5.2 16-bit word write mode figure 7-2 shows an example of 16-bit word write mode for pic18f8527/8622/8627/8722 devices. this mode is used for word-wide memories which includes some of the eprom and flash-type memories. this mode allows opcode fetches and table reads from all forms of 16-bit memory and table writes to any type of word-wide external memories. this method makes a distinction between tblwt cycles to even or odd addresses. during a tblwt cycle to an even address (tblptr<0> = 0 ), the tablat data is transferred to a holding latch and the external address data bus is tri-stated for the data portion of the bus cycle. no write signals are activated. during a tblwt cycle to an odd address (tblptr<0> = 1 ), the tablat data is presented on the upper byte of the ad15:ad0 bus. the contents of the holding latch are presented on the lower byte of the ad15:ad0 bus. the wrh signal is strobed for each write cycle; the wrl pin is unused. the signal on the ba0 pin indicates the least significant bit of tblptr but it is left unconnected. instead, the ub and lb signals are active to select both bytes. the obvious limitation to this method is that the table write must be done in pairs on a specific word boundary to correctly write a word location. figure 7-2: 16-bit word write mode example ad<7:0> pic18f8x27/8x22 ad<15:8> ale 373 a<20:1> 373 oe wrh a<19:16> (1) a d<15:0> oe wr (2) ce d<15:0> jedec word eprom memory address bus data bus control lines note 1: upper-order address lines are us ed only for 20-bit address widths. 2: this signal only applies to table writes. see section 6.1 ?table reads and table writes? . ce
? 2004 microchip technology inc. preliminary ds39646b-page 103 pic18f8722 family 7.5.3 16-bit byte select mode figure 7-3 shows an example of 16-bit byte select mode. this mode allows table write operations to word-wide external memories with byte selection capability. this generally includes both word-wide flash and sram devices. during a tblwt cycle, the tablat data is presented on the upper and lower byte of the ad15:ad0 bus. the wrh signal is strobed for each write cycle; the wrl pin is not used. the ba0 or ub /lb signals are used to select the byte to be written, based on the least significant bit of the tblptr register. flash and sram devices use different control signal combinations to implement byte select mode. jedec standard flash memories require that a controller i/o port pin be connected to the memory?s byte/word pin to provide the select signal. they also use the ba0 signal from the controller as a byte address. jedec standard static ram memories, on the other hand, use the ub or lb signals to select the byte. figure 7-3: 16-bit byte select mode example ad<7:0> pic18f8x27/8x22 ad<15:8> ale 373 a<20:1> 373 oe wrh a<19:16> (2) wrl ba0 jedec word a d<15:0> a<20:1> ce d<15:0> i/o oe wr (1) a0 byte/word flash memory jedec word a d<15:0> ce d<15:0> oe wr (1) lb ub sram memory lb ub 138 (3) address bus data bus control lines note 1: this signal only applies to table writes. see section 6.1 ?table reads and table writes? . 2: upper-order address lines are used only for 20-bit address width. 3: demultiplexing is only required when multiple memory devices are accessed.
pic18f8722 family ds39646b-page 104 preliminary ? 2004 microchip technology inc. 7.5.4 16-bit mode timing the presentation of control signals on the external memory bus is different for the various operating modes. typical signal timing diagrams are shown in figure 7-4 through figure 7-6. all examples assume either 20-bit or 21-bit address widths. figure 7-4: external memory bus timing for tblrd with a 1 t cy wait state (microprocessor mode) figure 7-5: external memory bus timing for tblrd (extended microcontroller mode) q2 q1 q3 q4 q2 q1 q3 q4 q4 q4 q4 q4 ale oe 3aabh wrh wrl ad<15:0> ba0 cf33h opcode fetch movlw 55h from 007556h 9256h 0e55h ? 1 ? ? 1 ? ? 1 ? ? 1 ? table read of 92h from 199e67h 1 t cy wait q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 apparent q actual q a<19:16> ce ? 0 ? ? 0 ? memory cycle instruction execution tblrd cycle 1 tblrd cycle 2 0ch 00h q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 a<19:16> ale oe ad<15:0> ce opcode fetch opcode fetch opcode fetch tblrd * tblrd cycle 1 addlw 55h from 000100h q2 q1 q3 q4 0ch cf33h tblrd 92h from 199e67h 9256h from 000104h memory cycle instruction execution inst(pc ? 2) tblrd cycle 2 movlw 55h from 000102h movlw
? 2004 microchip technology inc. preliminary ds39646b-page 105 pic18f8722 family figure 7-6: external memory bus timing for sleep (microprocessor mode) q2 q1 q3 q4 q2 q1 q3 q4 a<19:16> ale oe 3aaah ad<15:0> 00h 00h ce opcode fetch opcode fetch sleep sleep from 007554h q1 bus inactive (1) 0003h 3aabh 0e55h memory cycle instruction execution inst(pc ? 2) sleep mode, movlw 55h from 007556h note 1: bus becomes inactive regardless of power-managed mode entered when sleep is executed.
pic18f8722 family ds39646b-page 106 preliminary ? 2004 microchip technology inc. 7.6 8-bit data width modes in 8-bit data width mode, the external memory bus operates only in multiplexed mode; that is, data shares the 8 least significant bits of the address bus. figure 7-7 shows an example of 8-bit multiplexed mode for pic18f8527/8622/8627/8722 devices. this mode is used for a single 8-bit memory connected for 16-bit operation. the instructions will be fetched as two 8-bit bytes on a shared data/address bus. the two bytes are sequentially fetched within one instruction cycle (t cy ). therefore, the designer must choose external memory devices according to timing calcula- tions based on 1/2 t cy (2 times the instruction rate). for proper memory speed selection, glue logic propagation delay times must be considered along with setup and hold times. the address latch enable (ale) pin indicates that the address bits a<15:0> are available on the external memory interface bus. the output enable signal (oe ) will enable one byte of program memory for a portion of the instruction cycle, then ba0 will change and the sec- ond byte will be enabled to form the 16-bit instruction word. the least significant bit of the address, ba0, must be connected to the memory devices in this mode. the chip enable signal (ce ) is active at any time that the microcontroller accesses external memory, whether reading or writing; it is inactive (asserted high) whenever the device is in sleep mode. this generally includes basic eprom and flash devices. it allows table writes to byte-wide external memories. the appropriate level of ba0 control line is strobed on the lsb of the tblptr. figure 7-7: 8-bit multiplexed mode example ad<7:0> a<19:16> (1) ale d<15:8> 373 a<19:0> a d<7:0> oe oe wr (2) ce note 1: upper-order address bits are used only for 20-bi t address width. the upper ad byte is used for all address widths except 8-bit. 2: this signal only applies to table writes. see section 6.1 ?table reads and table writes? . wrl d<7:0> pic18f8x27/8x22 ad<15:8> (1) address bus data bus control lines ce a0 ba0
? 2004 microchip technology inc. preliminary ds39646b-page 107 pic18f8722 family 7.6.1 8-bit mode timing the presentation of control signals on the external memory bus is different for the various operating modes. typical signal timing diagrams are shown in figure 7-8 through figure 7-11. figure 7-8: external bus timing for tblrd (microprocessor mode) figure 7-9: external bus timing for tblr d (extended microcontroller mode) q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 ad<15:8>, ale oe aah wrh wrl ad<7:0> 03ah 03ah ba0 opcode fetch opcode fetch opcode fetch tblrd * tblrd cycle 1 addlw 55h from 007554h 08h ? 1 ? q2 q1 q3 q4 ccfh 33h table read 92h from 199e67h 92h ? 1 ? 00h abh 55h 0eh ach 55h 0fh 03ah ? 1 ? ? 1 ? from 007558h memory cycle instruction execution inst(pc ? 2) tblrd cycle 2 movlw 55h from 007556h movlw a<19:16> (1) note 1: the address lines actually used depends on the address width selected. this example assumes 20-bit addressing. q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 a<19:16> (1) ale oe ad<7:0> ce opcode fetch opcode fetch opcode fetch tblrd * tblrd cycle 1 addlw 55h from 000100h q2 q1 q3 q4 0ch 33h tblrd 92h from 199e67h 92h from 000104h memory cycle instruction execution inst(pc ? 2) tblrd cycle 2 movlw 55h from 000102h movlw ad<15:8> (1) cfh note 1: the address lines actually used depends on the address width selected. this example assumes 20-bit addressing.
pic18f8722 family ds39646b-page 108 preliminary ? 2004 microchip technology inc. figure 7-10: external memory bus timing for sleep (microprocessor mode) figure 7-11: typical opcode fetch, 8-bit mode q2 q1 q3 q4 q2 q1 q3 q4 a<19:16> (1) ale oe aah ad<7:0> 00h 00h ce opcode fetch opcode fetch sleep sleep from 007554h q1 bus inactive (2) 00h abh 55h memory cycle instruction execution inst(pc ? 2) sleep mode, movlw 55h from 007556h ad<15:8> (1) 3ah 3ah 03h 0eh ba0 note 1: the address lines actually used depends on the address width selected. this example assumes 20-bit addressing. 2: bus becomes inactive regardless of power-managed mode entered when sleep is executed. q2 q1 q3 q4 ad<15:8> (1) ale oe wrl ad<7:0> 03ah ba0 opcode fetch 55h 0eh ? 1 ? ? 1 ? memory cycle movlw 55h from 007556h 55h note 1: the address lines actually used depends on the address wi dth selected. this example assumes 16-bit addressing.
? 2004 microchip technology inc. preliminary ds39646b-page 109 pic18f8722 family 7.7 operation in power-managed modes in alternate power-managed run modes, the external bus continues to operate normally. if a clock source with a lower speed is selected, bus operations will run at that speed. in these cases, excessive access times for the external memory may result if wait states have been enabled and added to external memory opera- tions. if operations in a lower power run mode are anticipated, users should provide in their applications for adjusting memory access times at the lower clock speeds. in sleep and idle modes, the microcontroller core does not need to access data; bus operations are sus- pended. the state of the external bus is frozen with the address/data pins and most of the control pins holding at the same state they were in when the mode was invoked. the only potential changes are the ce , lb and ub pins which are held at logic high. table 7-3: summary of registers associated with power-managed modes name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page memcon (1) ebdis ?wait1wait0 ? ?wm1wm060 config3l (2) wait bw abw1 abw0 ? ?pm1pm0302 config3h mclre ? ? ? ? lpt1osc eccpmx (2) ccp2mx 303 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the external memory bus. note 1: this register is not implemented on 64-pin devices. 2: unimplemented in pic18f6527/6622/6627/6722 devices.
pic18f8722 family ds39646b-page 110 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39646b-page 111 pic18f8722 family 8.0 data eeprom memory the data eeprom is a nonvolatile memory array, separate from the data ram and program memory, that is used for long-term storage of program data. it is not directly mapped in either the register file or program memory space, but is indirectly addressed through the special function registers (sfrs). the eeprom is readable and writable during normal operation over the entire v dd range. five sfrs are used to read and write to the data eeprom, as well as the program memory. they are: eecon1 eecon2 eedata eeadr eeadrh the data eeprom allows byte read and write. when interfacing to the data memory block, eedata holds the 8-bit data for read/write and the eeadrh:eeadr register pair holds the address of the eeprom location being accessed. the eeprom data memory is rated for high erase/write cycle endurance. a byte write automatically erases the location and writes the new data (erase-before-write). the write time is controlled by an on-chip timer; it will vary with voltage and temperature, as well as from chip- to-chip. please refer to parameter d122 (table 28-1 in section 28.0 ?electrical characteristics? ) for exact limits. 8.1 eeadr and eeadrh registers the eeadrh:eeadr register pair is used to address the data eeprom for read and write operations. eeadrh holds the two msbs of the address; the upper 6 bits are ignored. the 10-bit range of the pair can address a memory range of 1024 bytes (00h to 3ffh). 8.2 eecon1 and eecon2 registers access to the data eeprom is controlled by two registers: eecon1 and eecon2. these are the same registers which control access to the program memory and are used in a similar manner for the data eeprom. the eecon1 register (register 8-1) is the control register for data and program memory access. control bit eepgd determines if the access will be to program or data eeprom memory. when clear, operations will access the data eeprom memory. when set, program memory is accessed. control bit cfgs determines if the access will be to the configuration registers or to program memory/data eeprom memory. when set, subsequent operations access configuration registers. when cfgs is clear, the eepgd bit selects either program flash or data eeprom memory. the wren bit, when set, will allow a write operation. on power-up, the wren bit is clear. the wrerr bit is set in hardware when the wren bit is set and cleared when the internal programming timer expires and the write operation is complete. the wr control bit initiates write operations. the bit cannot be cleared, only set, in software; it is cleared in hardware at the completion of the write operation. control bits, rd and wr, start read and erase/write operations, respectively. these bits are set by firmware and cleared by hardware at the completion of the operation. the rd bit cannot be set when accessing program memory (eepgd = 1 ). program memory is read using table read instructions. see section 6.1 ?table reads and table writes? regarding table reads. the eecon2 register is not a physical register. it is used exclusively in the memory write and erase sequences. reading eecon2 will read all ? 0 ?s. note: during normal operation, the wrerr is read as ? 1 ?. this can indicate that a write operation was prematurely terminated by a reset, or a write operation was attempted improperly. note: the eeif interrupt flag bit (pir2<4>) is set when the write is complete. it must be cleared in software.
pic18f8722 family ds39646b-page 112 preliminary ? 2004 microchip technology inc. register 8-1: eecon1: data eeprom control register 1 r/w-x r/w-x u-0 r/w-0 r/w-x r/w-0 r/s-0 r/s-0 eepgd cfgs ? free wrerr wren wr rd bit 7 bit 0 bit 7 eepgd: flash program or data eeprom memory select bit 1 = access flash program memory 0 = access data eeprom memory bit 6 cfgs: flash program/data eeprom or configuration select bit 1 = access configuration registers 0 = access flash program or data eeprom memory bit 5 unimplemented: read as ? 0 ? bit 4 free: flash row erase enable bit 1 = erase the program memory row addressed by tblptr on the next wr command (cleared by completion of erase operation) 0 = perform write only bit 3 wrerr: flash program/data eeprom error flag bit 1 = a write operation is prematurely terminated (any reset during self-timed programming in normal operation, or an improper write attempt) 0 = the write operation completed note: when a wrerr occurs, the eepgd and cfgs bits are not cleared. this allows tracing of the error condition. bit 2 wren: flash program/data eeprom write enable bit 1 = allows write cycles to flash program/data eeprom 0 = inhibits write cycles to flash program/data eeprom bit 1 wr: write control bit 1 = initiates a data eeprom erase/write cycle or a program memory erase cycle or write cycle. (the operation is self-timed and the bit is cleared by hardware once write is complete. the wr bit can only be set (not cleared) in software.) 0 = write cycle to the eeprom is complete bit 0 rd: read control bit 1 = initiates an eeprom read (read takes one cycle. rd is cleared in hardware. the rd bit can only be set (not cleared) in software. rd bit cannot be set when eepgd = 1 or cfgs = 1 .) 0 = does not initiate an eeprom read legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39646b-page 113 pic18f8722 family 8.3 reading the data eeprom memory to read a data memory location, the user must write the address to the eeadrh:eeadr register pair, clear the eepgd control bit (eecon1<7>) and then set control bit, rd (eecon1<0>). the data is available on the very next instruction cycle; therefore, the eedata register can be read by the next instruction. eedata will hold this value until another read operation, or until it is written to by the user (during a write operation). the basic process is shown in example 8-1. 8.4 writing to the data eeprom memory to write an eeprom data location, the address must first be written to the eeadrh:eeadr register pair and the data written to the eedata register. the sequence in example 8-2 must be followed to initiate the write cycle. the write will not begin if this sequence is not exactly followed (write 55h to eecon2, write 0aah to eecon2, then set wr bit) for each byte. it is strongly recommended that interrupts be disabled during this code segment. additionally, the wren bit in eecon1 must be set to enable writes. this mechanism prevents accidental writes to data eeprom due to unexpected code exe- cution (i.e., runaway programs). the wren bit should be kept clear at all times, except when updating the eeprom. the wren bit is not cleared by hardware. after a write sequence has been initiated, eecon1, eeadrh:eeadr and eedata cannot be modified. the wr bit will be inhibited from being set unless the wren bit is set. the wren bit must be set on a previous instruction. both wr and wren cannot be set with the same instruction. at the completion of the write cycle, the wr bit is cleared in hardware and the eeprom interrupt flag bit (eeif) is set. the user may either enable this interrupt, or poll this bit. eeif must be cleared by software. 8.5 write verify depending on the application, good programming practice may dictate that the value written to the mem- ory should be verified against the original value. this should be used in applications where excessive writes can stress bits near the specification limit. example 8-1: data eeprom read example 8-2: data eeprom write movlw data_ee_addrh ; movwf eeadrh ; upper bits of data memory address to read movlw data_ee_addr ; movwf eeadr ; lower bits of data memory address to read bcf eecon1, eepgd ; point to data memory bcf eecon1, cfgs ; access eeprom bsf eecon1, rd ; eeprom read movf eedata, w ; w = eedata movlw data_ee_addrh ; movwf eeadrh ; upper bits of data memory address to write movlw data_ee_addr ; movwf eeadr ; lower bits of data memory address to write movlw data_ee_data ; movwf eedata ; data memory value to write bcf eecon1, epgd ; point to data memory bcf eecon1, cfgs ; access eeprom bsf eecon1, wren ; enable writes bcf intcon, gie ; disable interrupts movlw 55h ; required movwf eecon2 ; write 55h sequence movlw 0aah ; movwf eecon2 ; write 0aah bsf eecon1, wr ; set wr bit to begin write bsf intcon, gie ; enable interrupts ; user code execution bcf eecon1, wren ; disable writes on write complete (eeif set)
pic18f8722 family ds39646b-page 114 preliminary ? 2004 microchip technology inc. 8.6 operation during code-protect data eeprom memory has its own code-protect bits in configuration words. external read and write operations are disabled if code protection is enabled. the microcontroller itself can both read and write to the internal data eeprom regardless of the state of the code-protect configuration bit. refer to section 25.0 ?special features of the cpu? for additional information. 8.7 protection against spurious write there are conditions when the device may not want to write to the data eeprom memory. to protect against spurious eeprom writes, various mechanisms have been implemented. on power-up, the wren bit is cleared. in addition, writes to the eeprom are blocked during the power-up timer period (t pwrt , parameter 33). the write initiate sequence and the wren bit together help prevent an accidental write during brown-out, power glitch or software malfunction. 8.8 using the data eeprom the data eeprom is a high endurance, byte address- able array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). frequently changing values will typically be updated more often than specification d124. if this is not the case, an array refresh must be performed. for this reason, variables that change infrequently (such as constants, ids, calibration, etc.) should be stored in flash program memory. a simple data eeprom refresh routine is shown in example 8-3. example 8-3: data eeprom refresh routine note: if data eeprom is only used to store constants and/or data that changes often, an array refresh is likely not required. see specification d124. clrf eeadr ; start at address 0 clrf eeadrh ; bcf eecon1, cfgs ; set for memory bcf eecon1, eepgd ; set for data eeprom bcf intcon, gie ; disable interrupts bsf eecon1, wren ; enable writes loop ; loop to refresh array bsf eecon1, rd ; read current address movlw 55h ; movwf eecon2 ; write 55h movlw 0aah ; movwf eecon2 ; write 0aah bsf eecon1, wr ; set wr bit to begin write btfsc eecon1, wr ; wait for write to complete bra $-2 incfsz eeadr, f ; increment address bra loop ; not zero, do it again incfsz eeadrh, f ; increment the high address bra loop ; not zero, do it again bcf eecon1, wren ; disable writes bsf intcon, gie ; enable interrupts
? 2004 microchip technology inc. preliminary ds39646b-page 115 pic18f8722 family table 8-1: registers associated with data eeprom memory name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 eeadrh ? ? ? ? ? ? eeprom address register high byte 59 eeadr eeprom address register low byte 59 eedata eeprom data register 59 eecon2 eeprom control register 2 (not a physical register) 59 eecon1 eepgd cfgs ? free wrerr wren wr rd 59 ipr2 oscfip cmip ? eeip bcl1ip hlvdip tmr3ip ccp2ip 60 pir2 oscfif cmif ? eeif bcl1if hlvdif tmr3if ccp2if 60 pie2 oscfie cmie ? eeie bcl1ie hlvdie tmr3ie ccp2ie 60 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used during flash/eeprom access.
pic18f8722 family ds39646b-page 116 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39646b-page 117 pic18f8722 family 9.0 8 x 8 hardware multiplier 9.1 introduction all pic18 devices include an 8 x 8 hardware multiplier as part of the alu. the multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, prodh:prodl. the multiplier?s operation does not affect any flags in the status register. making multiplication a hardware operation allows it to be completed in a single instruction cycle. this has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the pic18 devices to be used in many applica- tions previously reserved for digital signal processors. a comparison of various hardware and software multiply operations, along with the savings in memory and execution time, is shown in table 9-1. 9.2 operation example 9-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. only one instruction is required when one of the arguments is already loaded in the wreg register. example 9-2 shows the sequence to do an 8 x 8 signed multiplication. to account for the sign bits of the argu- ments, each argument?s most significant bit (msb) is tested and the appropriate subtractions are done. example 9-1: 8 x 8 unsigned multiply routine example 9-2: 8 x 8 signed multiply routine table 9-1: performance comparison for various multiply operations movf arg1, w ; mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl movf arg1, w mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl btfsc arg2, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg1 movf arg2, w btfsc arg1, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg2 routine multiply method program memory (words) cycles (max) time @ 40 mhz @ 10 mhz @ 4 mhz 8 x 8 unsigned without hardware multiply 13 69 6.9 s27.6 s69 s hardware multiply 1 1 100 ns 400 ns 1 s 8 x 8 signed without hardware multiply 33 91 9.1 s36.4 s91 s hardware multiply 6 6 600 ns 2.4 s6 s 16 x 16 unsigned without hardware multiply 21 242 24.2 s96.8 s 242 s hardware multiply 28 28 2.8 s 11.2 s28 s 16 x 16 signed without hardware multiply 52 254 25.4 s 102.6 s 254 s hardware multiply 35 40 4.0 s16.0 s40 s
pic18f8722 family ds39646b-page 118 preliminary ? 2004 microchip technology inc. example 9-3 shows the sequence to do a 16 x 16 unsigned multiplication. equation 9-1 shows the algorithm that is used. the 32-bit result is stored in four registers (res3:res0). equation 9-1: 16 x 16 unsigned multiplication algorithm example 9-3: 16 x 16 unsigned multiply routine example 9-4 shows the sequence to do a 16 x 16 signed multiply. equation 9-2 shows the algorithm used. the 32-bit result is stored in four registers (res3:res0). to account for the sign bits of the argu- ments, the msb for each argument pair is tested and the appropriate subtractions are done. equation 9-2: 16 x 16 signed multiplication algorithm example 9-4: 16 x 16 signed multiply routine res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 ) + (arg1h ? arg2l ? 2 8 ) + (arg1l ? arg2h ? 2 8 ) + (arg1l ? arg2l) movf arg1l, w mulwf arg2l ; arg1l * arg2l-> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movf arg1h, w mulwf arg2h ; arg1h * arg2h-> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movf arg1l, w mulwf arg2h ; arg1l * arg2h-> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; movf arg1h, w ; mulwf arg2l ; arg1h * arg2l-> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 ) + (arg1h ? arg2l ? 2 8 ) + (arg1l ? arg2h ? 2 8 ) + (arg1l ? arg2l) + (-1 ? arg2h<7> ? arg1h:arg1l ? 2 16 ) + (-1 ? arg1h<7> ? arg2h:arg2l ? 2 16 ) movf arg1l, w mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movf arg1h, w mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movf arg1l, w mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; movf arg1h, w ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; btfss arg2h, 7 ; arg2h:arg2l neg? bra sign_arg1 ; no, check arg1 movf arg1l, w ; subwf res2 ; movf arg1h, w ; subwfb res3 ; sign_arg1 btfss arg1h, 7 ; arg1h:arg1l neg? bra cont_code ; no, done movf arg2l, w ; subwf res2 ; movf arg2h, w ; subwfb res3 ; cont_code :
? 2004 microchip technology inc. preliminary ds39646b-page 119 pic18f8722 family 10.0 interrupts the pic18f8722 family of devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high priority level or a low priority level. the high priority interrupt vector is at 0008h and the low priority interrupt vector is at 0018h. high priority interrupt events will interrupt any low priority interrupts that may be in progress. there are ten registers which are used to control interrupt operation. these registers are: rcon intcon intcon2 intcon3 pir1, pir2, pir3 pie1, pie2, pie3 ipr1, ipr2, ipr3 it is recommended that the microchip header files supplied with mplab ? ide be used for the symbolic bit names in these registers. this allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. in general, interrupt sources have three bits to control their operation. they are: flag bit to indicate that an interrupt event occurred enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set priority bit to select high priority or low priority the interrupt priority feature is enabled by setting the ipen bit (rcon<7>). when interrupt priority is enabled, there are two bits which enable interrupts globally. setting the gieh bit (intcon<7>) enables all interrupts that have the priority bit set (high priority). setting the giel bit (intcon<6>) enables all interrupts that have the priority bit cleared (low priority). when the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 0008h or 0018h, depending on the priority bit setting. individual interrupts can be disabled through their corresponding enable bits. when the ipen bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with picmicro ? mid-range devices. in compatibility mode, the interrupt priority bits for each source have no effect. intcon<6> is the peie bit, which enables/disables all peripheral interrupt sources. intcon<7> is the gie bit, which enables/disables all interrupt sources. all interrupts branch to address 0008h in compatibility mode. when an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. if the ipen bit is cleared, this is the gie bit. if interrupt priority levels are used, this will be either the gieh or giel bit. high priority interrupt sources can interrupt a low priority interrupt. low priority interrupts are not processed while high priority interrupts are in progress. the return address is pushed onto the stack and the pc is loaded with the interrupt vector address (0008h or 0018h). once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. the ?return from interrupt? instruction, retfie , exits the interrupt routine and sets the gie bit (gieh or giel if priority levels are used), which re-enables interrupts. for external interrupt events, such as the int pins or the portb input change interrupt, the interrupt latency will be three to four instruction cycles. the exact latency is the same for one or two-cycle instructions. individual interrupt flag bits are set, regardless of the status of their corresponding enable bit or the gie bit. note: do not use the movff instruction to modify any of the interrupt control registers while any interrupt is enabled. doing so may cause erratic microcontroller behavior.
pic18f8722 family ds39646b-page 120 preliminary ? 2004 microchip technology inc. figure 10-1: pic18f8722 family interrupt logic tmr0ie gieh/gie giel/peie wake-up if in interrupt to cpu vector to location 0008h int2if int2ie int2ip int1if int1ie int1ip tmr0if tmr0ie tmr0ip rbif rbie rbip ipen tmr0if tmr0ip int1if int1ie int1ip int2if int2ie int2ip rbif rbie rbip int0if int0ie giel/peie interrupt to cpu vector to location ipen ipen 0018h pir1<7:0> pie1<7:0> ipr1<7:0> high priority interrupt generation low priority interrupt generation idle or sleep modes gieh/gie int3if int3ie int3ip int3if int3ie int3ip pir2<7:6, 4:0> pie2<7:6, 4:0> ipr2<7:6, 4:0> pir3<7:0> pie3<7:0> ipr3<7:0> pir1<7:0> pie1<7:0> ipr1<7:0> pir2<7:6, 4:0> pie2<7:6, 4:0> ipr2<7:6, 4:0> pir3<7:0> pie3<7:0> ipr3<7:0> ipen
? 2004 microchip technology inc. preliminary ds39646b-page 121 pic18f8722 family 10.1 intcon registers the intcon registers are readable and writable registers which contain various enable, priority and flag bits. register 10-1: intcon: interrupt control register note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif bit 7 bit 0 bit 7 gie/gieh: global interrupt enable bit when ipen = 0 : 1 = enables all unmasked interrupts 0 = disables all interrupts when ipen = 1 : 1 = enables all high priority interrupts 0 = disables all interrupts bit 6 peie/giel: peripheral interrupt enable bit when ipen = 0 : 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts when ipen = 1 : 1 = enables all low priority peripheral interrupts 0 = disables all low priority peripheral interrupts bit 5 tmr0ie: tmr0 overflow interrupt enable bit 1 = enables the tmr0 overflow interrupt 0 = disables the tmr0 overflow interrupt bit 4 int0ie: int0 external interrupt enable bit 1 = enables the int0 external interrupt 0 = disables the int0 external interrupt bit 3 rbie: rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 tmr0if: tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 int0if: int0 external interrupt flag bit 1 = the int0 external interrupt occurred (must be cleared in software) 0 = the int0 external interrupt did not occur bit 0 rbif: rb port change interrupt flag bit 1 = at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state note: a mismatch condition will continue to set this bit. reading portb will end the mismatch condition and allow the bit to be cleared. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 122 preliminary ? 2004 microchip technology inc. register 10-2: intcon2: interrupt control register 2 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg0 intedg1 intedg2 i ntedg3 tmr0ip int3ip rbip bit 7 bit 0 bit 7 rbpu : portb pull-up enable bit 1 = all portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg0: external interrupt 0 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 5 intedg1: external interrupt 1 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 4 intedg2: external interrupt 2 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 3 intedg3: external interrupt 3 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 2 tmr0ip: tmr0 overflow interrupt priority bit 1 = high priority 0 = low priority bit 1 int3ip: int3 external interrupt priority bit 1 = high priority 0 = low priority bit 0 rbip: rb port change interrupt priority bit 1 = high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling.
? 2004 microchip technology inc. preliminary ds39646b-page 123 pic18f8722 family register 10-3: intcon3: interrupt control register 3 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 int2ip int1ip int3ie int2ie int1ie int3if int2if int1if bit 7 bit 0 bit 7 int2ip: int2 external interrupt priority bit 1 = high priority 0 = low priority bit 6 int1ip: int1 external interrupt priority bit 1 = high priority 0 = low priority bit 5 int3ie: int3 external interrupt enable bit 1 = enables the int3 external interrupt 0 = disables the int3 external interrupt bit 4 int2ie: int2 external interrupt enable bit 1 = enables the int2 external interrupt 0 = disables the int2 external interrupt bit 3 int1ie: int1 external interrupt enable bit 1 = enables the int1 external interrupt 0 = disables the int1 external interrupt bit 2 int3if: int3 external interrupt flag bit 1 = the int3 external interrupt occurred (must be cleared in software) 0 = the int3 external interrupt did not occur bit 1 int2if: int2 external interrupt flag bit 1 = the int2 external interrupt occurred (must be cleared in software) 0 = the int2 external interrupt did not occur bit 0 int1if: int1 external interrupt flag bit 1 = the int1 external interrupt occurred (must be cleared in software) 0 = the int1 external interrupt did not occur legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling.
pic18f8722 family ds39646b-page 124 preliminary ? 2004 microchip technology inc. 10.2 pir registers the pir registers contain the individual flag bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are three peripheral interrupt request (flag) registers (pir1, pir2, pir3). register 10-4: pir1: peripheral interrupt request (flag) register 1 note 1: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit, gie (intcon<7>). 2: user software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if bit 7 bit 0 bit 7 pspif: parallel slave port read/write interrupt flag bit 1 = a read or a write operation has taken place (must be cleared in software) 0 = no read or write has occurred bit 6 adif: a/d converter interrupt flag bit 1 = an a/d conversion completed (must be cleared in software) 0 = the a/d conversion is not complete bit 5 rc1if: eusart1 receive interrupt flag bit 1 = the eusart1 receive buffer, rcreg1, is full (cleared when rcreg1 is read) 0 = the eusart1 receive buffer is empty bit 4 tx1if: eusart1 transmit interrupt flag bit 1 = the eusart1 transmit buffer, txreg1, is empty (cleared when txreg1 is written) 0 = the eusart1 transmit buffer is full bit 3 ssp1if: mssp1 interrupt flag bit 1 = the transmission/reception is complete (must be cleared in software) 0 = waiting to transmit/receive bit 2 ccp1if: eccp1 interrupt flag bit capture mode: 1 = a tmr1/tmr3 register capture occurred (must be cleared in software) 0 = no tmr1/tmr3 register capture occurred compare mode: 1 = a tmr1/tmr3 register compare match occurred (must be cleared in software) 0 = no tmr1/tmr3 register compare match occurred pwm mode: unused in this mode. bit 1 tmr2if: tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0 tmr1if: tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39646b-page 125 pic18f8722 family register 10-5: pir2: peripheral interrupt request (flag) register 2 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 oscfif cmif ? eeif bcl1if hlvdif tmr3if ccp2if bit 7 bit 0 bit 7 oscfif: oscillator fail interrupt flag bit 1 = device oscillator failed, clock input has changed to intosc (must be cleared in software) 0 = device clock operating bit 6 cmif: comparator interrupt flag bit 1 = comparator input has changed (must be cleared in software) 0 = comparator input has not changed bit 5 unimplemented: read as ? 0 ? bit 4 eeif: eeprom or flash write operation interrupt flag bit 1 = the write operation is complete (must be cleared in software) 0 = the write operation is not complete or has not been started bit 3 bcl1if: mssp1 bus collision interrupt flag bit 1 = a bus collision occurred while the mssp1 module configured in i 2 c? master mode was transmitting (must be cleared in software) 0 = no bus collision occurred bit 2 hlvdif: high/low-voltage detect interrupt flag bit 1 = a low-voltage condition occurred (must be cleared in software) 0 = the device voltage is above the low-voltage detect trip point bit 1 tmr3if: tmr3 overflow interrupt flag bit 1 = tmr3 register overflowed (must be cleared in software) 0 = tmr3 register did not overflow bit 0 ccp2if: eccp2 interrupt flag bit capture mode: 1 = a tmr1/tmr3 register capture occurred (must be cleared in software) 0 = no tmr1/tmr3 register capture occurred compare mode: 1 = a tmr1/tmr3 register compare match occurred (must be cleared in software) 0 = no tmr1/tmr3 register compare match occurred pwm mode: unused in this mode. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 126 preliminary ? 2004 microchip technology inc. register 10-6: pir3: peripheral interrupt request (flag) register 3 r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 ssp2if bcl2if rc2if tx2if tmr4if ccp5if ccp4if ccp3if bit 7 bit 0 bit 7 ssp2if: mssp2 interrupt flag bit 1 = the transmission/reception is complete (must be cleared in software) 0 = waiting to transmit/receive bit 6 bcl2if: mssp2 bus collision interrupt flag bit 1 = a bus collision has occurred while the mssp2 module configured in i 2 c? master was transmitting (must be cleared in software) 0 = no bus collision occurred bit 5 rc2if: eusart2 receive interrupt flag bit 1 = the eusart2 receive buffer, rcreg2, is full (cleared when rcreg2 is read) 0 = the eusart2 receive buffer is empty bit 4 tx2if: eusart2 transmit interrupt flag bit 1 = the eusart2 transmit buffer, txreg2, is empty (cleared when txreg2 is written) 0 = the eusart2 transmit buffer is full bit 3 tmr4if: tmr4 to pr4 match interrupt flag bit 1 = tmr4 to pr4 match occurred (must be cleared in software) 0 = no tmr4 to pr4 match occurred bit 2 ccp5if: ccp5 interrupt flag bit capture mode : 1 = a tmr register capture occurred (must be cleared in software) 0 = no tmr register capture occurred compare mode : 1 = a tmr register compare match occurred (must be cleared in software) 0 = no tmr register compare match occurred pwm mode: not used in pwm mode bit 1 ccp4if: ccp4 interrupt flag bit capture mode: 1 = a tmr register capture occurred (must be cleared in software) 0 = no tmr register capture occurred compare mode : 1 = a tmr register compare match occurred (must be cleared in software) 0 = no tmr register compare match occurred pwm mode: not used in pwm mode bit 0 ccp3if: eccp3 interrupt flag bit capture mode: 1 = a tmr register capture occurred (must be cleared in software) 0 = no tmr register capture occurred compare mode : 1 = a tmr register compare match occurred (must be cleared in software) 0 = no tmr register compare match occurred pwm mode: not used in pwm mode legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39646b-page 127 pic18f8722 family 10.3 pie registers the pie registers contain the individual enable bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are three peripheral interrupt enable registers (pie1, pie2, pie3). when ipen = 0 , the peie bit must be set to enable any of these peripheral interrupts. register 10-7: pie1: peripheral interrupt enable register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie bit 7 bit 0 bit 7 pspie: parallel slave port read/write interrupt enable bit 1 = enables the psp read/write interrupt 0 = disables the psp read/write interrupt bit 6 adie: a/d converter interrupt enable bit 1 = enables the a/d interrupt 0 = disables the a/d interrupt bit 5 rc1ie: eusart1 receive interrupt enable bit 1 = enables the eusart1 receive interrupt 0 = disables the eusart1 receive interrupt bit 4 tx1ie: eusart1 transmit interrupt enable bit 1 = enables the eusart1 transmit interrupt 0 = disables the eusart1 transmit interrupt bit 3 ssp1ie: mssp1 interrupt enable bit 1 = enables the mssp1 interrupt 0 = disables the mssp1 interrupt bit 2 ccp1ie: eccp1 interrupt enable bit 1 = enables the eccp1 interrupt 0 = disables the eccp1 interrupt bit 1 tmr2ie: tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0 tmr1ie: tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 128 preliminary ? 2004 microchip technology inc. register 10-8: pie2: peripheral interrupt enable register 2 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 oscfie cmie ? eeie bcl1ie hlvdie tmr3ie ccp2ie bit 7 bit 0 bit 7 oscfie: oscillator fail interrupt enable bit 1 = enabled 0 =disabled bit 6 cmie: comparator interrupt enable bit 1 = enabled 0 =disabled bit 5 unimplemented: read as ? 0 ? bit 4 eeie: interrupt enable bit 1 = enabled 0 =disabled bit 3 bcl1ie: mssp1 bus collision interrupt enable bit 1 = enabled 0 =disabled bit 2 hlvdie: high/low-voltage detect interrupt enable bit 1 = enabled 0 =disabled bit 1 tmr3ie: tmr3 overflow interrupt enable bit 1 = enabled 0 =disabled bit 0 ccp2ie: eccp2 interrupt enable bit 1 = enabled 0 =disabled legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39646b-page 129 pic18f8722 family register 10-9: pie3: peripheral interrupt enable register 3 r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 ssp2ie bcl2ie rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie bit 7 bit 0 bit 7 ssp2ie: mssp2 interrupt enable bit 1 = enables the mssp2 interrupt 0 = disables the mssp2 interrupt bit 6 bcl2ie: mssp2 bus collision interrupt enable bit 1 = enabled 0 = disabled bit 5 rc2ie: eusart2 receive interrupt enable bit 1 = enabled 0 = disabled bit 4 tx2ie: eusart2 transmit interrupt enable bit 1 = enabled 0 = disabled bit 3 tmr4ie: tmr4 to pr4 match interrupt enable bit 1 = enabled 0 = disabled bit 2 ccp5ie: ccp5 interrupt enable bit 1 = enabled 0 = disabled bit 1 ccp4ie: ccp4 interrupt enable bit 1 = enabled 0 = disabled bit 0 ccp3ie: eccp3 interrupt enable bit 1 = enabled 0 = disabled legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 130 preliminary ? 2004 microchip technology inc. 10.4 ipr registers the ipr registers contain the individual priority bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are three peripheral interrupt priority registers (ipr1, ipr2, ipr3). using the priority bits requires that the interrupt priority enable (ipen) bit be set. register 10-10: ipr1: peripheral interrupt priority register 1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip bit 7 bit 0 bit 7 pspip: parallel slave port read/write interrupt priority bit 1 =high priority 0 = low priority bit 6 adip: a/d converter interrupt priority bit 1 =high priority 0 = low priority bit 5 rc1ip: eusart1 receive interrupt priority bit 1 =high priority 0 = low priority bit 4 tx1ip: eusart1 transmit interrupt priority bit 1 =high priority 0 = low priority bit 3 ssp1ip: mssp1 interrupt priority bit 1 =high priority 0 = low priority bit 2 ccp1ip: eccp1 interrupt priority bit 1 =high priority 0 = low priority bit 1 tmr2ip: tmr2 to pr2 match interrupt priority bit 1 =high priority 0 = low priority bit 0 tmr1ip: tmr1 overflow interrupt priority bit 1 =high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39646b-page 131 pic18f8722 family register 10-11: ipr2: peripheral interrupt priority register 2 r/w-1 r/w-1 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 oscfip cmip ? eeip bcl1ip hlvdip tmr3ip ccp2ip bit 7 bit 0 bit 7 oscfip: oscillator fail interrupt priority bit 1 =high priority 0 = low priority bit 6 cmip: comparator interrupt priority bit 1 =high priority 0 = low priority bit 5 unimplemented: read as ? 0 ? bit 4 eeip: interrupt priority bit 1 =high priority 0 = low priority bit 3 bcl1ip: mssp1 bus collision interrupt priority bit 1 =high priority 0 = low priority bit 2 hlvdip: high/low-voltage detect interrupt priority bit 1 =high priority 0 = low priority bit 1 tmr3ip: tmr3 overflow interrupt priority bit 1 =high priority 0 = low priority bit 0 ccp2ip: eccp2 interrupt priority bit 1 =high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 132 preliminary ? 2004 microchip technology inc. register 10-12: ipr3: peripheral interrupt priority register 3 r/w-0 r/w-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ssp2ip bcl2ip rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip bit 7 bit 0 bit 7 ssp2ip: mssp2 interrupt priority bit 1 = high priority 0 = low priority bit 6 bcl2ip: mssp2 bus collision interrupt priority bit 1 = high priority 0 = low priority bit 5 rc2ip: eusart2 receive interrupt priority bit 1 = high priority 0 = low priority bit 4 tx2ip: eusart2 transmit interrupt priority bit 1 = high priority 0 = low priority bit 3 tmr4ip: tmr4 to pr4 match interrupt priority bit 1 = high priority 0 = low priority bit 2 ccp5ip: ccp5 interrupt priority bit 1 = high priority 0 = low priority bit 1 ccp4ip: ccp4 interrupt priority bit 1 = high priority 0 = low priority bit 0 ccp3ip: eccp3 interrupt priority bit 1 = high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39646b-page 133 pic18f8722 family 10.5 rcon register the rcon register contains bits used to determine the cause of the last reset or wake-up from idle or sleep modes. rcon also contains the bit that enables interrupt priorities (ipen). register 10-13: rcon: reset control re gister r/w-0 r/w-1 u-0 r/w-1 r-1 r-1 r/w-0 r/w-0 ipen sboren ?ri to pd por bor bit 7 bit 0 bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (pic16cxxx compatibility mode) bit 6 sboren: software bor enable bit for details of bit operation and reset state, see register 4-1. bit 5 unimplemented: read as ? 0 ? bit 4 ri : reset instruction flag bit for details of bit operation, see register 4-1. bit 3 to : watchdog timer time-out flag bit for details of bit operation, see register 4-1. bit 2 pd : power-down detection flag bit for details of bit operation, see register 4-1. bit 1 por : power-on reset status bit for details of bit operation, see register 4-1. bit 0 bor : brown-out reset status bit for details of bit operation, see register 4-1. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 134 preliminary ? 2004 microchip technology inc. 10.6 intn pin interrupts external interrupts on the rb0/int0, rb1/int1, rb2/ int2 and rb3/int3 pins are edge-triggered. if the corresponding intedgx bit in the intcon2 register is set (= 1 ), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. when a valid edge appears on the rbx/intx pin, the corresponding flag bit, intxif, is set. this interrupt can be disabled by clearing the corresponding enable bit, intxie. flag bit, intxif, must be cleared in software in the interrupt service routine before re-enabling the interrupt. all external interrupts (int0, int1, int2 and int3) can wake-up the processor from the power-managed modes if bit intxie was set prior to going into power- managed modes. if the global interrupt enable bit, gie, is set, the processor will branch to the interrupt vector following wake-up. interrupt priority for int1, int2 and int3 is determined by the value contained in the interrupt priority bits, int1ip (intcon3<6>), int2ip (intcon3<7>) and int3ip (intcon2<1>). there is no priority bit associated with int0. it is always a high priority interrupt source. 10.7 tmr0 interrupt in 8-bit mode (which is the default), an overflow in the tmr0 register (ffh 00h) will set flag bit, tmr0if. in 16-bit mode, an overflow in the tmr0h:tmr0l register pair (ffffh 0000h) will set tmr0if. the interrupt can be enabled/disabled by setting/clearing enable bit, tmr0ie (intcon<5>). interr upt priority for timer0 is determined by the value contained in the interrupt priority bit, tmr0ip (intcon2<2>). see section 12.0 ?timer0 module? for further details on the timer0 module. 10.8 portb interrupt-on-change an input change on portb<7:4> sets flag bit, rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit, rbie (intcon<3>). interrupt priority for portb interrupt-on-change is determined by the value contained in the interrupt priority bit, rbip (intcon2<0>). 10.9 context saving during interrupts during interrupts, the return pc address is saved on the stack. additionally, the wreg, status and bsr registers are saved on the fast return stack. if a fast return from interrupt is not used (see section 5.3 ?data memory organization? ), the user may need to save the wreg, status and bsr registers on entry to the interrupt service routine. depending on the user?s application, other registers may also need to be saved. example 10-1 saves and restores the wreg, status and bsr registers during an interrupt service routine. example 10-1: saving status, wreg and bsr registers in ram movwf w_temp ; w_temp is in virtual bank movff status, status_temp ; status_temp located anywhere movff bsr, bsr_temp ; bsr_tmep located anywhere ; ; user isr code ; movff bsr_temp, bsr ; restore bsr movf w_temp, w ; restore wreg movff status_temp, status ; restore status
? 2004 microchip technology inc. preliminary ds39646b-page 135 pic18f8722 family 11.0 i/o ports depending on the device selected and features enabled, there are up to nine ports available. some pins of the i/o ports are multiplexed with an alternate function from the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. each port has three registers for its operation. these registers are: tris register (data direction register) port register (reads the levels on the pins of the device) lat register (output latch) the data latch (lat register) is useful for read-modify-write operations on the value that the i/o pins are driving. a simplified model of a generic i/o port, without the interfaces to other peripherals, is shown in figure 11-1. figure 11-1: generic i/o port operation 11.1 porta, trisa and lata registers porta is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisa. setting a trisa bit (= 1 ) will make the corresponding porta pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisa bit (= 0 ) will make the corresponding porta pin an output (i.e., put the contents of the output latch on the selected pin). reading the porta register reads the status of the pins, whereas writing to it, will write to the port latch. the data latch register (lata) is also memory mapped. read-modify-write operations on the lata register read and write the latched output value for porta. the ra4 pin is multiplexed with the timer0 module clock input to become the ra4/t0cki pin. pins ra6 and ra7 are multiplexed with the main oscillator pins; they are enabled as oscillator or i/o pins by the selec- tion of the main oscillator in the configuration register (see section 25.1 ?configuration bits? for details). when they are not used as port pins, ra6 and ra7 and their associated tris and lat bits are read as ? 0 ?. the other porta pins are multiplexed with the analog v ref + and v ref - inputs. the operation of pins ra5:ra0 as a/d converter inputs is selected by clearing or setting the pcfg3:pcfg0 control bits in the adcon1 register. the ra4/t0cki pin is a schmitt trigger input and an open-drain output. all other porta pins have ttl input levels and full cmos output drivers. the trisa register controls the direction of the porta pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. example 11-1: initializing porta data bus wr lat wr tris rd port data latch tris latch rd tris input buffer i/o pin (1) q d ckx q d ckx en qd en rd lat or port note 1: i/o pins have diode protection to v dd and v ss . note: on a power-on reset, ra5 and ra3:ra0 are configured as analog inputs and read as ? 0 ?. ra4 is configured as a digital input. clrf porta ; initialize porta by ; clearing output ; data latches clrf lata ; alternate method ; to clear output ; data latches movlw 0fh ; configure a/d movwf adcon1 ; for digital inputs movlw 0cfh ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra<5:4> as outputs
pic18f8722 family ds39646b-page 136 preliminary ? 2004 microchip technology inc. table 11-1: porta functions table 11-2: summary of registers associated with porta pin name function tris setting i/o i/o type description ra0/an0 ra0 0 o dig lata<0> data output; not affected by analog input. 1 i ttl porta<0> data input; disabled when analog input enabled. an0 1 i ana a/d input channel 0. default input configuration on por; does not affect digital output. ra1/an1 ra1 0 o dig lata<1> data output; not affected by analog input. 1 i ttl porta<1> data input; disabled when analog input enabled. an1 1 i ana a/d input channel 1. default input configuration on por; does not affect digital output. ra2/an2/v ref -ra2 0 o dig lata<2> data output; not affected by analog input. 1 i ttl porta<2> data input. disabled when analog functions enabled. an2 1 i ana a/d input channel 2. default input configuration on por. v ref - 1 i ana comparator voltage reference low input and a/d voltage reference low input. ra3/an3/v ref +ra3 0 o dig lata<3> data output; not affected by analog input. 1 i ttl porta<3> data input; disabled when analog input enabled. an3 1 i ana a/d input channel 3. default input configuration on por. v ref + 1 i ana comparator voltage reference high input and a/d voltage reference high input. ra4/t0cki ra4 0 o dig lata<4> data output. 1 i st porta<4> data input; default configuration on por. t0cki x i st timer0 clock input. ra5/an4/hlvdin ra5 0 o dig lata<5> data output; not affected by analog input. 1 i ttl porta<5> data input; disabled when analog input enabled. an4 1 i ana a/d input channel 4. default configuration on por. hlvdin 1 i ana high/low-voltage detect external trip point input. osc2/clko/ra6 osc2 x o ana main oscillator feedback output connection (xt, hs, hspll and lp modes). clko x o dig system cycle clock output (f osc /4) in all oscillator modes except rc, intio7 and ec. ra6 0 o dig lata<6> data output. enabled in rcio, intio2 and ecio modes only. 1 i ttl porta<6> data input. enabled in rcio, intio2 and ecio modes only. osc1/clki/ra7 osc1 x i ana main oscillator input connection. clki x i ana main clock input connection. ra7 0 o dig lata<7> data output. disabled in external oscillator modes. 1 i ttl porta<7> data input. disabled in external oscillator modes. legend: pwr = power supply, o = output, i = input, ana = analog signal, dig = digital output, st= schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page porta ra7 (1) ra6 (1) ra5 ra4 ra3 ra2 ra1 ra0 61 lata lata7 (1) lata6 (1) lata5 lata4 lata3 lata2 lata1 lata0 60 trisa trisa7 (1) trisa6 (1) trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 60 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 59 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by porta. note 1: ra7:ra6 and their associated latch and data direction bits are enabled as i/o pins based on oscillator configuration; otherwise, they are read as ? 0 ?.
? 2004 microchip technology inc. preliminary ds39646b-page 137 pic18f8722 family 11.2 portb, trisb and latb registers portb is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisb. setting a trisb bit (= 1 ) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisb bit (= 0 ) will make the corresponding portb pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latb) is also memory mapped. read-modify-write operations on the latb register read and write the latched output value for portb. example 11-2: initializing portb each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is performed by clearing bit rbpu (intcon2<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on a power-on reset. four of the portb pins (rb7:rb4) have an interrupt-on-change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb7:rb4 pin configured as an output is excluded from the interrupt-on-change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the ?mismatch? outputs of rb7:rb4 are ored together to generate the rb port change interrupt with flag bit, rbif (intcon<0>). this interrupt can wake the device from power-managed modes. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb (except with the movsf, movss, movff (any), portb instruction). this will end the mismatch condition. b) clear flag bit rbif. a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt-on-change feature. polling of portb is not recommended while using the interrupt-on-change feature. for 80-pin devices, rb3 can be configured as the alternate peripheral pin for the eccp2 module by clearing the ccp2mx configuration bit. this applies only when the device is in one of the operating modes other than the default microcontroller mode. if the device is in microcontroller mode, the alternate assignment for eccp2 is re7. as with other eccp2 configurations, the user must ensure that the trisb<3> bit is set appropriately for the intended operation. clrf portb ; initialize portb by ; clearing output ; data latches clrf latb ; alternate method ; to clear output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs
pic18f8722 family ds39646b-page 138 preliminary ? 2004 microchip technology inc. table 11-3: portb functions pin name function tris setting i/o i/o type description rb0/int0/flt0 rb0 0 o dig latb<0> data output. 1 i ttl portb<0> data input; weak pull-up when rbpu bit is cleared. int0 1 i st external interrupt 0 input. flt0 1 i st eccpx pwm fault input, enabled in software. rb1/int1 rb1 0 o dig latb<1> data output. 1 i ttl portb<1> data input; weak pull-up when rbpu bit is cleared. int1 1 i st external interrupt 1 input. rb2/int2 rb2 0 o dig latb<2> data output. 1 i ttl portb<2> data input; weak pull-up when rbpu bit is cleared. int2 1 i st external interrupt 2 input. rb3/int3/ eccp2/p2a rb3 0 o dig latb<3> data output. 1 i ttl portb<3> data input; weak pull-up when rbpu bit is cleared and capture input is disabled. int3 1 i st external interrupt 3 input. eccp2 (1) 0 o dig eccp2 compare output and eccp2 pwm output. takes priority over port data. 1 i st eccp2 capture input. p2a (1) 0 o dig eccp2 enhanced pwm output, channel a. may be configured for tri-state during enhanced pwm shutdow n events. takes priority over port data. rb4/kbi0 rb4 0 o dig latb<4> data output. 1 i ttl portb<4> data input; weak pull-up when rbpu bit is cleared. kbi0 1 i ttl interrupt-on-pin change. rb5/kbi1/pgm rb5 0 o dig latb<5> data output 1 i ttl portb<5> data input; weak pull-up when rbpu bit is cleared. kbi1 1 i ttl interrupt-on-pin change. pgm x i st single-supply programming mode entry (icsp). enabled by lvp configuration bit; all other pin functions disabled. rb6/kbi2/pgc rb6 0 o dig latb<6> data output. 1 i ttl portb<6> data input; weak pull-up when rbpu bit is cleared. kbi2 1 i ttl interrupt-on-pin change. pgc x i st serial execution (icsp?) clock input for icsp and icd operation (2) . rb7/kbi3/pgd rb7 0 o dig latb<7> data output. 1 i ttl portb<7> data input; weak pull-up when rbpu bit is cleared. kbi3 1 i ttl interrupt-on-pin change. pgd x o dig serial execution data output for icsp and icd operation (2) . x i st serial execution data input for icsp and icd operation (2) . legend: pwr = power supply, o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: alternate assignment for eccp2 when the ccp2mx c onfiguration bit is clear ed (microprocessor, extended microcontroller and microcontroller with boot block m odes, 80-pin devices only). default assignment is rc1. 2: all other pin functions are disabled when icsp or icd operations are enabled.
? 2004 microchip technology inc. preliminary ds39646b-page 139 pic18f8722 family table 11-4: summary of registers associated with portb name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 60 latb latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 60 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 60 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 intcon2 rbpu intedg0 intedg1 intedg2 intedg3 tmr0ip int3ip rbip 57 intcon3 int2ip int1ip int3ie int2ie int1ie int3if int2if int1if 57 legend: shaded cells are not used by portb.
pic18f8722 family ds39646b-page 140 preliminary ? 2004 microchip technology inc. 11.3 portc, trisc and latc registers portc is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisc. setting a trisc bit (= 1 ) will make the corresponding portc pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisc bit (= 0 ) will make the corresponding portc pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latc) is also memory mapped. read-modify-write operations on the latc register read and write the latched output value for portc. portc is multiplexed with several peripheral functions. all port pins have schmitt trigger input buffers. rc1 is normally configured by configuration bit ccp2mx as the default peripheral pin of the eccp2 module (default/erased state, ccp2mx = 1 ). when enabling peripheral functions, care should be taken in defining tris bits for each portc pin. some peripherals override the tris bit to make a pin an output, while other peripherals override the tris bit to make a pin an input. the user should refer to the corresponding peripheral section for the correct tris bit settings. the contents of the trisc register are affected by peripheral overrides. reading trisc always returns the current contents, even though a peripheral device may be overriding one or more of the pins. example 11-3: initializing portc note: on a power-on reset, these pins are configured as digital inputs. clrf portc ; initialize portc by ; clearing output ; data latches clrf latc ; alternate method ; to clear output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisc ; set rc<3:0> as inputs ; rc<5:4> as outputs ; rc<7:6> as inputs
? 2004 microchip technology inc. preliminary ds39646b-page 141 pic18f8722 family table 11-5: portc functions pin name function tris setting i/o i/o type description rc0/t1oso/t13cki rc0 0 o dig latc<0> data output. 1 i st portc<0> data input. t1oso x o ana timer1 oscillator output; enabled when timer1 oscillator enabled. disables digital i/o. t13cki 1 i st timer1/timer3 counter input. rc1/t1osi/ eccp2/p2a rc1 0 o dig latc<1> data output. 1 i st portc<1> data input. t1osi x i ana timer1 oscillator input; enabled when timer1 oscillator enabled. disables digital i/o. eccp2 (1) 0 o dig eccp2 compare output and eccp2 pwm output. takes priority over port data. 1 i st eccp2 capture input. p2a (1) 0 o dig eccp2 enhanced pwm output, channel a. may be configured for tri-state during enhanced pwm shutdow n events. takes priority over port data. rc2/eccp1/p1a rc2 0 o dig latc<2> data output. 1 i st portc<2> data input. eccp1 0 o dig eccp1 compare output and eccp1 pwm output. takes priority over port data. 1 i st eccp1 capture input. p1a 0 o dig eccp1 enhanced pwm output, channel a. may be configured for tri-state during enhanced pwm shutdow n events. takes priority over port data. rc3/sck1/scl1 rc3 0 o dig latc<3> data output. 1 i st portc<3> data input. sck1 0 o dig spi? clock output (mssp1 module). takes priority over port data. 1 i st spi clock input (mssp1 module). scl1 0 odigi 2 c? clock output (mssp1 module). takes priority over port data. 1 ii 2 c/smb i 2 c clock input (mssp1 module); input type depends on module setting. rc4/sdi1/sda1 rc4 0 o dig latc<4> data output. 1 i st portc<4> data input. sdi1 1 i st spi data input (mssp1 module). sda1 1 odigi 2 c data output (mssp1 module). takes priority over port data. 1 ii 2 c/smb i 2 c data input (mssp1 module); input type depends on module setting. rc5/sdo1 rc5 0 o dig latc<5> data output. 1 i st portc<5> data input. sdo1 0 o dig spi data output (mssp1 module). takes priority over port data. legend: dig = digital level output; ttl = ttl input buffer; st = schmitt trigger input buffer; ana = analog level input/output; i 2 c/smb = i 2 c/smbus input buffer; x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: default assignment for eccp2 when ccp2mx configuration bit is set.
pic18f8722 family ds39646b-page 142 preliminary ? 2004 microchip technology inc. table 11-6: summary of registers associated with portc rc6/tx1/ck1 rc6 0 o dig latc<6> data output. 1 i st portc<6> data input. tx1 0 o dig asynchronous serial transmit data output (eusart1 module). takes priority over port data. ck1 0 o dig synchronous serial clock output (eusart1 module). takes priority over port data. 1 i st synchronous serial clock input (eusart1 module). rc7/rx1/dt1 rc7 0 o dig latc<7> data output. 1 i st portc<7> data input. rx1 1 i st asynchronous serial receive data input (eusart1 module) dt1 1 o dig synchronous serial data output (eusart1 module). takes priority over port data. user must configure as input. 1 i st synchronous serial data input (eusart1 module). user must configure as an input. table 11-5: portc functions (continued) pin name function tris setting i/o i/o type description legend: dig = digital level output; ttl = ttl input buffer; st = schmitt trigger input buffer; ana = analog level input/output; i 2 c/smb = i 2 c/smbus input buffer; x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: default assignment for eccp2 when ccp2mx configuration bit is set. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 60 latc latc7 latc6 latc5 latc4 latc3 latc2 latc1 latc0 60 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 60
? 2004 microchip technology inc. preliminary ds39646b-page 143 pic18f8722 family 11.4 portd, trisd and latd registers portd is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisd. setting a trisd bit (= 1 ) will make the corresponding portd pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisd bit (= 0 ) will make the corresponding portd pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latd) is also memory mapped. read-modify-write operations on the latd register read and write the latched output value for portd. all pins on portd are implemented with schmitt trigger input buffers. each pin is individually configurable as an input or output. in 80-pin devices, portd is multiplexed with the system bus as part of the external memory interface. i/o port and other functions are only available when the interface is disabled by setting the ebdis bit (memcon<7>). when the interface is enabled, portd is the low-order byte of the multiplexed address/data bus (ad7:ad0). the trisd bits are also overridden. portd can also be configured to function as an 8-bit wide parallel microprocessor port by setting the pspmode control bit (pspcon<4>). in this mode, parallel port data takes priority over other digital i/o (but not the external memory interface). when the parallel port is active, the input buffers are ttl. for more information, refer to section 11.10 ?parallel slave port? . example 11-4: initializing portd note: on a power-on reset, these pins are configured as digital inputs. clrf portd ; initialize portd by ; clearing output ; data latches clrf latd ; alternate method ; to clear output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisd ; set rd<3:0> as inputs ; rd<5:4> as outputs ; rd<7:6> as inputs
pic18f8722 family ds39646b-page 144 preliminary ? 2004 microchip technology inc. table 11-7: portd functions pin name function tris setting i/o i/o type description rd0/ad0/psp0 rd0 0 o dig latd<0> data output. 1 i st portd<0> data input. ad0 (1) x o dig external memory interface, address/data bit 0 output. takes priority over psp and port data. x i ttl external memory interface, data bit 0 input. psp0 x o dig psp read data output (latd<0>). takes priority over port data. x i ttl psp write data input. rd1/ad1/psp1 rd1 0 o dig latd<1> data output. 1 i st portd<1> data input. ad1 (1) x o dig external memory interface, address/data bit 1 output. takes priority over psp and port data. x i ttl external memory interface, data bit 1 input. psp1 x o dig psp read data output (latd<1>). takes priority over port data. x i ttl psp write data input. rd2/ad2/psp2 rd2 0 o dig latd<2> data output. 1 i st portd<2> data input. ad2 (1) x o dig external memory interface, address/data bit 2 output. takes priority over psp and port data. x i ttl external memory interface, data bit 2 input. psp2 x o dig psp read data output (latd<2>). takes priority over port data. x i ttl psp write data input. rd3/ad3/psp3 rd3 0 o dig latd<3> data output. 1 i st portd<3> data input. ad3 (1) x o dig external memory interface, address/data bit 3 output. takes priority over psp and port data. x i ttl external memory interface, data bit 3 input. psp3 x o dig psp read data output (latd<3>). takes priority over port data. x i ttl psp write data input. rd4/ad4/ psp4/sdo2 rd4 0 o dig latd<4> data output. 1 i st portd<4> data input. ad4 (1) x o dig external memory interface, address/data bit 4 output. takes priority over psp, mssp and port data. x i ttl external memory interface, data bit 4 input. psp4 x o dig psp read data output (latd<4>). takes priority over port and psp data. x i ttl psp write data input. sdo2 0 o dig spi? data output (mssp2 module). takes priority over psp and port data. legend: pwr = power supply, o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: implemented on 80-pin devices only.
? 2004 microchip technology inc. preliminary ds39646b-page 145 pic18f8722 family table 11-8: summary of registers associated with portd rd5/ad5/ psp5/sdi2 /sda2 rd5 0 o dig latd<5> data output. 1 i st portd<5> data input. ad5 (1) x o dig external memory interface, address/data bit 5 output. takes priority over psp, mssp and port data. x i ttl external memory interface, data bit 5 input. psp5 x o dig psp read data output (latd<5>). takes priority over port data. x i ttl psp write data input. sdi2 1 i st spi? data input (mssp2 module). sda2 1 odigi 2 c? data output (mssp2 module). takes priority over psp and port data. 1 ii 2 c/smb i 2 c data input (mssp2 module); input type depends on module setting. rd6/ad6/ psp6/sck2/ scl2 rd6 0 o dig latd<6> data output. 1 i st portd<6> data input. ad6 (1) x o dig-3 external memory interface, address/data bit 6 output. takes priority over psp, mssp and port data. x i ttl external memory interface, data bit 6 input. psp6 x o dig psp read data output (latd<6>). takes priority over port data. x i ttl psp write data input. sck2 0 o dig spi clock output (mssp2 module). takes priority over psp and port data. 1 i st spi clock input (mssp2 module). scl2 0 odigi 2 c clock output (mssp2 module). takes priority over psp and port data. 1 ii 2 c/smb i 2 c clock input (mssp2 module); input type depends on module setting. rd7/ad7/ psp7/ss2 rd7 0 o dig latd<7> data output. 1 i st portd<7> data input. ad7 (1) x o dig external memory interface, address/data bit 7 output. takes priority over psp and port data. x i ttl external memory interface, data bit 7 input. psp7 x o dig psp read data output (latd<7>). takes priority over port data. x i ttl psp write data input. ss 2 1 i ttl slave select input for ssp (mssp2 module). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 60 latd latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 60 trisd trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 60 table 11-7: portd functions (continued) pin name function tris setting i/o i/o type description legend: pwr = power supply, o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: implemented on 80-pin devices only.
pic18f8722 family ds39646b-page 146 preliminary ? 2004 microchip technology inc. 11.5 porte, trise and late registers porte is an 8-bit wide, bidirectional port. the corresponding data direction register is trise. setting a trise bit (= 1 ) will make the corresponding porte pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trise bit (= 0 ) will make the corresponding porte pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (late) is also memory mapped. read-modify-write operations on the late register read and write the latched output value for porte. all pins on porte are implemented with schmitt trigger input buffers. each pin is individually configurable as an input or output. when the device is operating in microcontroller mode, pin re7 can be configured as the alternate peripheral pin for the eccp2 module. this is done by clearing the ccp2mx configuration bit. in 80-pin devices, porte is multiplexed with the system bus as part of the external memory interface. i/o port and other functions are only available when the interface is disabled by setting the ebdis bit (memcon<7>). when the interface is enabled (80-pin devices only), porte is the high-order byte of the multiplexed address/data bus (ad15:ad8). the trise bits are also overridden. when the parallel slave port is active on portd, three of the porte pins (re0/ad8/rd /p2d, re1/ad9/wr /p2c and re2/ad10/cs /p2b) are config- ured as digital control inputs for the port. the control functions are summarized in table 11-9. the reconfigu- ration occurs automatically when the pspmode control bit (pspcon<4>) is set. users must still make certain the the corresponding trise bits are set to configure these pins as digital inputs. example 11-5: initializing porte note: on a power-on reset, these pins are configured as digital inputs. clrf porte ; initialize porte by ; clearing output ; data latches clrf late ; alternate method ; to clear output ; data latches movlw 03h ; value used to ; initialize data ; direction movwf trise ; set re<1:0> as inputs ; re<7:2> as outputs
? 2004 microchip technology inc. preliminary ds39646b-page 147 pic18f8722 family table 11-9: porte functions pin name function tris setting i/o i/o type description re0/ad8/ rd /p2d re0 0 o dig late<0> data output. 1 i st porte<0> data input. ad8 (2) x o dig external memory interface, address/data bit 8 output. takes priority over eccp and port data. x i ttl external memory interface, data bit 8 input. rd 1 i ttl parallel slave port read enable control input. p2d 0 o dig eccp2 enhanced pwm output, channel d. may be configured for tri-state during enhanced pwm shutdow n events. takes priority over port data. re1/ad9/ wr /p2c re1 0 o dig late<1> data output. 1 i st porte<1> data input. ad9 (2) x o dig external memory interface, address/data bit 9 output. takes priority over eccp and port data. x i ttl external memory interface, data bit 9 input. wr 1 i ttl parallel slave port write enable control input. p2c 0 o dig eccp2 enhanced pwm output, channel c. may be configured for tri-state during enhanced pwm shutdow n events. takes priority over port data. re2/ad10/ cs /p2b re2 0 o dig late<2> data output. 1 i st porte<2> data input. ad10 (2) x o dig external memory interface, address/data bit 10 output. takes priority over eccp and port data. x i ttl external memory interface, data bit 10 input. cs 1 i ttl parallel slave port chip select control input. p2b 0 o dig eccp2 enhanced pwm output, channel b. may be configured for tri-state during enhanced pwm shutdow n events. takes priority over port data. re3/ad11/p3c re3 0 o dig late<3> data output. 1 i st porte<3> data input. ad11 (2) x o dig external memory interface, address/data bit 11 output. takes priority over eccp and port data. x i ttl external memory interface, data bit 11 input. p3c 0 o dig eccp3 enhanced pwm output, channel c. may be configured for tri-state during enhanced pwm shutdow n events. takes priority over port data. re4/ad12/p3b re4 0 o dig late<4> data output. 1 i st porte<4> data input. ad12 (2) x o dig external memory interface, address/data bit 12 output. takes priority over eccp and port data. x i ttl external memory interface, data bit 12 input. p3b 0 o dig eccp3 enhanced pwm output, channel b. may be configured for tri-state during enhanced pwm shutdow n events. takes priority over port data. legend: pwr = power supply, o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: alternate assignment for eccp2 when ccp2mx configuration bit is cleared (all devices in microcontroller mode). 2: implemented on 80-pin devices only.
pic18f8722 family ds39646b-page 148 preliminary ? 2004 microchip technology inc. table 11-10: summary of registers associated with porte re5/ad13/p1c re5 0 o dig late<5> data output. 1 i st porte<5> data input. ad13 (2) x o dig external memory interface, address/data bit 13 output. takes priority over eccp and port data. x i ttl external memory interface, data bit 13 input. p1c 0 o dig eccp1 enhanced pwm output, channel c. may be configured for tri-state during enhanced pwm shutdow n events. takes priority over port data. re6/ad14/p1b re6 0 o dig late<6> data output. 1 i st porte<6> data input. ad14 (2) x o dig external memory interface, address/data bit 14 output. takes priority over eccp and port data. x i ttl external memory interface, data bit 14 input. p1b 0 o dig eccp1 enhanced pwm output, channel b. may be configured for tri-state during enhanced pwm shutdow n events. takes priority over port data. re7/ad15/ eccp2/p2a re7 0 o dig late<7> data output. 1 i st porte<7> data input. ad15 (2) x o dig external memory interface, address/data bit 15 output. takes priority over eccp and port data. x i ttl external memory interface, data bit 15 input. eccp2 (1) 0 o dig eccp2 compare output and eccp2 pw m output. takes priority over port data. 1 i st eccp2 capture input. p2a (1) 0 o dig eccp2 enhanced pwm output, channel a. takes priority over port and data. may be configured for tri-state during enhanced pwm shutdown events. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page porte re7 re6 re5 re4 re3 re2 re1 re0 60 late late7 late6 late5 late4 late3 late2 late1 late0 60 trise trise7 trise6 trise5 trise4 trise3 trise2 trise1 trise0 60 table 11-9: porte functions (continued) pin name function tris setting i/o i/o type description legend: pwr = power supply, o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: alternate assignment for eccp2 when ccp2mx configuration bit is cleared (all devices in microcontroller mode). 2: implemented on 80-pin devices only.
? 2004 microchip technology inc. preliminary ds39646b-page 149 pic18f8722 family 11.6 portf, latf and trisf registers portf is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisf. setting a trisf bit (= 1 ) will make the corresponding portf pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisf bit (= 0 ) will make the corresponding portf pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latf) is also memory mapped. read-modify-write operations on the latf register read and write the latched output value for portf. all pins on portf are implemented with schmitt trigger input buffers. each pin is individually configurable as an input or output. portf is multiplexed with several analog peripheral functions, including the a/d converter and comparator inputs, as well as the comparator outputs. pins rf1 through rf2 may be used as comparator inputs or outputs by setting the appropriate bits in the cmcon register. to use rf0:rf6 as digital inputs, it is necessary to turn off the a/d inputs. example 11-6: initializing portf note 1: on a power-on reset, the rf6:rf0 pins are configured as analog inputs and read as ? 0 ?. 2: to configure portf as digital i/o, set the adcon1 register. clrf portf ; initialize portf by ; clearing output ; data latches clrf latf ; alternate method ; to clear output ; data latches movlw 0x0f ; movwf adcon1 ; set portf as digital i/o movlw 0xcf ; value used to ; initialize data ; direction movwf trisf ; set rf3:rf0 as inputs ; rf5:rf4 as outputs ; rf7:rf6 as inputs
pic18f8722 family ds39646b-page 150 preliminary ? 2004 microchip technology inc. table 11-11: portf functions table 11-12: summary of registers associated with portf pin name function tris setting i/o i/o type description rf0/an5 rf0 0 o dig latf<0> data output; not affected by analog input. 1 i st portf<0> data input; disabled when analog input enabled. an5 1 i ana a/d input channel 5. default configuration on por. rf1/an6/c2out rf1 0 o dig latf<1> data output; not affected by analog input. 1 i st portf<1> data input; disabled when analog input enabled. an6 1 i ana a/d input channel 6. default configuration on por. c2out 0 o dig comparator 2 output; takes priority over port data. rf2/an7/c1out rf2 0 o dig latf<2> data output; not affected by analog input. 1 i st portf<2> data input; disabled when analog input enabled. an7 1 i ana a/d input channel 7. default configuration on por. c1out 0 o ttl comparator 1 output; takes priority over port data. rf3/an8 rf3 0 o dig latf<3> data output; not affected by analog input. 1 i st portf<3> data input; disabled when analog input enabled. an8 1 i ana a/d input channel 8 and comparator c2+ input. default input configuration on por; not affected by analog output. rf4/an9 rf4 0 o dig latf<4> data output; not affected by analog input. 1 i st portf<4> data input; disabled when analog input enabled. an9 1 i ana a/d input channel 9 and comparator c2- input. default input configuration on por; does not affect digital output. rf5/an10/cv ref rf5 0 o dig latf<5> data output; not affected by analog input. disabled when cv ref output enabled. 1 i st portf<5> data input; disabled when analog input enabled. disabled when cv ref output enabled. an10 1 i ana a/d input channel 10 and comparator c1+ input. default input configuration on por; not affected by analog output. cv ref x o ana comparator voltage reference output. enabling this feature disables digital i/o. rf6/an11 rf6 0 o dig latf<6> data output; not affected by analog input. 1 i st portf<6> data input; disabled when analog input enabled. an11 1 i ana a/d input channel 11 and comparator c1- input. default input configuration on por; does not affect digital output. rf7/ss 1 rf7 0 o dig latf<7> data output. 1 i st portf<7> data input. ss 1 1 i ttl slave select input for ssp (mssp1 module). legend: pwr = power supply, o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page trisf trisf7 trisf6 trisf5 trisf 4 trisf3 trisf2 trisf1 trisf0 60 portf rf7 rf6 rf5 rf4 rf3 rf2 rf1 rf0 60 latf latf7 latf6 latf5 latf4 latf3 latf2 latf1 latf0 60 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 59 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 59 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by portf.
? 2004 microchip technology inc. preliminary ds39646b-page 151 pic18f8722 family 11.7 portg, trisg and latg registers portg is a 6-bit wide, bidirectional port. the corre- sponding data direction register is trisg. setting a trisg bit (= 1 ) will make the corresponding portg pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisg bit (= 0 ) will make the corresponding portg pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latg) is also memory mapped. read-modify-write operations on the latg register, read and write the latched output value for portg. portg is multiplexed with eusart and ccp functions (table 11-13). portg pins have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in defining tris bits for each portg pin. some peripherals override the tris bit to make a pin an output, while other peripherals override the tris bit to make a pin an input. the user should refer to the corresponding peripheral section for the correct tris bit settings. the pin override value is not loaded into the tris register. this allows read-modify-write of the tris register without concern due to peripheral overrides. the sixth pin of portg (rg5/mclr /v pp ) is an input only pin. its operation is controlled by the mclre configuration bit. when selected as a port pin (mclre = 0 ), it functions as a digital input only pin; as such, it does not have tris or lat bits associated with its operation. otherwise, it functions as the device?s master clear input. in either configuration, rg5 also functions as the programming voltage input during programming. example 11-7: initializing portg note: on a power-on reset, rg5 is enabled as a digital input only if master clear functionality is disabled. all other 5 pins are configured as digital inputs. clrf portg ; initialize portg by ; clearing output ; data latches clrf latg ; alternate method ; to clear output ; data latches movlw 0x04 ; value used to ; initialize data ; direction movwf trisg ; set rg1:rg0 as outputs ; rg2 as input ; rg4:rg3 as inputs
pic18f8722 family ds39646b-page 152 preliminary ? 2004 microchip technology inc. table 11-13: portg functions pin name function tris setting i/o i/o type description rg0/eccp3/p3a rg0 0 o dig latg<0> data output. 1 i st portg<0> data input. eccp3 0 o dig eccp3 compare and eccp3 pwm output. takes priority over port data. 1 i st eccp3 capture input. p3a 0 o dig eccp3 enhanced pwm output, channel b. may be configured for tri-state during enhanced pwm shutdown events. takes priority over port data. rg1/tx2/ck2 rg1 0 o dig latg<1> data output. 1 i st portg<1> data input. tx2 0 o dig asynchronous serial transmit data output (eusart2 module). takes priority over port data. ck2 0 o dig synchronous serial clock output (eusart2 module). takes priority over port data. 1 i st synchronous serial clock input (eusart2 module). rg2/rx2/dt2 rg2 0 o dig latg<2> data output. 1 i st portg<2> data input. rx2 1 i st asynchronous serial receive data input (eusart2 module). dt2 1 o dig synchronous serial data output (eusart2 module). takes priority over port data. user must configure as an input. 1 i st synchronous serial data input (eusart2 module). user must configure as an input. rg3/ccp4/p3d rg3 0 o dig latg<3> data output. 1 i st portg<3> data input. ccp4 0 o dig ccp4 compare and pwm output; takes priority over port data and p3d function. 1 i st ccp4 capture input. p3d 0 o dig eccp3 enhanced pwm output, channel d. may be configured for tri-state during enhanced pwm shutdown events. takes priority over port data. rg4/ccp5/p1d rg4 0 o dig latg<4> data output. 1 i st portg<4> data input. ccp5 0 o dig ccp5 compare and pwm output. takes priority over port data and p1d function. 1 i st ccp5 capture input. p1d 0 o dig eccp1 enhanced pwm output, channel b. may be configured for tri-state during enhanced pwm shutdown events. takes priority over port data. rg5/mclr /v pp rg5 ? (1) i st portg<5> data input; enabled when mclre configuration bit is clear. mclr ? i st external master clear input; enabled when mclre configuration bit is set. v pp ? i ana high-voltage detection; used for icsp? mode entry detection. always available regardless of pin mode. legend: pwr = power supply, o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: rg5 does not have a corresponding trisg bit.
? 2004 microchip technology inc. preliminary ds39646b-page 153 pic18f8722 family table 11-14: summary of registers associated with portg name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portg ? ?rg5 (1) rg4 rg3 rg2 rg1 rg0 60 latg ? ?latg5 (1) latg4 latg3 latg2 latg1 latg0 60 trisg ? ? ? trisg4 trisg3 trisg2 trisg1 trisg0 60 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by portg. note 1: rg5 and latg5 are only available when mclr is disabled (mclre configuration bit = 0 ; otherwise, rg5 and latg5 read as ? 0 ?.
pic18f8722 family ds39646b-page 154 preliminary ? 2004 microchip technology inc. 11.8 porth, lath and trish registers porth is an 8-bit wide, bidirectional i/o port. the corresponding data direction register is trish. setting a trish bit (= 1 ) will make the corresponding porth pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trish bit (= 0 ) will make the corresponding porth pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (lath) is also memory mapped. read-modify-write operations on the lath register, read and write the latched output value for porth. all pins on porth are implemented with schmitt trigger input buffers. each pin is individually configurable as an input or output. when the external memory interface is enabled, four of the porth pins function as the high-order address lines for the interface. the address output from the interface takes priority over other digital i/o. the corresponding trish bits are also overridden. example 11-8: initializing porth note: porth is available only on pic18f8527/8622/8627/8722 devices. note: on a power-on reset, these pins are configured as digital inputs. clrf porth ; initialize porth by ; clearing output ; data latches clrf lath ; alternate method ; to clear output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trish ; set rh3:rh0 as inputs ; rh5:rh4 as outputs ; rh7:rh6 as inputs
? 2004 microchip technology inc. preliminary ds39646b-page 155 pic18f8722 family table 11-15: porth functions table 11-16: summary of registers associated with porth pin name function tris setting i/o i/o type description rh0/a16 rh0 0 o dig lath<0> data output. 1 i st porth<0> data input. a16 x o dig external memory interface, address line 16. takes priority over port data. rh1/a17 rh1 0 o dig lath<1> data output. 1 i st porth<1> data input. a17 x o dig external memory interface, address line 17. takes priority over port data. rh2/a18 rh2 0 o dig lath<2> data output. 1 i st porth<2> data input. a18 x o dig external memory interface, address line 18. takes priority over port data. rh3/a19 rh3 0 o dig lath<3> data output. 1 i st porth<3> data input. a19 x o dig external memory interface, address line 19. takes priority over port data. rh4/an12/ p3c rh4 0 o dig lath<4> data output. 1 i st porth<4> data input. an12 1 i ana a/d input channel 12. default configuration on por. p3c (1) 0 o dig eccp3 enhanced pwm output, channel c. may be configured for tri-state during enhanced pwm shutdown events. takes priority over port data. rh5/an13/ p3b rh5 0 o dig lath<5> data output. 1 i st porth<5> data input. an13 1 i ana a/d input channel 13. default configuration on por. p3b (1) 0 o dig eccp3 enhanced pwm output, channel b. may be configured for tri-state during enhanced pwm shutdown events. takes priority over port data. rh6/an14/ p1c rh6 0 o dig lath<6> data output. 1 i st porth<6> data input. an14 1 i ana a/d input channel 14. default configuration on por. p1c (1) 0 o dig eccp1 enhanced pwm output, channel c. may be configured for tri-state during enhanced pwm shutdown events. takes priority over port data. rh7/an15/ p1b rh7 0 o dig lath<7> data output. 1 i st porth<7> data input. an15 1 i ana a/d input channel 15. default configuration on por. p1b (1) 0 o dig eccp1 enhanced pwm output, channel b. may be configured for tri-state during enhanced pwm shutdown events. takes priority over port data. legend: pwr = power supply, o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: alternate assignment for p1b/p1c/p3b/p3c (eccpmx is clear). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page trish trish7 trish6 trish5 trish4 trish3 trish2 trish1 trish0 60 porth rh7 rh6 rh5 rh4 rh3 rh2 rh1 rh0 60 lath lath7 lath6 lath5 lath4 lath3 lath2 lath1 lath0 60 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 59
pic18f8722 family ds39646b-page 156 preliminary ? 2004 microchip technology inc. 11.9 portj, trisj and latj registers portj is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisj. setting a trisj bit (= 1 ) will make the corresponding portj pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisj bit (= 0 ) will make the corresponding portj pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latj) is also memory mapped. read-modify-write operations on the latj register, read and write the latched output value for portj. all pins on portj are implemented with schmitt trigger input buffers. each pin is individually configurable as an input or output. when the external memory interface is enabled, all of the portj pins function as control outputs for the interface. this occurs automatically when the interface is enabled by clearing the ebdis control bit (memcon<7>). the trisj bits are also overridden. example 11-9: initializing portj note: portj is available only on pic18f8527/8622/8627/8722 devices. note: on a power-on reset, these pins are configured as digital inputs. clrf portj ; initialize portj by ; clearing output ; data latches clrf latj ; alternate method ; to clear output ; data latches movlw 0xcf ; value used to ; initialize data ; direction movwf trisj ; set rj3:rj0 as inputs ; rj5:rj4 as output ; rj7:rj6 as inputs
? 2004 microchip technology inc. preliminary ds39646b-page 157 pic18f8722 family table 11-17: portj functions table 11-18: summary of registers associated with portj pin name function tris setting i/o i/o type description rj0/ale rj0 0 o dig latj<0> data output. 1 i st portj<0> data input. ale x o dig external memory interface address latch enable control output. takes priority over digital i/o. rj1/oe rj1 0 o dig latj<1> data output. 1 i st portj<1> data input. oe x o dig external memory interface output enable control output. takes priority over digital i/o. rj2/wrl rj2 0 o dig latj<2> data output. 1 i st portj<2> data input. wrl x o dig external memory bus write low by te control. takes priority over digital i/o. rj3/wrh rj3 0 o dig latj<3> data output. 1 i st portj<3> data input. wrh x o dig external memory interface write high byte control output. takes priority over digital i/o. rj4/ba0 rj4 0 o dig latj<4> data output. 1 i st portj<4> data input. ba0 x o dig external memory interface byte address 0 control output. takes priority over digital i/o. rj5/ce rj5 0 o dig latj<5> data output. 1 i st portj<5> data input. ce x o dig external memory interface chip enable control output. takes priority over digital i/o. rj6/lb rj6 0 o dig latj<6> data output. 1 i st portj<6> data input. lb x o dig external memory interface lower byte enable control output. takes priority over digital i/o. rj7/ub rj7 0 o dig latj<7> data output. 1 i st portj<7> data input. ub x o dig external memory interface upper byte enable control output. takes priority over digital i/o. legend: pwr = power supply, o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portj rj7 rj6 rj5 rj4 rj3 rj2 rj1 rj0 60 latj latj7 latj6 latj5 latj4 latj3 latj2 latj1 latj0 60 trisj trisj7 trisj6 trisj5 trisj4 trisj3 trisj2 trisj1 trisj0 60
pic18f8722 family ds39646b-page 158 preliminary ? 2004 microchip technology inc. 11.10 parallel slave port portd can also function as an 8-bit wide parallel slave port, or microprocessor port, when control bit pspmode (pspcon<4>) is set. it is asynchronously readable and writable by the external world through the rd and wr control input pins. the psp can directly interface to an 8-bit micro- processor data bus. the external microprocessor can read or write the portd latch as an 8-bit latch. setting bit pspmode enables port pin re0/rd to be the rd input, re1/wr to be the wr input and re2/cs to be the cs (chip select) input. for this functionality, the corresponding data direction bits of the trise register (trise<2:0>) must be configured as inputs (set). a write to the psp occurs when both the cs and wr lines are first detected low and ends when either are detected high. the pspif and ibf flag bits are both set when the write ends. a read from the psp occurs when both the cs and rd lines are first detected low. the data in portd is read out and the obf bit is set. if the user writes new data to portd to set obf, the data is immediately read out; however, the obf bit is not set. when either the cs or rd lines are detected high, the portd pins return to the input state and the pspif bit is set. user applications should wait for pspif to be set before servicing the psp; when this happens, the ibf and obf bits can be polled and the appropriate action taken. the timing for the control signals in write and read modes is shown in figure 11-3 and figure 11-4, respectively. figure 11-2: portd and porte block diagram (parallel slave port) note: for pic18f8527/8622/8627/8722 devices, the parallel slave port is available only in microcontroller mode. data bus wr latd rdx q d ckx en qd en rd portd pin one bit of portd set interrupt flag pspif (pir1<7>) read chip select write rd cs wr note: i/o pin has protection diodes to v dd and v ss . ttl ttl ttl ttl or portd rd latd data latch tris latch
? 2004 microchip technology inc. preliminary ds39646b-page 159 pic18f8722 family register 11-1: pspcon: parallel slave port control register r-0 r-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ibf obf ibov pspmode ? ? ? ? bit 7 bit 0 bit 7 ibf: input buffer full status bit 1 = a word has been received and is waiting to be read by the cpu 0 = no word has been received bit 6 obf: output buffer full status bit 1 = the output buffer still holds a previously written word 0 = the output buffer has been read bit 5 ibov: input buffer overflow detect bit 1 = a write occurred when a previously input word has not been read (must be cleared in software) 0 = no overflow occurred bit 4 pspmode: parallel slave port mode select bit 1 = parallel slave port mode 0 = general purpose i/o mode bit 3-0 unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 160 preliminary ? 2004 microchip technology inc. figure 11-3: parallel slave port write waveforms figure 11-4: parallel slave port read waveforms table 11-19: registers associated with parallel slave port q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr rd ibf obf pspif portd<7:0> q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr ibf pspif rd obf portd<7:0> name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 60 latd latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 60 trisd trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 60 porte re7 re6 re5 re4 re3 re2 re1 re0 60 late late7 late6 late5 late4 late3 late2 late1 late0 60 trise trise7 trise6 trise5 trise4 trise3 trise2 trise1 trise0 60 pspcon ibf obf ibov pspmode ? ? ? ?59 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 60 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 60 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 60 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the parallel slave port.
? 2004 microchip technology inc. preliminary ds39646b-page 161 pic18f8722 family 12.0 timer0 module the timer0 module incorporates the following features: software selectable operation as a timer or counter in both 8-bit or 16-bit modes readable and writable registers dedicated 8-bit, software programmable prescaler selectable clock source (internal or external) edge select for external clock interrupt-on-overflow the t0con register (register 12-1) controls all aspects of the module?s operation, including the prescale selection. it is both readable and writable. a simplified block diagram of the timer0 module in 8-bit mode is shown in figure 12-1. figure 12-2 shows a simplified block diagram of the timer0 module in 16-bit mode. register 12-1: t0con: timer0 control register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 bit 7 bit 0 bit 7 tmr0on: timer0 on/off control bit 1 = enables timer0 0 = stops timer0 bit 6 t08bit : timer0 8-bit/16-bit control bit 1 = timer0 is configured as an 8-bit timer/counter 0 = timer0 is configured as a 16-bit timer/counter bit 5 t0cs : timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clko) bit 4 t0se : timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa : timer0 prescaler assignment bit 1 = timer0 prescaler is not assigned. timer0 clock input bypasses prescaler. 0 = timer0 prescaler is assigned. timer0 clock input comes from prescaler output. bit 2-0 t0ps2:t0ps0 : timer0 prescaler select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 162 preliminary ? 2004 microchip technology inc. 12.1 timer0 operation timer0 can operate as either a timer or a counter; the mode is selected with the t0cs bit (t0con<5>). in timer mode (t0cs = 0 ), the module increments on every clock by default unless a different prescaler value is selected (see section 12.3 ?prescaler? ). if the tmr0 register is written to, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. the counter mode is selected by setting the t0cs bit (= 1 ). in this mode, timer0 increments either on every rising or falling edge of pin ra4/t0cki. the increment- ing edge is determined by the timer0 source edge select bit, t0se (t0con<4>); clearing this bit selects the rising edge. restrictions on the external clock input are discussed below. an external clock source can be used to drive timer0; however, it must meet certain requirements to ensure that the external clock can be synchronized with the internal phase clock (t osc ). there is a delay between synchronization and the onset of incrementing the timer/counter. 12.2 timer0 reads and writes in 16-bit mode tmr0h is not the actual high byte of timer0 in 16-bit mode; it is actually a buffered version of the real high byte of timer0 which is not directly readable nor writ- able (refer to figure 12-2). tmr0h is updated with the contents of the high byte of timer0 during a read of tmr0l. this provides the ability to read all 16 bits of timer0 without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. similarly, a write to the high byte of timer0 must also take place through the tmr0h buffer register. the high byte is updated with the contents of tmr0h when a write occurs to tmr0l. this allows all 16 bits of timer0 to be updated at once. figure 12-1: timer0 block diagram (8-bit mode) figure 12-2: timer0 block diagram (16-bit mode) note: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki max. prescale. t0cki pin t0se 0 1 1 0 t0cs f osc /4 programmable prescaler sync with internal clocks tmr0l (2 t cy delay) internal data bus psa t0ps2:t0ps0 set tmr0if on overflow 3 8 8 note: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki max. prescale. t0cki pin t0se 0 1 1 0 t0cs f osc /4 programmable prescaler sync with internal clocks tmr0l (2 t cy delay) internal data bus 8 psa t0ps2:t0ps0 set tmr0if on overflow 3 tmr0 tmr0h high byte 8 8 8 read tmr0l write tmr0l 8
? 2004 microchip technology inc. preliminary ds39646b-page 163 pic18f8722 family 12.3 prescaler an 8-bit counter is available as a prescaler for the timer0 module. the prescaler is not directly readable or writable; its value is set by the psa and t0ps2:t0ps0 bits (t0con<3:0>) which determine the prescaler assignment and prescale ratio. clearing the psa bit assigns the prescaler to the timer0 module. when it is assigned, prescale values from 1:2 through 1:256 in power-of-2 increments are selectable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf tmr0 , movwf tmr0 , bsf tmr0 , etc.) clear the prescaler count. 12.3.1 switching prescaler assignment the prescaler assignment is fully under software control and can be changed ?on-the-fly? during program execution. 12.4 timer0 interrupt the tmr0 interrupt is generated when the tmr0 register overflows from ffh to 00h in 8-bit mode, or from ffffh to 0000h in 16-bit mode. this overflow sets the tmr0if flag bit. the interrupt can be masked by clearing the tmr0ie bit (intcon<5>). before re- enabling the interrupt, the tmr0if bit must be cleared in software by the interrupt service routine. since timer0 is shut down in sleep mode, the tmr0 interrupt cannot awaken the processor from sleep. table 12-1: registers associated with timer0 note: writing to tmr0 when the prescaler is assigned to timer0 will clear the prescaler count, but will not change the prescaler assignment. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page tmr0l timer0 register low byte 58 tmr0h timer0 register high byte 58 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 t0con tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 58 trisa trisa7 (1) trisa6 (1) trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 60 legend: shaded cells are not used by timer0. note 1: porta<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. when disabled, these bits read as ? 0 ?.
pic18f8722 family ds39646b-page 164 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39646b-page 165 pic18f8722 family 13.0 timer1 module the timer1 timer/counter module incorporates these features: software selectable operation as a 16-bit timer or counter readable and writable 8-bit registers (tmr1h and tmr1l) selectable clock source (internal or external) with device clock or timer1 oscillator internal options interrupt-on-overflow reset on ccp special event trigger device clock status flag (t1run) a simplified block diagram of the timer1 module is shown in figure 13-1. a block diagram of the module?s operation in read/write mode is shown in figure 13-2. the module incorporates its own low-power oscillator to provide an additional clocking option. the timer1 oscillator can also be used as a low-power clock source for the microcontroller in power-managed operation. timer1 can also be used to provide real-time clock (rtc) functionality to applications with only a minimal addition of external components and code overhead. timer1 is controlled through the t1con control register (register 13-1). it also contains the timer1 oscillator enable bit (t1oscen). timer1 can be enabled or disabled by setting or clearing control bit, tmr1on (t1con<0>). register 13-1: t1con: timer1 control register r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 bit 7 rd16: 16-bit read/write mode enable bit 1 = enables register read/write of timer1 in one 16-bit operation 0 = enables register read/write of timer1 in two 8-bit operations bit 6 t1run: timer1 system clock status bit 1 = device clock is derived from timer1 oscillator 0 = device clock is derived from another source bit 5-4 t1ckps1:t1ckps0: timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: timer1 oscillator enable bit 1 = timer1 oscillator is enabled 0 = timer1 oscillator is shut off the oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 t1sync : timer1 external clock input synchronization select bit when tmr1cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr1cs = 0 : this bit is ignored. timer1 uses the internal clock when tmr1cs = 0 . bit 1 tmr1cs: timer1 clock source select bit 1 = external clock from pin rc0/t1oso/t13cki (on the rising edge) 0 = internal clock (f osc /4) bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 = stops timer1 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 166 preliminary ? 2004 microchip technology inc. 13.1 timer1 operation timer1 can operate in one of these modes: timer synchronous counter asynchronous counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). when tmr1cs is cleared (= 0 ), timer1 increments on every internal instruction cycle (fosc/4). when the bit is set, timer1 increments on every rising edge of the timer1 external clock input or the timer1 oscillator, if enabled. when timer1 is enabled, the rc1/t1osi and rc0/ t1oso/t13cki pins become inputs. this means the values of trisc<1:0> are ignored and the pins are read as ? 0 ?. figure 13-1: timer1 block diagram figure 13-2: timer1 block diagram (16-bit read/write mode) t1sync tmr1cs t1ckps1:t1ckps0 sleep input t1oscen (1) f osc /4 internal clock on/off prescaler 1, 2, 4, 8 synchronize detect 1 0 2 t1oso/t13cki t1osi 1 0 tmr1on tmr1l set tmr1if on overflow tmr1 high byte clear tmr1 (ccp special event trigger) timer1 oscillator note 1: when enable bit, t1oscen, is cleared, the inverter and f eedback resistor are turned off to eliminate power drain. on/off timer1 timer1 clock input t1sync tmr1cs t1ckps1:t1ckps0 sleep input t1oscen (1) f osc /4 internal clock prescaler 1, 2, 4, 8 synchronize detect 1 0 2 t1oso/t13cki t1osi note 1: when enable bit, t1oscen, is cleared, the inverter and f eedback resistor are turned off to eliminate power drain. 1 0 tmr1l internal data bus 8 set tmr1if on overflow tmr1 tmr1h high byte 8 8 8 read tmr1l write tmr1l 8 tmr1on clear tmr1 (ccp special event trigger) timer1 oscillator on/off timer1 timer1 clock input
? 2004 microchip technology inc. preliminary ds39646b-page 167 pic18f8722 family 13.2 timer1 16-bit read/write mode timer1 can be configured for 16-bit reads and writes (see figure 13-2). when the rd16 control bit (t1con<7>) is set, the address for tmr1h is mapped to a buffer register for the high byte of timer1. a read from tmr1l will load the contents of the high byte of timer1 into the timer1 high byte buffer. this provides the user with the ability to accurately read all 16 bits of timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. a write to the high byte of timer1 must also take place through the tmr1h buffer register. the timer1 high byte is updated with the contents of tmr1h when a write occurs to tmr1l. this allows a user to write all 16 bits to both the high and low bytes of timer1 at once. the high byte of timer1 is not directly readable or writable in this mode. all reads and writes must take place through the timer1 high byte buffer register. writes to tmr1h do not clear the timer1 prescaler. the prescaler is only cleared on writes to tmr1l. 13.3 timer1 oscillator an on-chip crystal oscillator circuit is incorporated between pins t1osi (input) and t1oso (amplifier out- put). it is enabled by setting the timer1 oscillator enable bit, t1oscen (t1con<3>). the oscillator is a low- power circuit rated for 32 khz crystals. it will continue to run during all power-managed modes. the circuit for a typical lp oscillator is s hown in figure 13-3. table 13-1 shows the capacitor selection for the timer1 oscillator. the user must provide a software time delay to ensure proper start-up of the timer1 oscillator. figure 13-3: external components for the timer1 lp oscillator table 13-1: capacitor selection for the timer oscillator (2,3,4) 13.3.1 using timer1 as a clock source the timer1 oscillator is also available as a clock source in power-managed modes. by setting the clock select bits, scs1:scs0 (osccon<1:0>), to ? 01 ?, the device switches to sec_run mode; both the cpu and peripherals are clocked from the timer1 oscillator. if the idlen bit (osccon<7>) is cleared and a sleep instruction is executed, the device enters sec_idle mode. additional details are available in section 3.0 ?power-managed modes? . whenever the timer1 oscillator is providing the clock source, the timer1 system clock status flag, t1run (t1con<6>), is set. this can be used to determine the controller?s current clocking mode. it can also indicate the clock source being currently used by the fail-safe clock monitor. if the clock monitor is enabled and the timer1 oscillator fails while providing the clock, polling the t1run bit will indicate whether the clock is being provided by the timer1 oscillator or another source. 13.3.2 low-power timer1 option the timer1 oscillator can operate at two distinct levels of power consumption based on device configuration. when the lpt1osc configuration bit is set, the timer1 oscillator operates in a low-power mode. when lpt1osc is not set, timer1 operates at a higher power level. power consumption for a particular mode is rela- tively constant, regardless of the device?s operating mode. the default timer1 configuration is the higher power mode. as the low-power timer1 mode tends to be more sensitive to interference, high noise environments may cause some oscillator instability. the low-power option is, therefore, best suited for low noise applications where power conservation is an important design consideration. note: see the notes with table 13-1 for additiona l information about capacitor selection. c1 c2 xtal pic18fxxxx t1osi t1oso 32.768 khz 27 pf 27 pf osc type freq c1 c2 lp 32 khz 27 pf (1) 27 pf (1) note 1: microchip suggests these values as a starting point in validating the oscillator circuit. 2: higher capacitance increases the stability of the oscillator but also increases the start-up time. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: capacitor values are for design guidance only.
pic18f8722 family ds39646b-page 168 preliminary ? 2004 microchip technology inc. 13.3.3 timer1 oscillator layout considerations the timer1 oscillator circuit draws very little power during operation. due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. the oscillator circuit, shown in figure 13-3, should be located as close as possible to the microcontroller. there should be no circuits passing within the oscillator circuit boundaries other than v ss or v dd . if a high-speed circuit must be located near the timer1 oscillator, a grounded guard ring around the oscillator circuit may be helpful when used on a single-sided pcb or in addition to a ground plane. 13.4 timer1 interrupt the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the timer1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, tmr1if (pir1<0>). this interrupt can be enabled or disabled by setting or clearing the timer1 interrupt enable bit, tmr1ie (pie1<0>). 13.5 resetting timer1 using the ccp special event trigger if any of the ccp modules are configured to use timer1 and generate a special event trigger in compare mode (ccpxm3:ccpxm0, this signal will reset timer1. the trigger from the eccp2 module will also start an a/d conversion if the a/d module is enabled (see section 17.3.4 ?special event trigger? for more information). the module must be configured as either a timer or a synchronous counter to take advantage of this feature. when used this way, the ccprh:ccprl register pair effectively becomes a period register for timer1. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a special event trigger, the write operation will take precedence. 13.6 using timer1 as a real-time clock adding an external lp oscillator to timer1 (such as the one described in section 13.3 ?timer1 oscillator? above) gives users the option to include rtc function- ality to their applications. this is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time. when operating in sleep mode and using a battery or supercapacitor as a power source, it can completely eliminate the need for a separate rtc device and battery backup. the application code routine, rtcisr , shown in example 13-1, demonstrates a simple method to increment a counter at one-second intervals using an interrupt service routine. incrementing the tmr1 register pair to overflow triggers the interrupt and calls the routine, which increments the seconds counter by one; additional counters for minutes and hours are incremented as the previous counter overflow. since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768 khz clock would take 2 seconds. to force the overflow at the required one-second intervals, it is necessary to pre- load it; the simplest method is to set the msb of tmr1h with a bsf instruction. note that the tmr1l register is never preloaded or altered; doing so may introduce cumulative error over many cycles. for this method to be accurate, timer1 must operate in asynchronous mode and the timer1 overflow interrupt must be enabled (pie1<0> = 1 ), as shown in the routine, rtcinit . the timer1 oscillator must also be enabled and running at all times. note: the special event triggers from the ccpx module will not set the tmr1if interrupt flag bit (pir1<0>).
? 2004 microchip technology inc. preliminary ds39646b-page 169 pic18f8722 family example 13-1: implementing a real-time clock using a timer1 interrupt service table 13-2: registers associated with timer1 as a timer/counter rtcinit movlw 80h ; preload tmr1 register pair movwf tmr1h ; for 1 second overflow clrf tmr1l movlw b?00001111? ; configure for external clock, movwf t1con ; asynchronous operation, external oscillator clrf secs ; initialize timekeeping registers clrf mins ; movlw .12 movwf hours bsf pie1, tmr1ie ; enable timer1 interrupt return rtcisr bsf tmr1h, 7 ; preload for 1 sec overflow bcf pir1, tmr1if ; clear interrupt flag incf secs, f ; increment seconds movlw .59 ; 60 seconds elapsed? cpfsgt secs return ; no, done clrf secs ; clear seconds incf mins, f ; increment minutes movlw .59 ; 60 minutes elapsed? cpfsgt mins return ; no, done clrf mins ; clear minutes incf hours, f ; increment hours movlw .23 ; 24 hours elapsed? cpfsgt hours return ; no, done clrf hours ; reset hours return ; done name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 60 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 60 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 60 tmr1l timer1 register low byte 58 tmr1h timer1 register high byte 58 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 58 legend: shaded cells are not used by the timer1 module.
pic18f8722 family ds39646b-page 170 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39646b-page 171 pic18f8722 family 14.0 timer2 module the timer2 timer module incorporates the following features: 8-bit timer and period registers (tmr2 and pr2, respectively) readable and writable (both registers) software programmable prescaler (1:1, 1:4 and 1:16) software programmable postscaler (1:1 through 1:16) interrupt on tmr2-to-pr2 match optional use as the shift clock for the msspx module the module is controlled through the t2con register (register 14-1), which enables or disables the timer and configures the prescaler and postscaler. timer2 can be shut off by clearing control bit, tmr2on (t2con<2>), to minimize power consumption. a simplified block diagram of the module is shown in figure 14-1. 14.1 timer2 operation in normal operation, tmr2 is incremented from 00h on each clock (f osc /4). a 4-bit counter/prescaler on the clock input gives direct input, divide-by-4 and divide-by- 16 prescale options; these are selected by the prescaler control bits, t2ckps1:t2ckps0 (t2con<1:0>). the value of tmr2 is compared to that of the period register, pr2, on each clock cycle. when the two values match, the comparator generates a match signal as the timer output. this signal also resets the value of tmr2 to 00h on the next cycle and drives the output counter/ postscaler (see section 14.2 ?timer2 interrupt? ). the tmr2 and pr2 registers are both directly readable and writable. the tmr2 register is cleared on any device reset, while the pr2 register initializes at ffh. both the prescaler and postscaler counters are cleared on the following events: a write to the tmr2 register a write to the t2con register any device reset (power-on reset, mclr reset, watchdog timer reset or brown-out reset) tmr2 is not cleared when t2con is written. register 14-1: t2con: time r2 control register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? t2outps3 t2outps2 t2outps1 t2outps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6-3 t2outps3:t2outps0 : timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 1111 = 1:16 postscale bit 2 tmr2on : timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps1:t2ckps0 : timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 172 preliminary ? 2004 microchip technology inc. 14.2 timer2 interrupt timer2 also can generate an optional device interrupt. the timer2 output signal (tmr2-to-pr2 match) pro- vides the input for the 4-bit output counter/postscaler. this counter generates the tmr2 match interrupt flag which is latched in tmr2if (pir1<1>). the interrupt is enabled by setting the tmr2 match interrupt enable bit, tmr2ie (pie1<1>). a range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, t2outps3:t2outps0 (t2con<6:3>). 14.3 timer2 output the unscaled output of tmr2 is available primarily to the ccp modules, where it is used as a time base for operations in pwm mode. timer2 can be optionally used as the shift clock source for the mssp module operating in spi mode. addi- tional information is provided in section 19.0 ?master synchronous serial port (mssp) module? . figure 14-1: timer2 block diagram table 14-1: registers associated with timer2 as a timer/counter name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 60 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 60 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 60 tmr2 timer2 register 58 t2con ? t2outps3 t2outps2 t2outps1 t2o utps0 tmr2on t2ckps1 t2ckps0 58 pr2 timer2 period register 58 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer2 module. comparator tmr2 output tmr2 postscaler prescaler pr2 2 f osc /4 1:1 to 1:16 1:1, 1:4, 1:16 4 t2outps3:t2outps0 t2ckps1:t2ckps0 set tmr2if internal data bus 8 reset tmr2/pr2 8 8 (to pwm or mssp) match
? 2004 microchip technology inc. preliminary ds39646b-page 173 pic18f8722 family 15.0 timer3 module the timer3 timer/counter module incorporates these features: software selectable operation as a 16-bit timer or counter readable and writable 8-bit registers (tmr3h and tmr3l) selectable clock source (internal or external) with device clock or timer1 oscillator internal options interrupt-on-overflow module reset on ccp special event trigger a simplified block diagram of the timer3 module is shown in figure 15-1. a block diagram of the module?s operation in read/write mode is shown in figure 15-2. the timer3 module is controlled through the t3con register (register 15-1). it also selects the clock source options for the ccp modules (see section 17.1.1 ?ccp modules and timer resources? for more information). register 15-1: t3con: time r3 control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on bit 7 bit 0 bit 7 rd16: 16-bit read/write mode enable bit 1 = enables register read/write of timer3 in one 16-bit operation 0 = enables register read/write of timer3 in two 8-bit operations bit 6,3 t3ccp2:t3ccp1: timer3 and timer1 to ccpx enable bits 11 = timer3 and timer4 are the clock sources for eccp1, eccp2, eccp3, ccp4 and ccp5 10 = timer3 and timer4 are the clock sources for eccp3, ccp4 and ccp5; timer1 and timer2 are the clock sources for eccp1 and eccp2 01 = timer3 and timer4 are the clock sources for eccp2, eccp3, ccp4 and ccp5; timer1 and timer2 are the clock sources for eccp1 00 = timer1 and timer2 are the clock sources for eccp1, eccp2, eccp3, ccp4 and ccp5 bit 5-4 t3ckps1:t3ckps0 : timer3 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 2 t3sync : timer3 external clock input synchronization control bit (not usable if the device clock comes from timer1/timer3.) when tmr3cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr3cs = 0 : this bit is ignored. timer3 uses the internal clock when tmr3cs = 0 . bit 1 tmr3cs: timer3 clock source select bit 1 = external clock input from timer1 oscillator or t13cki (on the rising edge after the first falling edge) 0 = internal clock (f osc /4) bit 0 tmr3on: timer3 on bit 1 = enables timer3 0 = stops timer3 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 174 preliminary ? 2004 microchip technology inc. 15.1 timer3 operation timer3 can operate in one of three modes: timer synchronous counter asynchronous counter the operating mode is determined by the clock select bit, tmr3cs (t3con<1>). when tmr3cs is cleared (= 0 ), timer3 increments on every internal instruction cycle (f osc /4). when the bit is set, timer3 increments on every rising edge of the timer1 external clock input or the timer1 oscillator, if enabled. as with timer1, the rc1/t1osi and rc0/t1oso/ t13cki pins become inputs when the timer1 oscillator is enabled. this means the values of trisc<1:0> are ignored and the pins are read as ? 0 ?. figure 15-1: timer3 block diagram figure 15-2: timer3 block diagram (16-bit read/write mode) t3sync tmr3cs t3ckps1:t3ckps0 sleep input t1oscen (1) f osc /4 internal clock prescaler 1, 2, 4, 8 synchronize detect 1 0 2 t1oso/t13cki t1osi 1 0 tmr3on tmr3l set tmr3if on overflow tmr3 high byte timer1 oscillator note 1: when enable bit, t1oscen, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. on/off timer3 ccpx special event trigger ccpx select from t3con<6,3> clear tmr3 timer1 clock input t3sync tmr3cs t3ckps1:t3ckps0 sleep input t1oscen (1) f osc /4 internal clock prescaler 1, 2, 4, 8 synchronize detect 1 0 2 t13cki/t1oso t1osi note 1: when enable bit, t1oscen, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. 1 0 tmr3l internal data bus 8 set tmr3if on overflow tmr3 tmr3h high byte 8 8 8 read tmr1l write tmr1l 8 tmr3on ccpx special event trigger timer1 oscillator on/off timer3 timer1 clock input ccpx select from t3con<6,3> clear tmr3
? 2004 microchip technology inc. preliminary ds39646b-page 175 pic18f8722 family 15.2 timer3 16-bit read/write mode timer3 can be configured for 16-bit reads and writes (see figure 15-2). when the rd16 control bit (t3con<7>) is set, the address for tmr3h is mapped to a buffer register for the high byte of timer3. a read from tmr3l will load the contents of the high byte of timer3 into the timer3 high byte buffer register. this provides the user with the ability to accurately read all 16 bits of timer3 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. a write to the high byte of timer3 must also take place through the tmr3h buffer register. the timer3 high byte is updated with the contents of tmr3h when a write occurs to tmr3l. this allows a user to write all 16 bits to both the high and low bytes of timer3 at once. the high byte of timer3 is not directly readable or writable in this mode. all reads and writes must take place through the timer3 high byte buffer register. writes to tmr3h do not clear the timer3 prescaler. the prescaler is only cleared on writes to tmr3l. 15.3 using the timer1 oscillator as the timer3 clock source the timer1 internal oscillator may be used as the clock source for timer3. the timer1 oscillator is enabled by setting the t1oscen (t1con<3>) bit. to use it as the timer3 clock source, the tmr3cs bit must also be set. as previously noted, this also configures timer3 to increment on every rising edge of the oscillator source. the timer1 oscillator is described in section 13.0 ?timer1 module? . 15.4 timer3 interrupt the tmr3 register pair (tmr3h:tmr3l) increments from 0000h to ffffh and overflows to 0000h. the timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, tmr3if (pir2<1>). this interrupt can be enabled or disabled by setting or clearing the timer3 interrupt enable bit, tmr3ie (pie2<1>). 15.5 resetting timer3 using the ccp special event trigger if any of the ccp modules are configured to use timer3 and to generate a special event trigger in compare mode (ccpxm3:ccpxm0 = 1011 ), this signal will reset timer3. eccp2 can also start an a/d conversion if the a/d module is enabled (see section 17.3.4 ?special event trigger? for more information). the module must be configured as either a timer or synchronous counter to take advantage of this feature. when used this way, the ccprxh:ccprxl register pair effectively becomes a period register for timer3. if timer3 is running in asynchronous counter mode, the reset operation may not work. in the event that a write to timer3 coincides with a special event trigger from a ccp module, the write will take precedence. table 15-1: registers associated with timer3 as a timer/counter note: the special event triggers from the ccpx module will not set the tmr3if interrupt flag bit (pir2<1>). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir2 oscfif cmif ? eeif bcl1if hlvdif tmr3if ccp2if 60 pie2 oscfie cmie ? eeie bcl1ie hlvdie tmr3ie ccp2ie 60 ipr2 oscfip cmip ? eeip bcl1ip hlvdip tmr3ip ccp2ip 60 tmr3l timer3 register low byte 59 tmr3h timer3 register high byte 59 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 58 t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 59 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer3 module.
pic18f8722 family ds39646b-page 176 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39646b-page 177 pic18f8722 family 16.0 timer4 module the timer4 timer module has the following features: 8-bit timer register (tmr4) 8-bit period register (pr4) readable and writable (both registers) software programmable prescaler (1:1, 1:4, 1:16) software programmable postscaler (1:1 to 1:16) interrupt on tmr4 match of pr4 timer4 has a control register shown in register 16-1. timer4 can be shut off by clearing control bit, tmr4on (t4con<2>), to minimize power consumption. the prescaler and postscaler selection of timer4 are also controlled by this register. figure 16-1 is a simplified block diagram of the timer4 module. 16.1 timer4 operation timer4 can be used as the pwm time base for the pwm mode of the ccp modules. the tmr4 register is readable and writable and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits t4ckps1:t4ckps0 (t4con<1:0>). the match out- put of tmr4 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr4 interrupt, latched in flag bit tmr4if (pir3<3>). the prescaler and postscaler counters are cleared when any of the following occurs: a write to the tmr4 register a write to the t4con register any device reset (power-on reset, mclr reset, watchdog timer reset or brown-out reset) tmr4 is not cleared when t4con is written. register 16-1: t4con: time r4 control register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? t4outps3 t4outps2 t4outps1 t4outps0 tmr4on t4ckps1 t4ckps0 bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6-3 t4outps3:t4outps0 : timer4 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 1111 = 1:16 postscale bit 2 tmr4on : timer4 on bit 1 = timer4 is on 0 = timer4 is off bit 1-0 t4ckps1:t4ckps0 : timer4 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 178 preliminary ? 2004 microchip technology inc. 16.2 timer4 interrupt the timer4 module has an 8-bit period register, pr4, which is both readable and writable. timer4 increments from 00h until it matches pr4 and then resets to 00h on the next increment cycle. the pr4 register is initialized to ffh upon reset. 16.3 output of tmr4 the output of tmr4 (before the postscaler) is used only as a pwm time base for the ccp modules. it is not used as a baud rate clock for the mssp, as is the timer2 output. figure 16-1: timer4 block diagram table 16-1: registers associated with timer4 as a timer/counter comparator tmr4 sets flag tmr4 output (1) reset postscaler prescaler pr4 2 f osc /4 1:1 to 1:16 1:1, 1:4, 1:16 eq 4 bit tmr4if t4outps3:t4outps0 t4ckps1:t4ckps0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 ipr3 ssp2ip bcl2ip rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip 60 pir3 ssp2if bcl2if rc2if tx2if tmr4if ccp5if ccp4if ccp3if 60 pie3 ssp2ie bcl2ie rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie 60 tmr4 timer4 register 61 t4con ? t4outps3 t4outps2 t4outps1 t4outps0 tmr4on t4ckps1 t4ckps0 61 pr4 timer4 period register 61 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer4 module.
? 2004 microchip technology inc. preliminary ds39646b-page 179 pic18f8722 family 17.0 capture/compare/pwm (ccp) modules the pic18f8722 family of devices all have a total of five ccp (capture/compare/pwm) modules. two of these (ccp4 and ccp5) implement standard capture, compare and pulse-width modulation (pwm) modes and are discussed in this section. the other three modules (eccp1, eccp2, eccp3) implement standard capture and compare modes, as well as enhanced pwm modes. these are discussed in section 18.0 ?enhanced capture/compare/pwm (eccp) module? . each ccp/eccp module contains a 16-bit register which can operate as a 16-bit capture register, a 16-bit compare register or a pwm master/slave duty cycle register. for the sake of clarity, all ccp module opera- tions in the following sections are described with respect to ccp4, but are equally applicable to ccp5. capture and compare operations described in this chap- ter apply to all standard and enhanced ccp modules. the operations of pwm mode described in section 17.4 ?pwm mode? apply to ccp4 and ccp5 only. register 17-1: ccpxcon: ccpx control register (ccp4 and ccp5 modules) note: throughout this section and section 18.0 ?enhanced capture/compare/pwm (eccp) module? , references to register and bit names that may be associated with a specific ccp module are referred to generically by the use of ?x? or ?y? in place of the specific module number. thus, ?ccpxcon? might refer to the control register for ccp4 or ccp5, or eccp1, eccp2 or eccp3. ?ccpxcon? is used throughout these sections to refer to the module control register, regardless of whether the ccp module is a standard or enhanced implementation. u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? dcxb1 dcxb0 ccpxm3 ccpxm2 ccpxm1 ccpxm0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-4 dcxb1:dcxb0 : pwm duty cycle bit 1 and bit 0 for ccp module x capture mode: unused. compare mode : unused. pwm mode: these bits are the two least significant bits (bit 1 and bit 0) of the 10-bit pwm duty cycle. the eight most significant bits (dcx9:dcx2) of the duty cycle are found in ccprxl. bit 3-0 ccpxm3:ccpxm0 : ccp module x mode select bits 0000 = capture/compare/pwm disabled; resets ccpx module 0001 = reserved 0010 = compare mode, toggle output on match; ccpxif bit is set 0011 = reserved 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, initialize ccpx pin low; on compare match, force ccpx pin high; ccpxif bit is set 1001 = compare mode, initialize ccpx pin high; on compare match, force ccpx pin low; ccpxif bit is set 1010 = compare mode, generate software interrupt on compare match; ccpxif bit is set; ccpx pin reflects i/o state 1011 = compare mode, trigger special event; ccpxif bit is set, ccpx pin is unaffected (see section 17.3.4 ?special event trigger? for effects of the trigger) 11xx =pwm mode legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 180 preliminary ? 2004 microchip technology inc. 17.1 ccp module configuration each capture/compare/pwm module is associated with a control register (generically, ccpxcon) and a data register (ccprx). the data register, in turn, is comprised of two 8-bit registers: ccprxl (low byte) and ccprxh (high byte). all registers are both readable and writable. 17.1.1 ccp modules and timer resources the ccp/eccp modules utilize timers 1, 2, 3 or 4, depending on the mode selected. timer1 and timer3 are available to modules in capture or compare modes, while timer2 and timer4 are available for modules in pwm mode. table 17-1: ccp mode ? timer resource the assignment of a particular timer to a module is determined by the timer-to-ccp enable bits in the t3con register (register 15-1). depending on the configuration selected, up to four timers may be active at once, with modules in the same configuration (capture/compare or pwm) sharing timer resources. the possible configurations are shown in figure 17-1. 17.1.2 eccp2 pin assignment the pin assignment for eccp2 (capture input, compare and pwm output) can change, based on device configuration. the ccp2mx configuration bit determines which pin eccp2 is multiplexed to. by default, it is assigned to rc1 (ccp2mx = 1 ). if the configuration bit is cleared, eccp2 is multiplexed with re7 in microcontroller mode, or re3 in all other modes. changing the pin assignment of eccp2 does not auto- matically change any requirements for configuring the port pin. users must always verify that the appropriate tris register is configured correctly for eccp2 operation regardless of where it is located. figure 17-1: ccp and timer interconnect configurations ccp mode timer resource capture compare pwm timer1 or timer3 timer1 or timer3 timer2 or timer4 tmr1 ccp5 tmr2 tmr3 tmr4 ccp4 eccp3 eccp2 eccp1 tmr1 tmr2 tmr3 ccp5 tmr4 ccp4 eccp3 eccp2 eccp1 tmr1 tmr2 tmr3 ccp5 tmr4 ccp4 eccp3 eccp2 eccp1 tmr1 tmr2 tmr3 ccp5 tmr4 ccp4 eccp3 eccp2 eccp1 t3ccp<2:1> = 00 t3ccp<2:1> = 01 t3ccp<2:1> = 10 t3ccp<2:1> = 11 timer1 is used for all capture and compare operations for all ccp modules. timer2 is used for pwm operations for all ccp modules. modules may share either timer resource as a common time base. timer3 and timer4 are not available. timer1 and timer2 are used for capture and compare or pwm operations for eccp1 only (depending on selected mode). all other modules use either timer3 or timer4. modules may share either timer resource as a common time base if they are in capture/ compare or pwm modes. timer1 and timer2 are used for capture and compare or pwm operations for eccp1 and eccp2 only (depending on the mode selected for each module). both modules may use a timer as a common time base if they are both in capture/compare or pwm modes. the other modules use either timer3 or timer4. modules may share either timer resource as a common time base if they are in capture/ compare or pwm modes. timer3 is used for all capture and compare operations for all ccp modules. timer4 is used for pwm operations for all ccp modules. modules may share either timer resource as a common time base. timer1 and timer2 are no t available.
? 2004 microchip technology inc. preliminary ds39646b-page 181 pic18f8722 family 17.2 capture mode in capture mode, the ccprxh:ccprxl register pair captures the 16-bit value of the tmr1 or tmr3 registers when an event occurs on the corresponding ccpx pin. an event is defined as one of the following: every falling edge every rising edge every 4th rising edge every 16th rising edge the event is selected by the mode select bits, ccpxm3:ccpxm0 (ccpxcon<3:0>). when a capture is made, the interrupt request flag bit, ccpxif, is set; it must be cleared in software. if another capture occurs before the value in the ccprx registers is read, the old captured value is overwritten by the new captured value. 17.2.1 ccpx pin configuration in capture mode, the appropriate ccpx pin should be configured as an input by setting the corresponding tris direction bit. 17.2.2 timer1/timer3 mode selection the timers that are to be used with the capture feature (timer1 and/or timer3) must be running in timer mode or synchronized counter mode. in asynchronous counter mode, the capture operation will not work. the timer to be used with each ccp module is selected in the t3con register (see section 17.1.1 ?ccp modules and timer resources? ). 17.2.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep the ccpxie interrupt enable bit clear to avoid false inter- rupts. the interrupt flag bit, ccpxif, should also be cleared following any such change in operating mode. 17.2.4 ccp prescaler there are four prescaler settings in capture mode; they are specified as part of the operating mode selected by the mode select bits (ccpxm3:ccpxm0). whenever the ccp module is turned off, or capture mode is disabled, the prescaler counter is cleared. this means that any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. example 17-1 shows the recommended method for switching between capture prescalers. this example also clears the prescaler counter and will not generate the ?false? interrupt. example 17-1: changing between capture prescalers (ccp5 shown) figure 17-2: capture mode operat ion block diagram note: if a ccpx pin is configured as an output, a write to the port can cause a capture condition. clrf ccp5con ; turn ccp module off movlw new_capt_ps ; load wreg with the ; new prescaler mode ; value and ccp on movwf ccp5con ; load ccp5con with ; this value ccpr4h ccpr4l tmr1h tmr1l set flag bit ccp4if tmr3 enable q?s ccp1con<3:0> rg3/ccp4 pin prescaler 1, 4, 16 and edge detect tmr3h tmr3l tmr1 enable t3ccp2 t3ccp2
pic18f8722 family ds39646b-page 182 preliminary ? 2004 microchip technology inc. 17.3 compare mode in compare mode, the 16-bit value of the ccprx registers is constantly compared against either the tmr1 or tmr3 register pair value. when a match occurs, the ccpx pin can be: driven high driven low toggled (high-to-low or low-to-high) remain unchanged (that is, reflects the state of the i/o latch) the action on the pin is based on the value of the mode select bits (ccpxm3:ccpxm0). at the same time, the interrupt flag bit, ccpxif, is set. 17.3.1 ccpx pin configuration the user must configure the ccpx pin as an output by clearing the appropriate tris bit. 17.3.2 timer1/timer3 mode selection timer1 and/or timer3 must be running in timer mode or synchronized counter mode if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 17.3.3 software interrupt mode when the generate software interrupt mode is chosen (ccpxm3:ccpxm0 = 1010 ), the corresponding ccpx pin is not affected. only a ccp interrupt is generated, if enabled and the ccpxie bit is set. 17.3.4 special event trigger all ccp modules are equipped with a special event trigger. this is an internal hardware signal generated in compare mode to trigger actions by other modules. the special event trigger is enabled by selecting the compare special event trigger mode (ccpxm3:ccpxm0 = 1011 ). for all ccp modules, the special event trigger resets the timer register pair for whichever timer resource is cur- rently assigned as the module?s time base. this allows the ccprx registers to serve as a programmable period register for either timer. the eccp2 special event trigger can also start an a/d conversion. in order to do this, the a/d converter must already be enabled. figure 17-3: compare mode operation block diagram note: clearing the ccpxcon register will force the compare output latch (depending on device configuration) to the default low level. this is not the port i/o data latch. ccpr4h ccpr4l tmr1h tmr1l comparator qs r output logic special event trigger set flag bit ccp4if match rg3/ccp4 pin trisg<3> ccp4con<3:0> mode select output enable tmr3h tmr3l t3ccp2 1 0
? 2004 microchip technology inc. preliminary ds39646b-page 183 pic18f8722 family table 17-2: registers associated with capture, compare, timer1 and timer3 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 rcon ipen sboren ? ri to pd por bor 56 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 60 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 60 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 60 pir2 oscfif cmif ? eeif bcl1if hlvdif tmr3if ccp2if 60 pie2 oscfie cmie ? eeie bcl1ie hlvdie tmr3ie ccp2ie 60 ipr2 oscfip cmip ? eeip bcl1ip hlvdip tmr3ip ccp2ip 60 pir3 ssp2if bcl2if rc2if tx2if tmr4if ccp5if ccp4if ccp3if 60 pie3 ssp2ie bcl2ie rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie 60 ipr3 ssp2ip bcl2ip rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip 60 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 60 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 60 trise trise7 trise6 trise5 trise4 trise3 trise2 trise1 trise0 60 trisg ? ? ? trisg4 trisg3 trisg2 trisg1 trisg0 60 trish (1) trish7 trish6 trish5 trish4 trish3 trish2 trish1 trish0 60 tmr1l timer1 register low byte 58 tmr1h timer1 register high byte 58 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 58 tmr3h timer3 register high byte 59 tmr3l timer3 register low byte 59 t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 59 ccpr1l enhanced capture/compare/pwm register 1 low byte 59 ccpr1h enhanced capture/compare/pwm register 1 high byte 59 ccp1con p1m1 p1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 59 ccpr2l enhanced capture/compare/pwm register 2 low byte 59 ccpr2h enhanced capture/compare/pwm register 2 high byte 59 ccp2con p2m1 p2m0 dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 59 ccp3con p3m1 p3m0 dc3b1 dc3b0 ccp3m3 ccp3m2 ccp3m1 ccp3m0 59 ccp4con ? ? dc4b1 dc4b0 ccp4m3 ccp4m2 ccp4m1 ccp4m0 61 ccp5con ? ? dc5b1 dc5b0 ccp5m3 ccp5m2 ccp5m1 ccp5m0 61 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by capture/compare, timer1 or timer3. note 1: implemented on 80-pin devices only.
pic18f8722 family ds39646b-page 184 preliminary ? 2004 microchip technology inc. 17.4 pwm mode in pulse-width modulation (pwm) mode, the ccpx pin produces up to a 10-bit resolution pwm output. since the ccp4 and ccp5 pins are multiplexed with a portg data latch, the appropriate trisg bit must be cleared to make the ccp4 or ccp5 pin an output. figure 17-4 shows a simplified block diagram of the ccp module in pwm mode. for a step-by-step procedure on how to set up a ccp module for pwm operation, see section 17.4.3 ?setup for pwm operation? . figure 17-4: simplified pwm block diagram a pwm output (figure 17-5) has a time base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 17-5: pwm output 17.4.1 pwm period the pwm period is specified by writing to the pr2 (pr4) register. the pwm period can be calculated using the following formula: equation 17-1: pwm frequency is defined as 1/[pwm period]. when tmr2 (tmr4) is equal to pr2 (pr4), the following three events occur on the next increment cycle: tmr2 (tmr4) is cleared the ccpx pin is set (exception: if pwm duty cycle = 0%, the ccpx pin will not be set) the pwm duty cycle is latched from ccprxl into ccprxh 17.4.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccprxl register and to the ccpxcon<5:4> bits. up to 10-bit resolution is available. the ccprxl contains the eight msbs and the ccpxcon<5:4> contains the two lsbs. this 10-bit value is represented by ccprxl:ccpxcon<5:4>. the following equation is used to calculate the pwm duty cycle in time: equation 17-2: ccprxl and ccpxcon<5:4> can be written to at any time, but the duty cycle value is not latched into ccprxh until after a match between pr2 (pr4) and tmr2 (tmr4) occurs (i.e., the period is complete). in pwm mode, ccprxh is a read-only register. note: clearing the ccp4con or ccp5con register will force the rg3 or rg4 output latch (depending on device configuration) to the default low level. this is not the portg i/o data latch. ccprxl ccprxh (slave) comparator tmr2 (tmr4) comparator pr2 (pr4) (note 1) r q s duty cycle registers ccpxcon<5:4> clear timer, ccpx pin and latch d.c. note 1: the 8-bit tmr2 or tmr4 value is concatenated with the 2-bit internal q clock, or 2 bits of the prescaler, to create the 10-bit time base. ccpx outpu t corresponding tris bit period duty cycle tmr2 (tmr4) = pr2 (tmr4) tmr2 (tmr4) = duty cycle tmr2 (tmr4) = pr2 (pr4) note: the timer2 and timer 4 postscalers (see section 14.0 ?timer2 module? and section 16.0 ?timer4 module? ) are not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different frequency than the pwm output. pwm period = [(pr2) + 1] 4 t osc (tmr2 prescale value) pwm duty cycle = (ccpr x l:ccp x con<5:4>) t osc (tmr2 prescale value)
? 2004 microchip technology inc. preliminary ds39646b-page 185 pic18f8722 family the ccprxh register and a 2-bit internal latch are used to double-buffer the pwm duty cycle. this double-buffering is essential for glitchless pwm operation. when the ccprxh and 2-bit latch match tmr2 (tmr4), concatenated with an internal 2-bit q clock or 2 bits of the tmr2 (tmr4) prescaler, the ccpx pin is cleared. the maximum pwm resolution (bits) for a given pwm frequency is given by the equation: equation 17-3: 17.4.3 setup for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 (pr4) register. 2. set the pwm duty cycle by writing to the ccprxl register and ccpxcon<5:4> bits. 3. make the ccpx pin an output by clearing the appropriate tris bit. 4. set the tmr2 (tmr4) prescale value, then enable timer2 (timer4) by writing to t2con (t4con). 5. configure the ccpx module for pwm operation. table 17-3: example pwm frequencies and resolutions at 40 mhz note: if the pwm duty cycle value is longer than the pwm period, the ccpx pin will not be cleared. f osc f pwm --------------- ?? ?? log 2 () log ----------------------------- b i t s = pwm resolution (max) pwm frequency 2.44 khz 9.77 khz 39.06 khz 156.25 khz 312.50 khz 416.67 khz timer prescaler (1, 4, 16)1641111 pr2 value ffh ffh ffh 3fh 1fh 17h maximum resolution (bits) 10 10 10 8 7 6.58
pic18f8722 family ds39646b-page 186 preliminary ? 2004 microchip technology inc. table 17-4: registers associated with pwm, timer2 and timer4 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 rcon ipen sboren ? ri to pd por bor 56 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 60 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 60 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 60 pir3 ssp2if bcl2if rc2if tx2if tmr4if ccp5if ccp4if ccp3if 60 pie3 ssp2ie bcl2if rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie 60 ipr3 ssp2ip bcl2ip rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip 60 tmr2 timer2 register 58 pr2 timer2 period register 58 t2con ? t2outps3 t2outps2 t2outps1 t2o utps0 tmr2on t2ckps1 t2ckps0 58 tmr4 timer4 register 61 pr4 timer4 period register 61 t4con ? t4outps3 t4outps2 t4outps1 t4o utps0 tmr4on t4ckps1 t4ckps0 61 ccpr1l enhanced capture/compare/pwm register 1 low byte 59 ccpr1h enhanced capture/compare/pwm register 1 high byte 59 ccpr2l enhanced capture/compare/pwm register 2 low byte 59 ccpr2h enhanced capture/compare/pwm register 2 high byte 59 ccp4con ? ? dc4b1 dc4b0 ccp4m3 ccp4m2 ccp4m1 ccp4m0 61 ccp5con ? ? dc5b1 dc5b0 ccp5m3 ccp5m2 ccp5m1 ccp5m0 61 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by pwm, timer2 or timer4.
? 2004 microchip technology inc. preliminary ds39646b-page 187 pic18f8722 family 18.0 enhanced capture/ compare/pwm (eccp) module in the pic18f8722 family of devices, eccp1, eccp2 and eccp3 are implemented as a standard ccp module with enhanced pwm capabilities. these include the provision for 2 or 4 output channels, user selectable polarity, dead-band control and automatic shutdown and restart. the enhanced features are discussed in detail in section 18.4 ?enhanced pwm mode? . capture, compare and single-output pwm functions of the eccp module are the same as described for the standard ccp module. the control register for the enhanced ccp modules is shown in register 18-1. it differs from the ccpxcon registers discussed in section 17.0 ?capture/ compare/pwm (ccp) modules? in that the two most significant bits are implemented to control pwm functionality. in addition to the expanded range of modes available through the enhanced ccpxcon register, the eccp modules each have two additional features associated with enhanced pwm operation and auto-shutdown features. they are: eccpxdel (dead-band delay) eccpxas (auto-shutdown configuration) register 18-1: ccpxcon: enhanced ccpx control register (eccp1, eccp2, eccp3) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pxm1 pxm0 dcxb1 dcxb0 ccpxm3 ccpxm2 ccpxm1 ccpxm0 bit 7 bit 0 bit 7-6 pxm1:pxm0: enhanced pwm output configuration bits if ccpxm3:ccpxm2 = 00 , 01 , 10 : xx = pxa assigned as capture/compare input/output; pxb, pxc, pxd assigned as port pins if ccpxm3:ccpxm2 = 11 : 00 = single output: pxa modulated; pxb, pxc, pxd assigned as port pins 01 = full-bridge output forward: p1d modulated; p1a active; p1b, p1c inactive 10 = half-bridge output: p1a, p1b modulated with dead-band control; p1c, p1d assigned as port pins 11 = full-bridge output reverse: p1b modulated; p1c active; p1a, p1d inactive bit 5-4 dcxb1:dcxb0 : pwm duty cycle bit 1 and bit 0 capture mode: unused. compare mode: unused. pwm mode: these bits are the two lsbs of the 10-bit pwm duty cycle. the eight msbs of the duty cycle are found in ccprxl. bit 3-0 ccpxm3:ccpxm0 : enhanced ccp mode select bits 0000 = capture/compare/pwm off (resets eccpx module) 0001 = reserved 0010 = compare mode: toggle output on match 0011 = capture mode 0100 = capture mode: every falling edge 0101 = capture mode: every rising edge 0110 = capture mode: every 4th rising edge 0111 = capture mode: every 16th rising edge 1000 = compare mode: initialize eccpx pin low; set output on compare match (set ccpxif) 1001 = compare mode: initialize eccpx pin high; clear output on compare match (set ccpxif) 1010 = compare mode: generate software interrupt only; eccpx pin reverts to i/o state 1011 = compare mode: trigger special event (eccp resets tmr1 or tmr3, sets ccpxif bit; eccp2 trigger starts a/d conversion if a/d module is enabled) 1100 = pwm mode: pxa, pxc active-high; pxb, pxd active-high 1101 = pwm mode: pxa, pxc active-high; pxb, pxd active-low 1110 = pwm mode: pxa, pxc active-low; pxb, pxd active-high 1111 = pwm mode: pxa, pxc active-low; pxb, pxd active-low legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 188 preliminary ? 2004 microchip technology inc. 18.1 eccp outputs and configuration each of the enhanced ccp modules may have up to four pwm outputs, depending on the selected operating mode. these outputs, designated pxa through pxd, are multiplexed with various i/o pins. some eccpx pin assignments are constant, while others change based on device configuration. for those pins that do change, the controlling bits are: ccp2mx configuration bit (config3h<0>) eccpmx configuration bit (config3h<1>) program memory mode (set by configuration bits, config3l<1:0>) the pin assignments for the enhanced ccp modules are summarized in table 18-1, table 18-2 and table 18-3. to configure the i/o pins as pwm outputs, the proper pwm mode must be selected by setting the pxmx and ccpxmx bits (ccpxcon<7:6> and <3:0>, respectively). the appropriate tris direction bits for the corresponding port pins must also be set as outputs. 18.1.1 use of ccp4 and ccp5 with eccp1 and eccp3 only the eccp2 module has four dedicated output pins available for use. assuming that the i/o ports or other multiplexed functions on those pins are not needed, they may be used whenever needed without interfering with any other ccp module. eccp1 and eccp3, on the other hand, only have three dedicated output pins: eccpx/p3a, pxb and pxc. whenever these modules are configured for quad pwm mode, the pin used for ccp4 or ccp5 takes priority over the d output pins for eccp3 and eccp1, respectively. 18.1.2 eccp module outputs, program memory modes and emb address bus width for pic18f8527/8622/8627/8722 devices, the program memory mode of the device ( section 7.2 ?address and data width? and section 7.4 ?pro- gram memory modes and the external memory bus? ) impacts both pin multiplexing and the operation of the module. the eccp2 input/output (eccp2/p2a) can be multi- plexed to one of three pins. by default, this is rc1 for all devices; in this case, the default is in effect when ccp2mx is set and the device is operating in micro- controller mode. with pic18f8527/8622/8627/8722 devices, three other options exist. when ccp2mx is not set (= 0 ) and the device is in microcontroller mode, eccp2/p2a is multiplexed to re7; in all other program memory modes, it is multiplexed to rb3. another option is for eccpmx to be set while the device is operating in one of the three other program memory modes. in this case, eccp1 and eccp3 oper- ate as compatible (i.e., single output) ccp modules. the pins used by their other outputs (pxb through pxd) are available for other multiplexed functions. eccp2 continues to operate as an enhanced ccp module regardless of the program memory mode. the final option is that the abw<1:0> configuration bits can be used to select 8, 12, 16 or 20-bit emb address- ing. pins not assigned to emb address pins are available for peripheral or port functions.
? 2004 microchip technology inc. preliminary ds39646b-page 189 pic18f8722 family table 18-1: pin config urations for eccp1 eccp mode ccp1con configuration rc2 re6 re5 rg4 rh7 rh6 pic18f6527/6622/6627/6722 devices: compatible ccp 00xx 11xx eccp1 re6 re5 rg4/ccp5 n/a n/a dual pwm 10xx 11xx p1a p1b re5 rg4/ccp5 n/a n/a quad pwm x1xx 11xx p1a p1b p1c ccp5/p1d (1) n/a n/a pic18f8527/8622/8627/8722 devices, eccpmx = 1 , microcontroller mode: compatible ccp 00xx 11xx eccp1 re6 re5 rg4/ccp5 rh7/an15 rh6/an14 dual pwm 10xx 11xx p1a p1b re5 rg4/ccp5 rh7/an15 rh6/an14 quad pwm x1xx 11xx p1a p1b p1c ccp5/p1d (1) rh7/an15 rh6/an14 pic18f8527/8622/8627/8722 devices, eccpmx = 0 , microcontroller mode: compatible ccp 00xx 11xx eccp1 re6 re5 rg4/ccp5 rh7/an15 rh6/an14 dual pwm 10xx 11xx p1a re6 re5 rg4/ccp5 p1b rh6/an14 quad pwm x1xx 11xx p1a re6 re5 ccp5/p1d (1) p1b p1c pic18f8527/8622/8627/8722 devices, eccpmx = 1 , all other program memory modes: compatible ccp 00xx 11xx eccp1 ad14 (2) ad13 (2) rg4/ccp5 rh7/an15 rh6/an14 dual pwm 10xx 11xx p1a p1b/ad14 (2) ad13 (2) rg4/ccp5 rh7/an15 rh6/an14 quad pwm x1xx 11xx p1a p1b/ad14 (2) p1c/ad13 (2) ccp5/p1d (1) rh7/an15 rh6/an14 pic18f8527/8622/8627/8722 devices, eccpmx = 0 , all other program memory modes: compatible ccp 00xx 11xx eccp1 ad14 (2) ad13 (2) rg4/ccp5 rh7/an15 rh6/an14 dual pwm 10xx 11xx p1a ad14 (2) ad13 (2) rg4/ccp5 p1b rh6/an14 quad pwm x1xx 11xx p1a ad14 (2) ad13 (2) ccp5/p1d (1) p1b p1c legend: x = don?t care, n/a = not available. shaded cells indicate pin assignments not used by eccp1 in a given mode. note 1: with eccp1 in quad pwm mode, the ccp5 module?s output overrides p1d. 2: the emb address bus width will determine whether the pin will perform an emb or port/peripheral function.
pic18f8722 family ds39646b-page 190 preliminary ? 2004 microchip technology inc. table 18-2: pin config urations for eccp2 eccp mode ccp2con configuration rb3 rc1 re7 re2 re1 re0 pic18f6527/6622/6627/6722 devices, ccp2mx = 1 : compatible ccp 00xx 11xx rb3/int3 eccp2 re7 re2 re1 re0 dual pwm 10xx 11xx rb3/int3 p2a re7 p2b re1 re0 quad pwm x1xx 11xx rb3/int3 p2a re7 p2b p2c p2d pic18f6527/6622/6627/6722 devices ccp2mx = 0 : compatible ccp 00xx 11xx rb3/int3 rc1/t1osi eccp2 re2 re1 re0 dual pwm 10xx 11xx rb3/int3 rc1/t1osi p2a p2b re1 re0 quad pwm x1xx 11xx rb3/int3 rc1/t1osi p2a p2b p2c p2d pic18f8527/8622/8627/8722 devices, ccp2mx = 1 , microcontroller mode: compatible ccp 00xx 11xx rb3/int3 eccp2 re7 re2 re1 re0 dual pwm 10xx 11xx rb3/int3 p2a re7 p2b re1 re0 quad pwm x1xx 11xx rb3/int3 p2a re7 p2b p2c p2d pic18f8527/8622/8627/8722 devices, ccp2mx = 0 , microcontroller mode: compatible ccp 00xx 11xx rb3/int3 rc1/t1osi eccp2 re2 re1 re0 dual pwm 10xx 11xx rb3/int3 rc1/t1osi p2a p2b re1 re0 quad pwm x1xx 11xx rb3/int3 rc1/t1osi p2a p2b p2c p2d pic18f8527/8622/8627/8722 devices, ccp2mx = 1 , all other program memory modes: compatible ccp 00xx 11xx rb3/int3 eccp2 ad15 (1) ad10 (1) ad9 (1) ad8 (1) dual pwm 10xx 11xx rb3/int3 p2a ad15 (1) ad10/p2b (1) ad9 (1) ad8 (1) quad pwm x1xx 11xx rb3/int3 p2a ad15 (1) ad10/p2b (1) ad9/p2c (1) p2d/ad8 (1) pic18f8527/8622/8627/8722 devices, ccp2mx = 0 , all other program memory modes: compatible ccp 00xx 11xx eccp2 rc1/t1osi ad15 (1) ad10 (1) ad9 (1) ad8 (1) dual pwm 10xx 11xx p2a rc1/t1osi ad15 (1) ad10/p2b (1) ad9 (1) ad8 (1) quad pwm x1xx 11xx p2a rc1/t1osi ad15 (1) ad10/p2b (1) ad9/p2c (1) p2d/ad8 (1) legend: x = don?t care. shaded cells indicate pin assignments not used by eccp2 in a given mode. note 1: the emb address bus width will determine whether the pin will perform an emb or port/peripheral function.
? 2004 microchip technology inc. preliminary ds39646b-page 191 pic18f8722 family table 18-3: pin config urations for eccp3 eccp mode ccp3con configuration rg0 re4 re3 rg3 rh5 rh4 pic18f6527/6622/6627/6722 devices: compatible ccp 00xx 11xx eccp3 re4 re3 rg3/ccp4 n/a n/a dual pwm 10xx 11xx p3a p3b re3 rg3/ccp4 n/a n/a quad pwm x1xx 11xx p3a p3b p3c ccp4/p3d (1) n/a n/a pic18f8527/8622/8627/8722 devices, eccpmx = 1 , microcontroller mode: compatible ccp 00xx 11xx eccp3 re4 re3 rg3/ccp4 rh5/an13 rh4/an12 dual pwm 10xx 11xx p3a p3b re3 rg3/ccp4 rh5/an13 rh4/an12 quad pwm x1xx 11xx p3a p3b p3c ccp4/p3d (1) rh5/an13 rh4/an12 pic18f8527/8622/8627/8722 devices, eccpmx = 0 , microcontroller mode: compatible ccp 00xx 11xx eccp3 re4 re3 rg3/ccp4 rh5/an13 rh4/an12 dual pwm 10xx 11xx p3a re4 re3 rg3/ccp4 p3b rh4/an12 quad pwm x1xx 11xx p3a re4 re3 ccp4/p3d (1) p3b p3c pic18f8527/8622/8627/8722 devices, eccpmx = 1 , all other program memory modes: compatible ccp 00xx 11xx eccp3 ad12 (2) ad10 (2) rg3/ccp4 rh5/an13 rh4/an12 dual pwm 10xx 11xx p3a ad12/p3b (2) ad10 (2) rg3/ccp4 rh5/an13 rh4/an12 quad pwm x1xx 11xx p3a ad12/p3b (2) p3c/ad10 (1) ccp4/p3d (1) rh5/an13 rh4/an12 pic18f8527/8622/8627/8722 devices, eccpmx = 0 , all other program memory modes: compatible ccp 00xx 11xx eccp3 ad12 (2) ad10 (2) rg3/ccp4 rh5/an13 rh4/an12 dual pwm 10xx 11xx p3a ad12 (2) ad10 (2) rg3/ccp4 p3b rh4/an12 quad pwm x1xx 11xx p3a ad12 (2) ad10 (2) ccp4/p3d (1) p3b p3c legend: x = don?t care, n/a = not available. shaded cells indicate pin assignments not used by eccp3 in a given mode. note 1: with eccp3 in quad pwm mode, the ccp4 module?s output overrides p3d. 2: the emb address bus width will determine whether the pin will perform an emb or port/peripheral function.
pic18f8722 family ds39646b-page 192 preliminary ? 2004 microchip technology inc. 18.1.3 eccp modules and timer resources like the standard ccp modules, the eccp modules can utilize timers 1, 2, 3 or 4, depending on the mode selected. timer1 and timer3 are available for modules in capture or compare modes, while timer2 and timer4 are available for modules in pwm mode. additional details on timer resources are provided in section 17.1.1 ?ccp modules and timer resources? . 18.2 capture and compare modes with the exception of the special event trigger discussed below, the capture and compare modes of the eccp modules are identical in operation to that of ccp4. these are discussed in detail in section 17.2 ?capture mode? and section 17.3 ?compare mode? . 18.2.1 special event trigger the special event trigger output of eccpx resets the tmr1 or tmr3 register pair, depending on which timer resource is currently selected. this allows the ccprx registers to effectively be 16-bit programmable period registers for timer1 or timer3. 18.3 standard pwm mode when configured in single output mode, the eccp module functions identically to the standard ccp module in pwm mode as described in section 17.4 ?pwm mode? . this is also sometimes referred to as ?compatible ccp? mode as in tables 18-1 through 18-3. 18.4 enhanced pwm mode the enhanced pwm mode provides additional pwm output options for a broader range of control applica- tions. the module is a backward compatible version of the standard ccp module and offers up to four outputs, designated pxa through pxd. users are also able to select the polarity of the signal (either active-high or active-low). the module?s output mode and polarity are configured by setting the pxm1:pxm0 and ccpxm3:ccpxm0 bits of the ccpxcon register (ccpxcon<7:6> and ccpxcon<3:0>, respectively). for the sake of clarity, enhanced pwm mode operation is described generically throughout this section with respect to eccp1 and tmr2 modules. control register names are presented in terms of eccp1. all three enhanced modules, as well as the two timer resources, can be used interchangeably and function identically. tmr2 or tmr4 can be selected for pwm operation by selecting the proper bits in t3con. figure 18-1 shows a simplified block diagram of pwm operation. all control registers are double-buffered and are loaded at the beginning of a new pwm cycle (the period boundary when timer2 resets) in order to pre- vent glitches on any of the outputs. the exception is the pwm delay register, eccp1del, which is loaded at either the duty cycle boundary or the boundary period (whichever comes first). because of the buffering, the module waits until the assigned timer resets instead of starting immediately. this means that enhanced pwm waveforms do not exactly match the standard pwm waveforms, but are instead offset by one full instruction cycle (4 t osc ). as before, the user must manually configure the appropriate tris bits for output. 18.4.1 pwm period the pwm period is specified by writing to the pr2 register. the pwm period can be calculated using the following equation: equation 18-1: pwm frequency is defined as 1/[pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: tmr2 is cleared the eccp1 pin is set (if pwm duty cycle = 0%, the eccp1 pin will not be set) the pwm duty cycle is copied from ccpr1l into ccpr1h note: when setting up single output pwm operations, users are free to use either of the processes described in section 17.4.3 ?setup for pwm operation? or section 18.4.9 ?setup for pwm opera- tion? . the latter is more generic, but will work for either single or multi-output pwm. note: the timer2 postscaler (see section 14.0 ?timer2 module? ) is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different frequency than the pwm output. pwm period = [(pr2) + 1] 4 t osc (tmr2 prescale value)
? 2004 microchip technology inc. preliminary ds39646b-page 193 pic18f8722 family figure 18-1: simplified block diagram of the enhanced pwm module 18.4.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available. the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr1l:ccp1con<5:4>. the pwm duty cycle is calculated by the equation: equation 18-2: ccpr1l and ccp1con<5:4> can be written to at any time but the duty cycle value is not copied into ccpr1h until a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read-only register. the ccpr1h register and a 2-bit internal latch are used to double-buffer the pwm duty cycle. this double-buffering is essential for glitchless pwm opera- tion. when the ccpr1h and 2-bit latch match tmr2, concatenated with an internal 2-bit q clock or two bits of the tmr2 prescaler, the eccp1 pin is cleared. the maximum pwm resolution (bits) for a given pwm frequency is given by the equation: equation 18-3: table 18-4: example pwm frequencies and resolutions at 40 mhz ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) rq s duty cycle registers ccp1con<5:4> clear timer, set eccp1 pin and latch d.c. note: the 8-bit tmr2 register is concatenated with the 2-bit internal q clock, or 2 bits of the prescaler, to create the 10-bit time base. trisx eccp1/p1a trisx p1b trisx trisx p1d output controller p1m1<1:0> 2 ccp1m<3:0> 4 eccp1del eccp1/p1a p1b p1c p1d p1c pwm duty cycle = (ccpr1l:ccp1con<5:4>) t osc (tmr2 prescale value) note: if the pwm duty cycle value is longer than the pwm period, the eccp1 pin will not be cleared. ( ) pwm resolution (max) = f osc f pwm log log(2) bits pwm frequency 2.44 khz 9.77 khz 39.06 khz 156.25 khz 312.50 khz 416.67 khz timer prescaler (1, 4, 16)1641111 pr2 value ffh ffh ffh 3fh 1fh 17h maximum resolution (bits) 10 10 10 8 7 6.58
pic18f8722 family ds39646b-page 194 preliminary ? 2004 microchip technology inc. 18.4.3 pwm output configurations the p1m1:p1m0 bits in the ccp1con register allow one of four configurations: single output half-bridge output full-bridge output, forward mode full-bridge output, reverse mode the single output mode is the standard pwm mode discussed in section 18.4 ?enhanced pwm mode? . the half-bridge and full-bridge output modes are covered in detail in the sections that follow. the general relationship of the outputs in all configurations is summarized in figure 18-2. figure 18-2: pwm output relationships (active-high state) 0 period 00 10 01 11 signal pr2 + 1 ccp1con<7:6> p1a modulated p1a modulated p1b modulated p1a active p1b inactive p1c inactive p1d modulated p1a inactive p1b modulated p1c active p1d inactive duty cycle (single output) (half-bridge) (full-bridge, forward) (full-bridge, reverse) delay (1) delay (1) relationships: period = 4 * t osc * (pr2 + 1) * (tmr2 prescale value) duty cycle = t osc * (ccpr1l<7:0>:ccp1con<5:4>) * (tmr2 prescale value) delay = 4 * t osc * (eccp1del<6:0>) note 1: dead-band delay is programmed us ing the eccp1del register ( section 18.4.6 ?programmable dead-band delay? ).
? 2004 microchip technology inc. preliminary ds39646b-page 195 pic18f8722 family figure 18-3: pwm output relationships (active-low state) 0 period 00 10 01 11 signal pr2 + 1 ccp1con<7:6> p1a modulated p1a modulated p1b modulated p1a active p1b inactive p1c inactive p1d modulated p1a inactive p1b modulated p1c active p1d inactive duty cycle (single output) (half-bridge) (full-bridge, forward) (full-bridge, reverse) delay (1) delay (1) relationships: period = 4 * t osc * (pr2 + 1) * (tmr2 prescale value) duty cycle = t osc * (ccpr1l<7:0>:ccp1con<5:4>) * (tmr2 prescale value) delay = 4 * t osc * (eccp1del<6:0>) note 1: dead-band delay is programmed usi ng the eccp1del register ( section 18.4.6 ?programmable dead-band delay? ).
pic18f8722 family ds39646b-page 196 preliminary ? 2004 microchip technology inc. 18.4.4 half-bridge mode in the half-bridge output mode, two pins are used as outputs to drive push-pull loads. the pwm output sig- nal is output on the p1a pin, while the complementary pwm output signal is output on the p1b pin (figure 18-4). this mode can be used for half-bridge applications, as shown in figure 18-5, or for full-bridge applications, where four power switches are being modulated with two pwm signals. in half-bridge output mode, the programmable dead-band delay can be used to prevent shoot-through current in half-bridge power devices. the value of bits, p1dc6:p1dc0 sets the number of instruction cycles before the output is driven active. if the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. see section 18.4.6 ?programmable dead-band delay? for more details on dead-band delay operations. the p1a and p1b outputs are multiplexed with the portc<2> and porte<6> data latches. alterna- tively, p1b can be assigned to porth<7> by program- ming the eccpmx configuration bit to ? 0 ?. see table 18-1, table 18-2 and table 18-3 for more information. the associated tris bit must be cleared to configure p1a and p1b as outputs. figure 18-4: half-bridge pwm output figure 18-5: examples of half-bri dge output mode applications period duty cycle td td (1) p1a (2) p1b (2) td = dead band delay period (1) (1) note 1: at this time, the tmr2 register is equal to the pr2 register. 2: output signals are shown as active-high. pic18f6x27/6x22/8x27/8x22 p1a p1b fet driver fet driver v+ v- load + v - + v - fet driver fet driver v+ v- load fet driver fet driver pic18f6x27/6x22/8x27/8x22 p1a p1b standard half-bridge circuit (?push-pull?) half-bridge output driving a full-bridge circuit
? 2004 microchip technology inc. preliminary ds39646b-page 197 pic18f8722 family 18.4.5 full-bridge mode in full-bridge output mode, four pins are used as outputs; however, only two outputs are active at a time. in the forward mode, pin p1a is continuously active and pin p1d is modulated. in the reverse mode, pin p1c is continuously active and pin p1b is modulated. these are illustrated in figure 18-6. p1a, p1b, p1c and p1d outputs are multiplexed with the portc<2>, porte<6:5> and portg<4> data latches. alternatively, p1b and p1c can be assigned to porth<7> and porth<6>, respectively, by program- ming the eccpmx configuration bit to ? 0 ?. see table 18-1, table 18-2 and table 18-3 for more infor- mation. the associated bits must be cleared to make the p1a, p1b, p1c and p1d pins outputs. figure 18-6: full-bridge pwm output period duty cycle p1a (2) p1b (2) p1c (2) p1d (2) forward mode (1) period duty cycle p1a (2) p1c (2) p1d (2) p1b (2) reverse mode (1) (1) (1) note 1: at this time, the tmr2 register is equal to the pr2 register. note 2: output signal is shown as active-high.
pic18f8722 family ds39646b-page 198 preliminary ? 2004 microchip technology inc. figure 18-7: example of full-bridge application 18.4.5.1 direction change in full-bridge mode in the full-bridge output mode, the p1m1 bit in the ccp1con register allows users to control the forward/ reverse direction. when the application firmware changes this direction control bit, the module will assume the new direction on the next pwm cycle. just before the end of the current pwm period, the modulated outputs (p1b and p1d) are placed in their inactive state, while the unmodulated outputs (p1a and p1c) are switched to drive in the opposite direction. this occurs in a time interval of (4 t osc * (timer2 prescale value)) before the next pwm period begins. the timer2 prescaler will be either 1, 4 or 16, depend- ing on the value of the t2ckpsx bit (t2con<1:0>). during the interval from the switch of the unmodulated outputs to the beginning of the next period, the modulated outputs (p1b and p1d) remain inactive. this relationship is shown in figure 18-8. note that in the full-bridge output mode, the eccp1 module does not provide any dead-band delay. in gen- eral, since only one output is modulated at all times, dead-band delay is not required. however, there is a situation where a dead-band delay might be required. this situation occurs when both of the following conditions are true: 1. the direction of the pwm output changes when the duty cycle of the output is at or near 100%. 2. the turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. figure 18-9 shows an example where the pwm direc- tion changes from forward to reverse at a near 100% duty cycle. at time t1, the outputs p1a and p1d become inactive, while output p1c becomes active. in this example, since the turn-off time of the power devices is longer than the turn-on time, a shoot-through current may flow through power devices qc and qd (see figure 18-7) for the duration of ?t?. the same phenomenon will occur to power devices qa and qb for pwm direction change from reverse to forward. if changing pwm direction at high duty cycle is required for an application, one of the following requirements must be met: 1. reduce pwm for a pwm period before changing directions. 2. use switch drivers that can drive the switches off faster than they can drive them on. other options to prevent shoot-through current may exist. pic18f6x27/6x22/8x27/8x22 p1a p1c fet driver fet driver v+ v- load fet driver fet driver p1b p1d qa qb qd qc
? 2004 microchip technology inc. preliminary ds39646b-page 199 pic18f8722 family figure 18-8: pwm direction change figure 18-9: pwm direction chang e at near 100% duty cycle (1) dc period (1) signal note 1: the direction bit in the eccp1 control register (ccp 1con<7>) is written any time during the pwm cycle. 2: when changing directions, the p1a and p1c signals switch before the end of the current pwm cycle at intervals of 4 t osc , 16 t osc or 64 t osc , depending on the timer2 prescaler value. the modulated p1b and p1d signals are inactive at this time. period (note 2) p1a (active-high) p1b (active-high) p1c (active-high) p1d (active-high) dc forward period reverse period p1a t on (2) t off (3) t = t off ? t on p1b p1c p1d external switch d potential shoot-through current note 1: all signals are shown as active-high. 2: t on is the turn-on delay of power switch qc and its driver. 3: t off is the turn-off delay of power switch qd and its driver. external switch c t1 dc dc
pic18f8722 family ds39646b-page 200 preliminary ? 2004 microchip technology inc. 18.4.6 programmable dead-band delay in half-bridge applications where all power switches are modulated at the pwm frequency at all times, the power switches normally require more time to turn off than to turn on. if both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period of time until one switch completely turns off. during this brief interval, a very high current ( shoot-through current ) may flow through both power switches, shorting the bridge supply. to avoid this potentially destructive shoot-through current from flow- ing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. in the half-bridge output mode, a digitally program- mable dead-band delay is available to avoid shoot-through current from destroying the bridge power switches. the delay occurs at the signal transi- tion from the non-active state to the active state. see figure 18-4 for illustration. the lower seven bits of the eccp1del register (register 18-2) set the delay period in terms of microcontroller instruction cycles (t cy or 4 t osc ). 18.4.7 enhanced pwm auto-shutdown when the eccp is programmed for any of the enhanced pwm modes, the active output pins may be configured for auto-shutdown. auto-shutdown immedi- ately places the enhanced pwm output pins into a defined shutdown state when a shutdown event occurs. a shutdown event can be caused by either of the two comparator modules or the flt0 pin (or any combina- tion of these three source s). the comparators may be used to monitor a voltage input proportional to a current being monitored in the bridge circuit. if the voltage exceeds a threshold, the comparator switches state and triggers a shutdown. alternatively, a digital signal on the flt0 pin can also trigger a shutdown. the auto-shutdown feature can be disabled by not selecting any auto-shutdown sources. the auto-shutdown sources to be used are selected using the eccp1as2:eccp1as0 bits (eccp1as<6:4>). when a shutdown occurs, the output pins are asynchronously placed in their shutdown states, specified by the pss1ac1:pss1ac0 and pss1bd1:pss1bd0 bits (eccp1as<3:0>). each pin pair (p1a/p1c and p1b/p1d) may be set to drive high, drive low or be tri-stated (not driving). the eccp1ase bit (eccp1as<7>) is also set to hold the enhanced pwm outputs in their shutdown states. the eccp1ase bit is set by hardware when a shut- down event occurs. if automatic restarts are not enabled, the eccp1ase bit is cleared by firmware when the cause of the shutdown clears. if automatic restarts are enabled, the eccp1ase bit is auto- matically cleared when the cause of the auto-shutdown has cleared. if the eccp1ase bit is set when a pwm period begins, the pwm outputs remain in their shutdown state for that entire pwm period. when the eccp1ase bit is cleared, the pwm outputs will return to normal operation at the beginning of the next pwm period. register 18-2: eccpxdel: enhanced pwm config uration register note: writing to the eccp1ase bit is disabled while a shutdown condition is active. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pxrsen pxdc6 pxdc5 pxdc 4 pxdc3 pxdc2 pxdc1 pxdc0 bit 7 bit 0 bit 7 pxrsen: pwm restart enable bit 1 = upon auto-shutdown, the eccpxase bit clears automatically once the shutdown event goes away; the pwm restarts automatically 0 = upon auto-shutdown, the eccpxase bit must be cleared in software to restart the pwm bit 6-0 pxdc6:pxdc0: pwm delay count bits delay time, in number of f osc /4 (4 * t osc ) cycles, between the scheduled and actual time for a pwm signal to transition to active. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39646b-page 201 pic18f8722 family register 18-3: eccpxas: enhanced ccp auto-shutdown control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eccpxase eccpxas2 eccpxas1 eccpxas0 pssxac1 pssxac0 pssxbd1 pssxbd0 bit 7 bit 0 bit 7 eccpxase: eccp auto-shutdown event status bit 0 = eccp outputs are operating 1 = a shutdown event has occurred; eccp outputs are in shutdown state bit 6-4 eccpxas2:eccpxas0: eccp auto-shutdown source select bits 000 = auto-shutdown is disabled 001 = comparator 1 output 010 = comparator 2 output 011 = either comparator 1 or 2 100 =flt0 101 = flt0 or comparator 1 110 = flt0 or comparator 2 111 = flt0 or comparator 1 or comparator 2 bit 3-2 pssxac1:pssxac0: pins a and c shutdown state control bits 00 = drive pins a and c to ? 0 ? 01 = drive pins a and c to ? 1 ? 1x = pins a and c tri-state bit 1-0 pssxbd1:pssxbd0: pins b and d shutdown state control bits 00 = drive pins b and d to ? 0 ? 01 = drive pins b and d to ? 1 ? 1x = pins b and d tri-state legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 202 preliminary ? 2004 microchip technology inc. 18.4.7.1 auto-shutdown and automatic restart the auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. this is enabled by setting the p1rsen bit of the eccp1del register (eccp1del<7>). in shutdown mode with p1rsen = 1 (figure 18-10), the eccp1ase bit will remain set for as long as the cause of the shutdown continues. when the shutdown condition clears, the eccp1ase bit is cleared. if p1rsen = 0 (figure 18-11), once a shutdown condi- tion occurs, the eccp1ase bit will remain set until it is cleared by firmware. once eccp1ase is cleared, the enhanced pwm will resume at the beginning of the next pwm period. independent of the p1rsen bit setting, if the auto-shutdown source is one of the comparators, the shutdown condition is a level. the eccp1ase bit can- not be cleared as long as the cause of the shutdown persists. the auto-shutdown mode can be forced by writing a ? 1 ? to the eccp1ase bit. 18.4.8 start-up considerations when the eccp module is used in the pwm mode, the application hardware must use the proper external pull-up and/or pull-down resistors on the pwm output pins. when the microcontroller is released from reset, all of the i/o pins are in the high-impedance state. the external circuits must keep the power switch devices in the off state until the microcontroller drives the i/o pins with the proper signal levels or activates the pwm output(s). the ccp1m1:ccp1m0 bits (ccp1con<1:0>) allow the user to choose whether the pwm output signals are active-high or active-low for each pair of pwm output pins (p1a/p1c and p1b/p1d). the pwm output polarities must be selected before the pwm pins are configured as outputs. changing the polarity configura- tion while the pwm pins are configured as outputs is not recommended since it may result in damage to the application circuits. the p1a, p1b, p1c and p1d output latches may not be in the proper states when the pwm module is initialized. enabling the pwm pins for output at the same time as the eccp1 module may cause damage to the applica- tion circuit. the eccp1 module must be enabled in the proper output mode and complete a full pwm cycle before configuring the pwm pins as outputs. the com- pletion of a full pwm cycle is indicated by the tmr2if bit being set as the second pwm period begins. figure 18-10: pwm auto-shutdown (p1rsen = 1 , auto-restart enabled) figure 18-11: pwm auto-shutdown (p1rsen = 0 , auto-restart disabled) note: writing to the eccp1ase bit is disabled while a shutdown condition is active. shutdown pwm eccp1ase bit activity event shutdown event occurs shutdown event clears pwm resumes normal pwm start of pwm period pwm period shutdown pwm eccp1ase bit activity event shutdown event occurs shutdown event clears pwm resumes normal pwm start of pwm period eccp1ase cleared by firmware pwm period
? 2004 microchip technology inc. preliminary ds39646b-page 203 pic18f8722 family 18.4.9 setup for pwm operation the following steps should be taken when configuring the eccp1 module for pwm operation using timer2: 1. configure the pwm pins, p1a and p1b (and p1c and p1d, if used), as inputs by setting the corresponding tris bits. 2. set the pwm period by loading the pr2 register. 3. if auto-shutdown is required do the following: disable auto-shutdown (eccp1as = 0 ) configure source (flt0, comparator 1 or comparator 2) wait for non-shutdown condition 4. configure the eccp1 module for the desired pwm mode and configuration by loading the ccp1con register with the appropriate values: select one of the available output configurations and direction with the p1m1:p1m0 bits. select the polarities of the pwm output signals with the ccp1m3:ccp1m0 bits. 5. set the pwm duty cycle by loading the ccpr1l register and ccp1con<5:4> bits. 6. for half-bridge output mode, set the dead-band delay by loading eccp1del<6:0> with the appropriate value. 7. if auto-shutdown operation is required, load the eccp1as register: select the auto-shutdown sources using the eccp1as2:eccp1as0 bits. select the shutdown states of the pwm output pins using the pss1ac1:pss1ac0 and pss1bd1:pss1bd0 bits. set the eccp1ase bit (eccp1as<7>). configure the comparators using the cmcon register. configure the comparator inputs as analog inputs. 8. if auto-restart operation is required, set the p1rsen bit (eccp1del<7>). 9. configure and start tmr2: clear the tmr2 interrupt flag bit by clearing the tmr2if bit (pir1<1>). set the tmr2 prescale value by loading the t2ckps bits (t2con<1:0>). enable timer2 by setting the tmr2on bit (t2con<2>). 10. enable pwm outputs after a new pwm cycle has started: wait until tmrn overflows (tmrnif bit is set). enable the eccp1/p1a, p1b, p1c and/or p1d pin outputs by clearing the respective tris bits. clear the eccp1ase bit (eccp1as<7>). 18.4.10 operation in power-managed modes in sleep mode, all clock sources are disabled. timer2 or timer4 will not increment and the state of the module will not change. if the eccp1 pin is driving a value, it will continue to drive that value. when the device wakes up, it will continue from this st ate. if two-speed start-ups are enabled, the initial start-up frequency from intosc and the postscaler may not be stable immediately. in pri_idle mode, the primary clock will continue to clock the eccp1 module without change. in all other power-managed modes, the selected power-managed mode clock will clock timer2 or timer4. other power-managed mode clocks will most likely be different than the primary clock frequency. 18.4.10.1 operation with fail-safe clock monitor if the fail-safe clock monitor is enabled, a clock failure will force the device into the power-managed rc_run mode and the oscfif bit (pir2<7>) will be set. the eccp1 will then be clocked from the internal oscillator clock source, which may have a different clock frequency than the primary clock. see the previous section for additional details. 18.4.11 effects of a reset both power-on reset and subsequent resets will force all ports to input mode and the ccp registers to their reset states. this forces the enhanced ccp module to reset to a state compatible with the standard ccp module.
pic18f8722 family ds39646b-page 204 preliminary ? 2004 microchip technology inc. table 18-5: registers associated with eccp modules and timer1 to timer4 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 rcon ipen sboren ? ri to pd por bor 58 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 60 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 60 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 60 pir2 oscfif cmif ? eeif bcl1if hlvdif tmr3if ccp2if 60 pie2 oscfie cmie ? eeie bcl1ie hlvdie tmr3ie ccp2ie 60 ipr2 oscfip cmip ? eeip bcl1ip hlvdip tmr3ip ccp2ip 60 pir3 ssp2if bcl2if rc2if tx2if tmr4if ccp5if ccp4if ccp3if 60 pie3 ssp2ie bcl2ie rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie 60 ipr3 ssp2ip bcl2ip rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip 60 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 60 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 60 trise trise7 trise6 trise5 trise4 trise3 trise2 trise1 trise0 60 trisg ? ? ? trisg4 trisg3 trisg2 trisg1 trisg0 60 trish (2) trish7 trish6 trish5 trish4 trish3 trish2 trish1 trish0 60 tmr1l timer1 register low byte 58 tmr1h timer1 register high byte 58 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 58 tmr2 timer2 register 58 t2con ? t2outps3 t2outps2 t2outps1 t2outps0 tmr2on t2ckps1 t2ckps0 58 pr2 timer2 period register 58 tmr3l timer3 register low byte 59 tmr3h timer3 register high byte 59 t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 59 tmr4 timer4 register 61 t4con ? t4outps3 t4outps2 t4outps1 t4outps0 tmr4on t4ckps1 t4ckps0 61 pr4 timer4 period register 61 ccprxl (1) enhanced capture/compare/pwm register x low byte 59, 61 ccprxh (1) enhanced capture/compare/pwm register x high byte 59, 61 ccpxcon (1) pxm1 pxm0 dcxb1 dcxb0 ccpxm3 ccpxm2 ccpxm1 ccpxm0 59 eccpxas (1) eccpxase eccpxas2 eccpxas1 eccpxas0 pssxac1 pssxac0 pssxbd1 pssxbd0 59, 61 eccpxdel (1) pxrsen pxdc6 pxdc5 pxdc4 pxdc3 pxdc2 pxdc1 pxdc0 61 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used during eccp operation. note 1: generic term for all of the identical registers of this name for all enhanced ccp modules, where ?x? identifies the individual module (eccp1, eccp2 or eccp3). bit assignments and reset values for all registers of the same generic name are identical. 2: this register is not implemented on pic18f6527/6622/6627/6722 devices.
? 2004 microchip technology inc. preliminary ds39646b-page 205 pic18f8722 family 19.0 master synchronous serial port (mssp) module 19.1 master ssp (mssp) module overview the master synchronous serial port (mssp) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/d converters, etc. the mssp module can operate in one of two modes: serial peripheral interface (spi?) inter-integrated circuit (i 2 c?) - full master mode - slave mode (with general address call) the i 2 c interface supports the following modes in hardware: master mode multi-master mode slave mode all members of the pic18f8722 family have two mssp modules, designated as mssp1 and mssp2. each module operates independently of the other. 19.2 control registers each mssp module has three associated control regis- ters. these include a status register (sspxstat) and two control registers (sspxcon1 and sspxcon2). the use of these registers and their individual configuration bits differ significantly depending on whether the mssp module is operated in spi or i 2 c mode. additional details are provided under the individual sections. 19.3 spi mode the spi mode allows 8 bits of data to be synchronously transmitted and received simultaneously. all four modes of spi are supported. to accomplish communication, typically three pins are used: serial data out (sdox) ? rc5/sdo1 or rd4/sdo2 serial data in (sdix) ? rc4/sdi1/sda1 or rd5/sdi2/sda2 serial clock (sckx) ? rc3/sck1/scl1 or rd6/sck2/scl2 additionally, a fourth pin may be used when in a slave mode of operation: slave select (ssx ) ? rf7/ss1 or rd7/ss2 figure 19-1 shows the block diagram of the mssp module when operating in spi mode. figure 19-1: mssp block diagram (spi? mode) note: throughout this section, generic refer- ences to an mssp module in any of its operating modes may be interpreted as being equally applicable to mssp1 or mssp2. register names and module i/o signals use the generic designator ?x? to indicate the use of a numeral to distinguish a particular module when required. control bit names are not individuated. note: in devices with more than one mssp module, it is very important to pay close attention to sspcon register names. ssp1con1 and ssp1con2 control different operational aspects of the same module, while ssp1con1 and ssp2con1 control the same features for two different modules. ( ) read write internal data bus sspxsr reg sspm3:sspm0 bit 0 shift clock ss x control enable edge select clock select tmr2 output t osc prescaler 4, 16, 64 2 edge select 2 4 data to txx/rxx in sspxsr tris bit 2 smp:cke rc5 or rd4 sspxbuf reg rc4 or rd5 rf7 or rd7 rc3 or rd6 note: only port i/o names are used in this diagram for the sake of brevity. refer to the text for a full list of multiplexed functions.
pic18f8722 family ds39646b-page 206 preliminary ? 2004 microchip technology inc. 19.3.1 registers each mssp module has four registers for spi mode operation. these are: mssp control register 1 (sspxcon1) mssp status register (sspxstat) serial receive/transmit buffer register (sspxbuf) mssp shift register (sspxsr) ? not directly accessible sspxcon1 and sspxstat are the control and status registers in spi mode operation. the sspxcon1 register is readable and writable. the lower 6 bits of the sspxstat are read-only. the upper two bits of the sspxstat are read/write. sspxsr is the shift register used for shifting data in or out. sspxbuf is the buffer register to which data bytes are written to or read from. in receive operations, sspxsr and sspxbuf together create a double-buffered receiver. when sspxsr receives a complete byte, it is transferred to sspxbuf and the sspxif interrupt is set. during transmission, the sspxbuf is not double-buffered. a write to sspxbuf will write to both sspxbuf and sspxsr. register 19-1: sspxstat: msspx status register (spi? mode) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 bit 7 smp: sample bit spi master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode: smp must be cleared when spi is used in slave mode. bit 6 cke: spi clock select bit 1 = transmit occurs on transition from active to idle clock state 0 = transmit occurs on transition from idle to active clock state note: polarity of clock state is set by the ckp bit (sspxcon1<4>). bit 5 d/a : data/address bit used in i 2 c mode only. bit 4 p: stop bit used in i 2 c mode only. this bit is cleared when the mssp module is disabled, sspen is cleared. bit 3 s: start bit used in i 2 c mode only. bit 2 r/w : read/write information bit used in i 2 c mode only. bit 1 ua: update address bit used in i 2 c mode only. bit 0 bf: buffer full status bit (receive mode only) 1 = receive complete, sspxbuf is full 0 = receive not complete, sspxbuf is empty legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39646b-page 207 pic18f8722 family register 19-2: sspxcon1: msspx control register 1 (spi? mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 bit 7 wcol: write collision detect bit 1 = the sspxbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov: receive overflow indicator bit spi slave mode: 1 = a new byte is received while the sspxbuf register is still holding the previous data. in case of overflow, the data in sspxsr is lost. overflow can only occur in slave mode. the user must read the sspxbuf, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = no overflow note: in master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the sspxbuf register. bit 5 sspen: synchronous serial port enable bit 1 = enables serial port and configures sckx, sdox, sdix and ssx as serial port pins 0 = disables serial port and configures these pins as i/o port pins note: when enabled, these pins must be properly configured as input or output. bit 4 ckp: clock polarity select bit 1 = idle state for clock is a high level 0 = idle state for clock is a low level bit 3-0 sspm3:sspm0: synchronous serial port mode select bits 0101 = spi slave mode, clock = sckx pin, ss x pin control disabled, ss x can be used as i/o pin 0100 = spi slave mode, clock = sckx pin, ss x pin control enabled 0011 = spi master mode, clock = tmr2 output/2 0010 = spi master mode, clock = f osc /64 0001 = spi master mode, clock = f osc /16 0000 = spi master mode, clock = f osc /4 note: bit combinations not specifically listed here are either reserved or implemented in i 2 c mode only. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 208 preliminary ? 2004 microchip technology inc. 19.3.2 operation when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits (sspxcon1<5:0> and sspxstat<7:6>). these control bits allow the following to be specified: master mode (sckx is the clock output) slave mode (sckx is the clock input) clock polarity (idle state of sckx) data input sample phase (middle or end of data output time) clock edge (output data on rising/falling edge of sckx) clock rate (master mode only) slave select mode (slave mode only) each mssp module consists of a transmit/receive shift register (sspxsr) and a buffer register (sspxbuf). the sspxsr shifts the data in and out of the device, msb first. the sspxbuf holds the data that was written to the sspxsr until the received data is ready. once the 8 bits of data have been received, that byte is moved to the sspxbuf register. then, the buffer full detect bit, bf (sspxstat<0>) and the interrupt flag bit, sspxif, are set. this double-buffering of the received data (sspxbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspxbuf register during transmis- sion/reception of data will be ignored and the write collision detect bit, wcol (sspxcon1<7>), will be set. user software must clear the wcol bit so that it can be determined if the following write(s) to the sspxbuf register completed successfully. when the application software is expecting to receive valid data, the sspxbuf should be read before the next byte of data to transfer is written to the sspxbuf. the buffer full bit, bf (sspxstat<0>), indicates when sspxbuf has been loaded with the received data (transmission is complete). when the sspxbuf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. generally, the mssp interrupt is used to determine when the transmis- sion/reception has completed. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. example 19-1 shows the loading of the sspxbuf (sspxsr) for data transmission. the sspxsr is not directly readable or writable and can only be accessed by addressing the sspxbuf register. additionally, the sspxstat register indicates the various status conditions. example 19-1: loading the ssp1buf (ssp1sr) register loop btfss ssp1stat, bf ;has data been received (transmit complete)? bra loop ;no movf ssp1buf, w ;wreg reg = contents of ssp1buf movwf rxdata ;save in user ram, if data is meaningful movf txdata, w ;w reg = contents of txdata movwf ssp1buf ;new data to xmit
? 2004 microchip technology inc. preliminary ds39646b-page 209 pic18f8722 family 19.3.3 enabling spi i/o to enable the serial port, ssp enable bit, sspen (sspxcon1<5>), must be set. to reset or reconfigure spi mode, clear the sspen bit, reinitialize the sspxcon registers and then set the sspen bit. this configures the sdix, sdox, sckx and ssx pins as serial port pins. for the pins to behave as the serial port function, some must have their data direction bits (in the tris register) appropriately programmed as follows: sdix is automatically controlled by the spi module sdox must have the trisc<5> or trisd<4> bit cleared sckx (master mode) must have the trisc<3> or trisd<6>bit cleared sckx (slave mode) must have the trisc<3> or trisd<6> bit set ss x must have the trisf<7> or trisd<7> bit set any serial port function that is not desired may be overridden by programming the corresponding data direction (tris) register to the opposite value. 19.3.4 typical connection figure 19-2 shows a typical connection between two microcontrollers. the master controller (processor 1) initiates the data transfer by sending the sckx signal. data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock. both processors should be programmed to the same clock polarity (ckp), then both controllers would send and receive data at the same time. whether the data is meaningful (or dummy data) depends on the application software. this leads to three scenarios for data transmission: master sends data ? slave sends dummy data master sends data ? slave sends data master sends dummy data ? slave sends data figure 19-2: spi? master/slave connection serial input buffer (sspxbuf) shift register (sspxsr) msb lsb sdox sdix processor 1 sckx spi? master sspm3:sspm0 = 00xxb serial input buffer (sspxbuf) shift register (sspxsr) lsb msb sdix sdox processor 2 sckx spi? slave sspm3:sspm0 = 010xb serial clock
pic18f8722 family ds39646b-page 210 preliminary ? 2004 microchip technology inc. 19.3.5 master mode the master can initiate the data transfer at any time because it controls the sckx. the master determines when the slave (processor 1, figure 19-2) is to broadcast data by the software protocol. in master mode, the data is transmitted/received as soon as the sspxbuf register is written to. if the spi is only going to receive, the sdox output could be dis- abled (programmed as an input). the sspxsr register will continue to shift in the signal present on the sdix pin at the programmed clock rate. as each byte is received, it will be loaded into the sspxbuf register as if a normal received byte (interrupts and status bits appropriately set). this could be useful in receiver applications as a ?line activity monitor? mode. the clock polarity is selected by appropriately programming the ckp bit (sspxcon1<4>). this then, would give waveforms for spi communication as shown in figure 19-3, figure 19-5 and figure 19-6, where the msb is transmitted first. in master mode, the spi clock rate (bit rate) is user programmable to be one of the following: f osc /4 (or t cy ) f osc /16 (or 4 t cy ) f osc /64 (or 16 t cy ) timer2 output/2 this allows a maximum data rate (at 40 mhz) of 10.00 mbps. figure 19-3 shows the waveforms for master mode. when the cke bit is set, the sdox data is valid before there is a clock edge on sckx. the change of the input sample is shown based on the state of the smp bit. the time when the sspxbuf is loaded with the received data is shown. figure 19-3: spi? mode waveform (master mode) sckx (ckp = 0 sckx (ckp = 1 sckx (ckp = 0 sckx (ckp = 1 4 clock modes input sample input sample sdix bit 7 bit 0 sdox bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 sdix sspxif (smp = 1 ) (smp = 0 ) (smp = 1 ) cke = 1 ) cke = 0 ) cke = 1 ) cke = 0 ) (smp = 0 ) write to sspxbuf sspxsr to sspxbuf sdox bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (cke = 0 ) (cke = 1 ) next q4 cycle after q2 bit 0
? 2004 microchip technology inc. preliminary ds39646b-page 211 pic18f8722 family 19.3.6 slave mode in slave mode, the data is transmitted and received as the external clock pulses appear on sckx. when the last bit is latched, the sspxif interrupt flag bit is set. while in slave mode, the external clock is supplied by the external clock source on the sckx pin. this exter- nal clock must meet the minimum high and low times as specified in the electrical specifications. while in sleep mode, the slave can transmit/receive data. when a byte is received, the device can be configured to wake-up from sleep. 19.3.7 slave select synchronization the ssx pin allows a synchronous slave mode. the spi must be in slave mode with the ssx pin control enabled (sspxcon1<3:0> = 04h). when the ssx pin is low, transmission and reception are enabled and the sdox pin is driven. when the ssx pin goes high, the sdox pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. exter- nal pull-up/pull-down resistors may be desirable depending on the application. when the spi module resets, the bit counter is forced to ? 0 ?. this can be done by either forcing the ssx pin to a high level or clearing the sspen bit. to emulate two-wire communication, the sdox pin can be connected to the sdix pin. when the spi needs to operate as a receiver, the sdox pin can be configured as an input. this disables transmissions from the sdox. the sdix can always be left as an input (sdi function) since it cannot create a bus conflict. figure 19-4: slave synchronization waveform note 1: when the spi is in slave mode with s sx pin control enabled (sspxcon1<3:0> = 0100 ), the spi module will reset if the ssx pin is set to v dd . 2: if the spi is used in slave mode with cke set, then the ssx pin control must be enabled. sckx (ckp = 1 sckx (ckp = 0 input sample sdix bit 7 sdox bit 7 bit 6 bit 7 sspxif interrupt (smp = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) write to sspxbuf sspxsr to sspxbuf ssx flag bit 0 bit 7 bit 0 next q4 cycle after q2
pic18f8722 family ds39646b-page 212 preliminary ? 2004 microchip technology inc. figure 19-5: spi? mode waveform (slave mode with cke = 0 ) figure 19-6: spi? mode waveform (slave mode with cke = 1 ) sckx (ckp = 1 sckx (ckp = 0 input sample sdix bit 7 sdox bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspxif interrupt (smp = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) write to sspxbuf sspxsr to sspxbuf ssx flag optional next q4 cycle after q2 bit 0 sckx (ckp = 1 sckx (ckp = 0 input sample sdix bit 7 bit 0 sdox bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspxif interrupt (smp = 0 ) cke = 1 ) cke = 1 ) (smp = 0 ) write to sspxbuf sspxsr to sspxbuf ssx flag not optional next q4 cycle after q2
? 2004 microchip technology inc. preliminary ds39646b-page 213 pic18f8722 family 19.3.8 operation in power-managed modes in spi master mode, module clocks may be operating at a different speed than when in full power mode; in the case of the sleep mode, all clocks are halted. in idle modes, a clock is provided to the peripherals. that clock can be from the primary clock source, the secondary clock (timer1 oscillator) or the intosc source. see section 2.7 ?clock sources and oscillator switching? for additional information. in most cases, the speed that the master clocks spi data is not important; however, this should be evaluated for each system. if mssp interrupts are enabled, they can wake the con- troller from sleep mode, or one of the idle modes, when the master completes sending data. if an exit from sleep or idle mode is not desired, mssp interrupts should be disabled. if the sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the devices wakes. after the device returns to run mode, the module will resume transmitting and receiving data. in spi slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in any power-managed mode and data to be shifted into the spi trans- mit/receive shift register. when all 8 bits have been received, the mssp interrupt flag bit will be set and if enabled, will wake the device. 19.3.9 effects of a reset a reset disables the mssp module and terminates the current transfer. 19.3.10 bus mode compatibility table 19-1 shows the compatibility between the standard spi modes and the states of the ckp and cke control bits. table 19-1: spi? bus modes there is also an smp bit which controls when the data is sampled. 19.3.11 spi clock speed and module interactions because mssp1 and mssp2 are independent modules, they can operate simultaneously at different data rates. setting the sspm3:sspm0 bits of the sspxcon register determines the rate for the corresponding module. an exception is when both modules use timer2 as a time base in master mode. in this instance, any changes to the timer2 module?s operation will affect both mssp modules equally. if different bit rates are required for each module, the user should select one of the other three time base options for one of the modules. standard spi? mode terminology control bits state ckp cke 0, 0 0 1 0, 1 0 0 1, 0 1 1 1, 1 1 0
pic18f8722 family ds39646b-page 214 preliminary ? 2004 microchip technology inc. table 19-2: registers associated with spi operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 60 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 60 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 60 pir3 ssp2if bcl2if rc2if tx2if tmr4if ccp5if ccp4if ccp3if 60 pie3 ssp2ie bcl2ie rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie 60 ipr3 ssp2ip bcl2ip rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip 60 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 60 trisd trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 60 trisf trisf7 trisf6 trisf5 trisf 4 trisf3 trisf2 trisf1 trisf0 60 tmr2 timer2 register 58 pr2 timer2 period register 58 ssp1buf mssp1 receive buffer/transmit register 58 ssp1con1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 58 ssp1stat smp cke d/a p s r/w ua bf 58 ssp2buf mssp2 receive buffer/transmit register 61 ssp2con1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 61 ssp2stat smp cke d/a p s r/w ua bf 61 legend: shaded cells are not used by the mssp module in spi? mode.
? 2004 microchip technology inc. preliminary ds39646b-page 215 pic18f8722 family 19.4 i 2 c mode the mssp module in i 2 c mode fully implements all master and slave functions (including general call support) and provides interrupts on start and stop bits in hardware to determine a free bus (multi-master function). the mssp module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. two pins are used for data transfer: serial clock (sclx) ? rc3/sck1/scl1 or rd6/sck2/scl2 serial data (sdax) ? rc4/sdi1/sda1 or rd5/sdi2/sda2 the user must configure these pins as inputs by setting the associated tris bits. figure 19-7: mssp block diagram (i 2 c? mode) 19.4.1 registers the mssp module has six registers for i 2 c operation. these are: mssp control register 1 (sspxcon1) mssp control register 2 (sspxcon2) mssp status register (sspxstat) serial receive/transmit buffer register (sspxbuf) mssp shift register (sspxsr) ? not directly accessible mssp address register (sspxadd) sspxcon1, sspxcon2 and sspxstat are the control and status registers in i 2 c mode operation. the sspxcon1 and sspxcon2 registers are readable and writable. the lower 6 bits of the sspxstat are read-only. the upper two bits of the sspxstat are read/write. sspxsr is the shift register used for shifting data in or out. sspxbuf is the buffer register to which data bytes are written to or read from. sspxadd register holds the slave device address when the mssp is configured in i 2 c slave mode. when the mssp is configured in master mode, the lower seven bits of sspxadd act as the baud rate generator reload value. in receive operations, sspxsr and sspxbuf together create a double-buffered receiver. when sspxsr receives a complete byte, it is transferred to sspxbuf and the sspxif interrupt is set. during transmission, the sspxbuf is not double-buffered. a write to sspxbuf will write to both sspxbuf and sspxsr. read write sspxsr reg match detect sspxadd reg sspxbuf reg internal data bus addr match set, reset s, p bits (sspxstat reg) rc3 or rc4 or shift clock msb lsb note: only port i/o names are used in this diagram for the sake of brevity. refer to the text for a full list of multiplexed functions. rd6 rd5 start and stop bit detect
pic18f8722 family ds39646b-page 216 preliminary ? 2004 microchip technology inc. register 19-3: sspxstat: msspx status register (i 2 c? mode) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 bit 7 smp: slew rate control bit in master or slave mode: 1 = slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0 = slew rate control enabled for high-speed mode (400 khz) bit 6 cke: smbus select bit in master or slave mode: 1 = enable smbus specific inputs 0 = disable smbus specific inputs bit 5 d/a : data/address bit in master mode: reserved. in slave mode: 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p: stop bit 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last note: this bit is cleared on reset and when sspen is cleared. bit 3 s: start bit 1 = indicates that a start bit has been detected last 0 = start bit was not detected last note: this bit is cleared on reset and when sspen is cleared. bit 2 r/w : read/write information bit in slave mode: 1 = read 0 = write note: this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit or not ack bit. in master mode: 1 = transmit is in progress 0 = transmit is not in progress note: oring this bit with sen, rsen, pen, rcen or acken will indicate if the mssp is in active mode. bit 1 ua: update address bit (10-bit slave mode only) 1 = indicates that the user needs to update the address in the sspxadd register 0 = address does not need to be updated bit 0 bf: buffer full status bit in transmit mode: 1 = sspxbuf is full 0 = sspxbuf is empty in receive mode: 1 = sspxbuf is full (does not include the ack and stop bits) 0 = sspxbuf is empty (does not include the ack and stop bits) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39646b-page 217 pic18f8722 family register 19-4: sspxcon1: msspx control register 1 (i 2 c? mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 bit 7 wcol: write collision detect bit in master transmit mode: 1 = a write to the sspxbuf register was attempted while the i 2 c conditions were not valid for a transmission to be started (must be cleared in software) 0 = no collision in slave transmit mode: 1 = the sspxbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision in receive mode (master or slave modes): this is a ?don?t care? bit. bit 6 sspov: receive overflow indicator bit in receive mode: 1 = a byte is received while the sspxbuf register is still holding the previous byte (must be cleared in software) 0 = no overflow in transmit mode: this is a ?don?t care? bit in transmit mode. bit 5 sspen: synchronous serial port enable bit 1 = enables the serial port and configures the sdax and sclx pins as the serial port pins 0 = disables serial port and configures these pins as i/o port pins note: when enabled, the sdax and sclx pins must be configured as input. bit 4 ckp: sckx release control bit in slave mode: 1 = release clock 0 = holds clock low (clock stretch), used to ensure data setup time in master mode: unused in this mode. bit 3-0 sspm3:sspm0: synchronous serial port mode select bits 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1011 = i 2 c firmware controlled master mode (slave idle) 1000 = i 2 c master mode, clock = f osc /(4 * (sspxadd + 1)) 0111 = i 2 c slave mode, 10-bit address 0110 = i 2 c slave mode, 7-bit address bit combinations not specifically listed here are either reserved or implemented in spi? mode only. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 218 preliminary ? 2004 microchip technology inc. register 19-5: sspxcon2: msspx control register 2 (i 2 c? mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gcen ackstat ackdt acken (1) rcen (1) pen (1) rsen (1) sen (1) bit 7 bit 0 bit 7 gcen: general call enable bit (slave mode only) 1 = enable interrupt when a general call address (0000h) is received in the sspxsr 0 = general call address disabled bit 6 ackstat: acknowledge status bit (master transmit mode only) 1 = acknowledge was not received from slave 0 = acknowledge was received from slave bit 5 ackdt: acknowledge data bit (master receive mode only) 1 = not acknowledge 0 = acknowledge note: value that will be transmitted when the user initiates an acknowledge sequence at the end of a receive. bit 4 acken: acknowledge sequence enable bit (master receive mode only) (1) 1 = initiate acknowledge sequence on sdax and sclx pins and transmit ackdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle bit 3 rcen: receive enable bit (master mode only) (1) 1 = enables receive mode for i 2 c 0 = receive idle bit 2 pen: stop condition enable bit (master mode only) (1) 1 = initiate stop condition on sdax and sclx pins. automatically cleared by hardware. 0 = stop condition idle bit 1 rsen: repeated start condition enable bit (master mode only) (1) 1 = initiate repeated start condition on sdax and sclx pins. automatically cleared by hardware. 0 = repeated start condition idle bit 0 sen: start condition enable/stretch enable bit (1) in master mode: 1 = initiate start condition on sdax and sclx pins. automatically cleared by hardware. 0 = start condition idle in slave mode: 1 = clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = clock stretching is disabled note 1: for bits acken, rcen, pen, rsen, sen: if the i 2 c module is active, these bits may not be set (no spooling) and the sspxbuf may not be written (or writes to the sspxbuf are disabled). legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39646b-page 219 pic18f8722 family 19.4.2 operation the mssp module functions are enabled by setting mssp enable bit, sspen (sspxcon1<5>). the sspxcon1 register allows control of the i 2 c operation. four mode selection bits (sspxcon1<3:0>) allow one of the following i 2 c modes to be selected: i 2 c master mode, clock i 2 c slave mode (7-bit address) i 2 c slave mode (10-bit address) i 2 c slave mode (7-bit address) with start and stop bit interrupts enabled i 2 c slave mode (10-bit address) with start and stop bit interrupts enabled i 2 c firmware controlled master mode, slave is idle selection of any i 2 c mode with the sspen bit set forces the sclx and sdax pins to be open-drain, provided these pins are programmed as inputs by setting the appropriate trisc or trisd bits. to ensure proper operation of the module, pull-up resistors must be provided externally to the sclx and sdax pins. 19.4.3 slave mode in slave mode, the sclx and sdax pins must be configured as inputs (trisc<4:3> set). the mssp module will override the input state with the output data when required (slave-transmitter). the i 2 c slave mode hardware will always generate an interrupt on an address match. through the mode select bits, the user can also choose to interrupt on start and stop bits when an address is matched, or the data transfer after an address match is received, the hardware auto- matically will generate the acknowledge (ack ) pulse and load the sspxbuf register with the received value currently in the sspxsr register. any combination of the following conditions will cause the mssp module not to give this ack pulse: the buffer full bit, bf (sspxstat<0>), was set before the transfer was received. the overflow bit, sspov (sspxcon1<6>), was set before the transfer was received. in this case, the sspxsr register value is not loaded into the sspxbuf, but bit sspxif is set. the bf bit is cleared by reading the sspxbuf register, while bit sspov is cleared through software. the sclx clock input must have a minimum high and low for proper operation. the high and low times of the i 2 c specification, as well as the requirement of the mssp module, are shown in timing parameter 100 and parameter 101. 19.4.3.1 addressing once the mssp module has been enabled, it waits for a start condition to occur. following the start condition, the 8 bits are shifted into the sspxsr register. all incoming bits are sampled with the rising edge of the clock (sclx) line. the value of register sspxsr<7:1> is compared to the value of the sspxadd register. the address is compared on the falling edge of the eighth clock (sclx) pulse. if the addresses match and the bf and sspov bits are clear, the following events occur: 1. the sspxsr register value is loaded into the sspxbuf register. 2. the buffer full bit, bf, is set. 3. an ack pulse is generated. 4. the mssp interrupt flag bit, sspxif, is set (and interrupt is generated, if enabled) on the falling edge of the ninth sclx pulse. in 10-bit address mode, two address bytes need to be received by the slave. the five most significant bits (msbs) of the first address byte specify if this is a 10-bit address. bit r/w (sspxstat<2>) must specify a write so the slave device will receive the second address byte. for a 10-bit address, the first byte would equal ? 11110 a9 a8 0 ?, where ? a9 ? and ? a8 ? are the two msbs of the address. the sequence of events for 10-bit address is as follows, with steps 7 through 9 for the slave-transmitter: 1. receive first (high) byte of address (bits sspxif, bf and ua (sspxstat<1>) are set on address match). 2. update the sspxadd register with second (low) byte of address (clears bit ua and releases the sclx line). 3. read the sspxbuf register (clears bit bf) and clear flag bit sspxif. 4. receive second (low) byte of address (bits sspxif, bf and ua are set). 5. update the sspxadd register with the first (high) byte of address. if match releases sclx line, this will clear bit ua. 6. read the sspxbuf register (clears bit bf) and clear flag bit sspxif. 7. receive repeated start condition. 8. receive first (high) byte of address (bits sspxif and bf are set). 9. read the sspxbuf register (clears bit bf) and clear flag bit sspxif.
pic18f8722 family ds39646b-page 220 preliminary ? 2004 microchip technology inc. 19.4.3.2 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspxstat register is cleared. the received address is loaded into the sspxbuf register and the sdax line is held low (ack ). when the address byte overflow condition exists, then the no acknowledge (ack ) pulse is given. an overflow condition is defined as either bit bf (sspxstat<0>) is set, or bit sspov (sspxcon1<6>) is set. an mssp interrupt is generated for each data transfer byte. the interrupt flag bit, sspxif, must be cleared in software. the sspxstat register is used to determine the status of the byte. if sen is enabled (sspxcon2<0> = 1 ), sclx will be held low (clock stretch) following each data transfer. the clock must be released by setting bit, ckp (sspxcon1<4>). see section 19.4.4 ?clock stretching? for more detail. 19.4.3.3 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspxstat register is set. the received address is loaded into the sspxbuf register. the ack pulse will be sent on the ninth bit and pin sclx is held low regard- less of sen (see section 19.4.4 ?clock stretching? for more detail). by stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. the transmit data must be loaded into the sspxbuf register which also loads the sspxsr register. then pin sclx should be enabled by setting bit, ckp (sspxcon1<4>). the eight data bits are shifted out on the falling edge of the sclx input. this ensures that the sdax signal is valid during the sclx high time (figure 19-9). the ack pulse from the master-receiver is latched on the rising edge of the ninth sclx input pulse. if the sdax line is high (not ack ), then the data transfer is complete. in this case, when the ack is latched by the slave, the slave logic is reset (resets sspxstat register) and the slave monitors for another occurrence of the start bit. if the sdax line was low (ack ), the next transmit data must be loaded into the sspxbuf register. again, pin sclx must be enabled by setting bit ckp. an mssp interrupt is generated for each data transfer byte. the sspxif bit must be cleared in software and the sspxstat register is used to determine the status of the byte. the sspxif bit is set on the falling edge of the ninth clock pulse.
? 2004 microchip technology inc. preliminary ds39646b-page 221 pic18f8722 family figure 19-8: i 2 c? slave mode timing with sen = 0 (reception, 7-bit address) sdax sclx sspxif (pir1<3> or pir3<7>) bf (sspxstat<0>) sspov (sspxcon1<6>) s 12345678912345678912345 789 p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d1 d0 ack receiving data ack receiving data r/w = 0 ack receiving address cleared in software sspxbuf is read bus master terminates transfer sspov is set because sspxbuf is still full. ack is not sent. d2 6 ckp (ckp does not reset to ? 0 ? when sen = 0 )
pic18f8722 family ds39646b-page 222 preliminary ? 2004 microchip technology inc. figure 19-9: i 2 c? slave mode timing (transmission, 7-bit address) sdax sclx bf (sspxstat<0>) a6 a5 a4 a3 a2 a1 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 sspxbuf is written in software cleared in software data in sampled s ack transmitting data r/w = 0 ack receiving address a7 d7 9 1 d6 d5 d4 d3 d2 d1 d0 2 3 4 5 6 7 8 9 sspxbuf is written in software cleared in software from sspxif isr transmitting data d7 1 ckp p ack ckp is set in software ckp is set in software sclx held low while cpu responds to sspxif sspxif (pir1<3> or pir3<7>) from sspxif isr
? 2004 microchip technology inc. preliminary ds39646b-page 223 pic18f8722 family figure 19-10: i 2 c? slave mode timing with sen = 0 (reception, 10-bit address) sdax sclx sspxif (pir1<3> or pir3<7>) bf (sspxstat<0>) s 123456789 123456789 12345 789 p 1 1 1 1 0 a9a8 a7 a6a5 a4a3a2a1 a0 d7 d6d5d4d3 d1d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software d2 6 cleared in software receive second byte of address cleared by hardware when sspxadd is updated with low byte of address ua (sspxstat<1>) clock is held low until update of sspxadd has taken place ua is set indicating that the sspxadd needs to be updated ua is set indicating that sspxadd needs to be updated cleared by hardware when sspxadd is updated with high byte of address sspxbuf is written with contents of sspxsr dummy read of sspxbuf to clear bf flag ack ckp 12345 789 d7 d6 d5 d4 d3 d1 d0 receive data byte bus master terminates transfer d2 6 ack cleared in software cleared in software sspov (sspxcon1<6>) sspov is set because sspxbuf is still full. ack is not sent. (ckp does not reset to ? 0 ? when sen = 0 ) clock is held low until update of sspxadd has taken place
pic18f8722 family ds39646b-page 224 preliminary ? 2004 microchip technology inc. figure 19-11: i 2 c? slave mode timing (transmission, 10-bit address) sdax sclx sspxif (pir1<3> or pir3<7>) bf (sspxstat<0>) s 1234 5 6789 12345678 9 12345 7 89 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1 a0 1 1 1 1 0 a8 r/w = 1 ack ack r/w = 0 ack receive first byte of address cleared in software bus master terminates transfer a9 6 receive second byte of address cleared by hardware when sspxadd is updated with low byte of address ua (sspxstat<1>) clock is held low until update of sspxadd has taken place ua is set indicating that the sspxadd needs to be updated ua is set indicating that sspxadd needs to be updated cleared by hardware when sspxadd is updated with high byte of address. sspxbuf is written with contents of sspxsr dummy read of sspxbuf to clear bf flag receive first byte of address 12345 789 d7 d6 d5 d4 d3 d1 ack d2 6 transmitting data byte d0 dummy read of sspxbuf to clear bf flag sr cleared in software write of sspxbuf initiates transmit cleared in software completion of clears bf flag ckp (sspxcon1<4>) ckp is set in software ckp is automatically cleared in hardware, holding sclx low clock is held low until update of sspxadd has taken place data transmission clock is held low until ckp is set to ? 1 ? third address sequence bf flag is clear at the end of the
? 2004 microchip technology inc. preliminary ds39646b-page 225 pic18f8722 family 19.4.4 clock stretching both 7-bit and 10-bit slave modes implement automatic clock stretching during a transmit sequence. the sen bit (sspxcon2<0>) allows clock stretching to be enabled during receives. setting sen will cause the sclx pin to be held low at the end of each data receive sequence. 19.4.4.1 clock stretching for 7-bit slave receive mode (sen = 1 ) in 7-bit slave receive mode, on the falling edge of the ninth clock at the end of the ack sequence, if the bf bit is set, the ckp bit in the sspxcon1 register is automatically cleared, forcing the sclx output to be held low. the ckp being cleared to ? 0 ? will assert the sclx line low. the ckp bit must be set in the user?s isr before reception is allowed to continue. by holding the sclx line low, the user has time to service the isr and read the contents of the sspxbuf before the master device can initiate another receive sequence. this will prevent buffer overruns from occurring (see figure 19-13). 19.4.4.2 clock stretching for 10-bit slave receive mode (sen = 1 ) in 10-bit slave receive mode during the address sequence, clock stretching automatically takes place but ckp is not cleared. during this time, if the ua bit is set after the ninth clock, clock stretching is initiated. the ua bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the r/w bit cleared to ? 0 ?. the release of the clock line occurs upon updating sspxadd. clock stretching will occur on each data receive sequence as described in 7-bit mode. 19.4.4.3 clock stretching for 7-bit slave transmit mode the 7-bit slave transmit mode implements clock stretching by clearing the ckp bit after the falling edge of the ninth clock if the bf bit is clear. this occurs regardless of the state of the sen bit. the user?s isr must set the ckp bit before transmis- sion is allowed to continue. by holding the sclx line low, the user has time to service the isr and load the contents of the sspxbuf before the master device can initiate another transmit sequence (see figure 19-9). 19.4.4.4 clock stretching for 10-bit slave transmit mode in 10-bit slave transmit mode, clock stretching is controlled during the first two address sequences by the state of the ua bit, just as it is in 10-bit slave receive mode. the first two addresses are followed by a third address sequence which contains the high-order bits of the 10-bit address and the r/w bit set to ? 1 ?. after the third address sequence is performed, the ua bit is not set, the module is now configured in transmit mode and clock stretching is controlled by the bf flag as in 7-bit slave transmit mode (see figure 19-11). note 1: if the user reads the contents of the sspxbuf before the falling edge of the ninth clock, thus clearing the bf bit, the ckp bit will not be cleared and clock stretching will not occur. 2: the ckp bit can be set in software regardless of the state of the bf bit. the user should be careful to clear the bf bit in the isr before the next receive sequence in order to prevent an overflow condition. note: if the user polls the ua bit and clears it by updating the sspxadd register before the falling edge of the ninth clock occurs and if the user hasn?t cleared the bf bit by read- ing the sspxbuf register before that time, then the ckp bit will still not be asserted low. clock stretching on the basis of the state of the bf bit only occurs during a data sequence, not an address sequence. note 1: if the user loads the contents of sspxbuf, setting the bf bit before the falling edge of the ninth clock, the ckp bit will not be cleared and clock stretching will not occur. 2: the ckp bit can be set in software regardless of the state of the bf bit.
pic18f8722 family ds39646b-page 226 preliminary ? 2004 microchip technology inc. 19.4.4.5 clock synchronization and the ckp bit when the ckp bit is cleared, the sclx output is forced to ? 0 ?. however, clearing the ckp bit will not assert the sclx output low until the sclx output is already sam- pled low. therefore, the ckp bit will not assert the sclx line until an external i 2 c master device has already asserted the sclx line. the sclx output will remain low until the ckp bit is set and all other devices on the i 2 c bus have deasserted sclx. this ensures that a write to the ckp bit will not violate the minimum high time requirement for sclx (see figure 19-12). figure 19-12: clock synchronization timing sdax sclx dx ? 1 dx wr q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 sspxcon1 ckp master device deasserts clock master device asserts clock
? 2004 microchip technology inc. preliminary ds39646b-page 227 pic18f8722 family figure 19-13: i 2 c? slave mode timing with sen = 1 (reception, 7-bit address) sdax sclx sspxif (pir1<3> or pir3<7>) bf (sspxstat<0>) sspov (sspxcon1<6>) s 1 234 56 7 8 9 1 2345 67 89 1 23 45 7 89 p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d1 d0 ack receiving data ack receiving data r/w = 0 ack receiving address cleared in software sspxbuf is read bus master terminates transfer sspov is set because sspxbuf is still full. ack is not sent. d2 6 ckp ckp written to ? 1 ? in if bf is cleared prior to the falling edge of the 9th clock, ckp will not be reset to ? 0 ? and no clock stretching will occur software clock is held low until ckp is set to ? 1 ? clock is not held low because buffer full bit is clear prior to falling edge of 9th clock clock is not held low because ack = 1 bf is set after falling edge of the 9th clock, ckp is reset to ? 0 ? and clock stretching occurs
pic18f8722 family ds39646b-page 228 preliminary ? 2004 microchip technology inc. figure 19-14: i 2 c? slave mode timing with sen = 1 (reception, 10-bit address) sdax sclx sspxif (pir1<3> or pir3<7>) bf (sspxstat<0>) s 123456789 123456789 12345 789 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1 a0 d7d6d5d4d3 d1d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software d2 6 cleared in software receive second byte of address cleared by hardware when sspxadd is updated with low byte of address after falling edge ua (sspxstat<1>) clock is held low until update of sspxadd has taken place ua is set indicating that the sspxadd needs to be updated ua is set indicating that sspxadd needs to be updated cleared by hardware when sspxadd is updated with high byte of address after falling edge sspxbuf is written with contents of sspxsr dummy read of sspxbuf to clear bf flag ack ckp 12345 789 d7 d6 d5 d4 d3 d1 d0 receive data byte bus master terminates transfer d2 6 ack cleared in software cleared in software sspov (sspxcon1<6>) ckp written to ? 1 ? note: an update of the sspxadd register before the falling edge of the ninth clock will have no effect on ua and ua will remain set. note: an update of the sspxadd register before the falling edge of the ninth clock will have no effect on ua and ua will remain set. in software clock is held low until update of sspxadd has taken place of ninth clock of ninth clock sspov is set because sspxbuf is still full. ack is not sent. dummy read of sspxbuf to clear bf flag clock is held low until ckp is set to ? 1 ? clock is not held low because ack = 1
? 2004 microchip technology inc. preliminary ds39646b-page 229 pic18f8722 family 19.4.5 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually determines which device will be the slave addressed by the master. the exception is the general call address which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is one of eight addresses reserved for specific purposes by the i 2 c protocol. it consists of all ? 0 ?s with r/w = 0 . the general call address is recognized when the general call enable bit, gcen, is enabled (sspxcon2<7> set). following a start bit detect, 8 bits are shifted into the sspxsr and the address is compared against the sspxadd. it is also compared to the general call address and fixed in hardware. if the general call address matches, the sspxsr is transferred to the sspxbuf, the bf flag bit is set (eighth bit) and on the falling edge of the ninth bit (ack bit), the sspxif interrupt flag bit is set. when the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the sspxbuf. the value can be used to determine if the address was device specific or a general call address. in 10-bit mode, the sspxadd is required to be updated for the second half of the address to match and the ua bit is set (sspxstat<1>). if the general call address is sampled when the gcen bit is set, while the slave is configured in 10-bit address mode, then the second half of the address is not necessary, the ua bit will not be set and the slave will begin receiving data after the acknowledge (figure 19-15). figure 19-15: slave mode general call address sequence (7 or 10-bit address mode) sdax sclx s sspxif bf (sspxstat<0>) sspov (sspxcon1<6>) cleared in software sspxbuf is read r/w = 0 ack general call address address is compared to general call address gcen (sspxcon2<7>) receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack , set interrupt ? 0 ? ? 1 ?
pic18f8722 family ds39646b-page 230 preliminary ? 2004 microchip technology inc. 19.4.6 master mode master mode is enabled by setting and clearing the appropriate sspm bits in sspxcon1 and by setting the sspen bit. in master mode, the sclx and sdax lines are manipulated by the mssp hardware if the tris bits are set. master mode of operation is supported by interrupt generation on the detection of the start and stop con- ditions. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle, with both the s and p bits clear. in firmware controlled master mode, user code conducts all i 2 c bus operations based on start and stop bit conditions. once master mode is enabled, the user has six options. 1. assert a start condition on sdax and sclx. 2. assert a repeated start condition on sdax and sclx. 3. write to the sspxbuf register initiating transmission of data/address. 4. configure the i 2 c port to receive data. 5. generate an acknowledge condition at the end of a received byte of data. 6. generate a stop condition on sdax and sclx. the following events will cause the ssp interrupt flag bit, sspxif, to be set (and ssp interrupt, if enabled): start condition stop condition data transfer byte transmitted/received acknowledge transmit repeated start figure 19-16: mssp block diagram (i 2 c? master mode) note: the mssp module, when configured in i 2 c master mode, does not allow queueing of events. for instance, the user is not allowed to initiate a start condition and immediately write the sspxbuf register to initiate transmission before the start condi- tion is complete. in this case, the sspxbuf will not be written to and the wcol bit will be set, indicating that a write to the sspxbuf did not occur. read write sspxsr start bit, stop bit, sspxbuf internal data bus set/reset s, p (sspxstat), wcol (sspxcon1) shift clock msb lsb sdax acknowledge generate stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv sclx sclx in bus collision sdax in receive enable clock cntl clock arbitrate/wcol detect (hold off clock source) sspxadd<6:0> baud set sspxif, bclxif reset ackstat, pen (sspxcon2) rate generator sspm3:sspm0 start bit detect
? 2004 microchip technology inc. preliminary ds39646b-page 231 pic18f8722 family 19.4.6.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since the repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sdax, while sclx outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic ? 0 ?. serial data is transmitted 8 bits at a time. after each byte is transmit- ted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the r/w bit. in this case, the r/w bit will be logic ? 1 ?. thus, the first byte transmitted is a 7-bit slave address, followed by a ? 1 ? to indicate the receive bit. serial data is received via sdax, while sclx outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions indicate the beginning and end of transmission. the baud rate generator used for the spi mode operation is used to set the sclx clock frequency for either 100 khz, 400 khz or 1 mhz i 2 c operation. see section 19.4.7 ?baud rate? for more detail. a typical transmit sequence would go as follows: 1. the user generates a start condition by setting the start enable bit, sen (sspxcon2<0>). 2. sspxif is set. the mssp module will wait the required start time before any other operation takes place. 3. the user loads the sspxbuf with the slave address to transmit. 4. address is shifted out the sdax pin until all 8 bits are transmitted. 5. the mssp module shifts in the ack bit from the slave device and writes its value into the sspxcon2 register (sspxcon2<6>). 6. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspxif bit. 7. the user loads the sspxbuf with eight bits of data. 8. data is shifted out the sdax pin until all 8 bits are transmitted. 9. the mssp module shifts in the ack bit from the slave device and writes its value into the sspxcon2 register (sspxcon2<6>). 10. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspxif bit. 11. the user generates a stop condition by setting the stop enable bit, pen (sspxcon2<2>). 12. interrupt is generated once the stop condition is complete.
pic18f8722 family ds39646b-page 232 preliminary ? 2004 microchip technology inc. 19.4.7 baud rate in i 2 c master mode, the baud rate generator (brg) reload value is placed in the lower 7 bits of the sspxadd register (figure 19-17). when a write occurs to sspxbuf, the baud rate generator will automatically begin counting. the brg counts down to ? 0 ? and stops until another reload has taken place. the brg count is decremented twice per instruction cycle (t cy ) on the q2 and q4 clocks. in i 2 c master mode, the brg is reloaded automatically. once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ack ), the internal clock will automatically stop counting and the sclx pin will remain in its last state. table 19-3 demonstrates clock rates based on instruction cycles and the brg value loaded into sspxadd. 19.4.7.1 baud rate and module interdependence because mssp1 and mssp2 are independent, they can operate simultaneously in i 2 c master mode at different baud rates. this is done by using different brg reload values for each module. because this mode derives its basic clock source from the system clock, any changes to the clock will affect both modules in the same proportion. it may be possible to change one or both baud rates back to a previous value by changing the brg reload value. figure 19-17: baud rate generator block diagram table 19-3: i 2 c? clock rate w/brg sspm3:sspm0 brg down counter clko f osc /4 sspxadd<6:0> sspm3:sspm0 sclx reload control reload f osc f cy f cy *2 brg value f scl (2 rollovers of brg) 40 mhz 10 mhz 20 mhz 18h 400 khz (1) 40 mhz 10 mhz 20 mhz 1fh 312.5 khz 40 mhz 10 mhz 20 mhz 63h 100 khz 16 mhz 4 mhz 8 mhz 09h 400 khz (1) 16 mhz 4 mhz 8 mhz 0ch 308 khz 16 mhz 4 mhz 8 mhz 27h 100 khz 4 mhz 1 mhz 2 mhz 02h 333 khz (1) 4 mhz 1 mhz 2 mhz 09h 100 khz 4 mhz 1 mhz 2 mhz 00h 1 mhz (1) note 1: the i 2 c interface does not conform to the 400 khz i 2 c specification (which applies to rates greater than 100 khz) in all details, but may be used with care where higher rates are required by the application.
? 2004 microchip technology inc. preliminary ds39646b-page 233 pic18f8722 family 19.4.7.2 clock arbitration clock arbitration occurs when the master, during any receive, transmit or repeated start/stop condition, deasserts the sclx pin (sclx allowed to float high). when the sclx pin is allowed to float high, the baud rate generator (brg) is suspended from counting until the sclx pin is actually sampled high. when the sclx pin is sampled high, the baud rate generator is reloaded with the contents of sspxadd<6:0> and begins counting. this ensures that the sclx high time will always be at least one brg rollover count in the event that the clock is held low by an external device (figure 19-18). figure 19-18: baud rate generator timing with clock arbitration sdax sclx sclx deasserted but slave holds dx ? 1 dx brg sclx is sampled high, reload takes place and brg starts its count 03h 02h 01h 00h (hold off) 03h 02h reload brg value sclx low (clock arbitration) sclx allowed to transition high brg decrements on q2 and q4 cycles
pic18f8722 family ds39646b-page 234 preliminary ? 2004 microchip technology inc. 19.4.8 i 2 c master mode start condition timing to initiate a start condition, the user sets the start enable bit, sen (sspxcon2<0>). if the sdax and sclx pins are sampled high, the baud rate generator is reloaded with the contents of sspxadd<6:0> and starts its count. if sclx and sdax are both sampled high when the baud rate generator times out (t brg ), the sdax pin is driven low. the action of the sdax being driven low while sclx is high is the start condi- tion and causes the s bit (sspxstat<3>) to be set. following this, the baud rate generator is reloaded with the contents of sspxadd<6:0> and resumes its count. when the baud rate generator times out (t brg ), the sen bit (sspxcon2<0>) will be auto- matically cleared by hardware; the baud rate generator is suspended, leaving the sdax line held low and the start condition is complete. 19.4.8.1 wcol status flag if the user writes the sspxbuf when a start sequence is in progress, the wcol bit is set and the contents of the buffer are unchanged (the write doesn?t occur). figure 19-19: first start bit timing note: if at the beginning of the start condition, the sdax and sclx pins are already sam- pled low, or if during the start condition, the sclx line is sampled low before the sdax line is driven low, a bus collision occurs, the bus collision interrupt flag, bclxif, is set, the start condition is aborted and the i 2 c module is reset into its idle state. note: because queueing of events is not allowed, writing to the lower 5 bits of sspxcon2 is disabled until the start condition is complete. sdax sclx s t brg 1st bit 2nd bit t brg sdax = 1 , at completion of start bit, sclx = 1 write to sspxbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here set s bit (sspxstat<3>) and sets sspxif bit
? 2004 microchip technology inc. preliminary ds39646b-page 235 pic18f8722 family 19.4.9 i 2 c master mode repeated start condition timing a repeated start condition occurs when the rsen bit (sspxcon2<1>) is programmed high and the i 2 c logic module is in the idle state. when the rsen bit is set, the sclx pin is asserted low. when the sclx pin is sampled low, the baud rate generator is loaded with the contents of sspxadd<5:0> and begins counting. the sdax pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate generator times out, if sdax is sampled high, the sclx pin will be deasserted (brought high). when sclx is sampled high, the baud rate generator is reloaded with the contents of sspxadd<6:0> and begins count- ing. sdax and sclx must be sampled high for one t brg . this action is then followed by assertion of the sdax pin (sdax = 0 ) for one t brg while sclx is high. following this, the rsen bit (sspxcon2<1>) will be automatically cleared and the baud rate generator will not be reloaded, leaving the sdax pin held low. as soon as a start condition is detected on the sdax and sclx pins, the s bit (sspxstat<3>) will be set. the sspxif bit will not be set until the baud rate generator has timed out. immediately following the sspxif bit getting set, the user may write the sspxbuf with the 7-bit address in 7-bit mode or the default first address in 10-bit mode. after the first eight bits are transmitted and an ack is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). 19.4.9.1 wcol status flag if the user writes the sspxbuf when a repeated start sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). figure 19-20: repeated start condition waveform note 1: if rsen is programmed while any other event is in progress, it will not take effect. 2: a bus collision during the repeated start condition occurs if: sdax is sampled low when sclx goes from low-to-high. sclx goes low before sdax is asserted low. this may indicate that another master is attempting to transmit a data ? 1 ?. note: because queueing of events is not allowed, writing of the lower 5 bits of sspxcon2 is disabled until the repeated start condition is complete. sdax sclx sr = repeated start write to sspxcon2 write to sspxbuf occurs here on falling edge of ninth clock, end of xmit at completion of start bit, hardware clears rsen bit 1st bit s bit set by hardware t brg sdax = 1 , sdax = 1 , sclx (no change). sclx = 1 occurs here: and sets sspxif rsen bit set by hardware t brg t brg t brg t brg
pic18f8722 family ds39646b-page 236 preliminary ? 2004 microchip technology inc. 19.4.10 i 2 c master mode transmission transmission of a data byte, a 7-bit address, or the other half of a 10-bit address, is accomplished by sim- ply writing a value to the sspxbuf register. this action will set the buffer full flag bit, bf and allow the baud rate generator to begin counting and start the next transmission. each bit of address/data will be shifted out onto the sdax pin after the falling edge of sclx is asserted (see data hold time specification parameter 106). sclx is held low for one baud rate generator rollover count (t brg ). data should be valid before sclx is released high (see data setup time specification parameter 107). when the sclx pin is released high, it is held that way for t brg . the data on the sdax pin must remain stable for that duration and some hold time after the next falling edge of sclx. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf flag is cleared and the master releases sdax. this allows the slave device being addressed to respond with an ack bit during the ninth bit time if an address match occurred, or if data was received properly. the status of ack is written into the ackdt bit on the falling edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit, ackstat, is cleared. if not, the bit is set. after the ninth clock, the sspxif bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the sspxbuf, leaving sclx low and sdax unchanged (figure 19-21). after the write to the sspxbuf, each bit of the address will be shifted out on the falling edge of sclx until all seven address bits and the r/w bit are completed. on the falling edge of the eighth clock, the master will deassert the sdax pin, allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock, the master will sample the sdax pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the ackstat status bit (sspxcon2<6>). following the falling edge of the ninth clock transmission of the address, the sspxif is set, the bf flag is cleared and the baud rate generator is turned off until another write to the sspxbuf takes place, holding sclx low and allowing sdax to float. 19.4.10.1 bf status flag in transmit mode, the bf bit (sspxstat<0>) is set when the cpu writes to sspxbuf and is cleared when all 8 bits are shifted out. 19.4.10.2 wcol status flag if the user writes the sspxbuf when a transmit is already in progress (i.e., sspxsr is still shifting out a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write doesn?t occur) after 2t cy after the sspxbuf write. if sspxbuf is rewritten within 2 t cy , the wcol bit is set and sspxbuf is updated. this may result in a corrupted transfer. the user should verify that the wcol bit is clear after each write to sspxbuf to ensure the transfer is correct. in all cases, wcol must be cleared in software. 19.4.10.3 ackstat status flag in transmit mode, the ackstat bit (sspxcon2<6>) is cleared when the slave has sent an acknowledge (ack = 0 ) and is set when the slave does not acknowl- edge (ack = 1 ). a slave sends an acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 19.4.11 i 2 c master mode reception master mode reception is enabled by programming the receive enable bit, rcen (sspxcon2<3>). the baud rate generator begins counting and on each rollover, the state of the sclx pin changes (high-to-low/low-to-high) and data is shifted into the sspxsr. after the falling edge of the eighth clock, the receive enable flag is automatically cleared, the con- tents of the sspxsr are loaded into the sspxbuf, the bf flag bit is set, the sspxif flag bit is set and the baud rate generator is suspended from counting, holding sclx low. the mssp is now in idle state awaiting the next command. when the buffer is read by the cpu, the bf flag bit is automatically cleared. the user can then send an acknowledge bit at the end of reception by setting the acknowledge sequence enable bit, acken (sspxcon2<4>). 19.4.11.1 bf status flag in receive operation, the bf bit is set when an address or data byte is loaded into sspxbuf from sspxsr. it is cleared when the sspxbuf register is read. 19.4.11.2 sspov status flag in receive operation, the sspov bit is set when 8 bits are received into the sspxsr and the bf flag bit is already set from a previous reception. 19.4.11.3 wcol status flag if the user writes the sspxbuf when a receive is already in progress (i.e., sspxsr is still shifting in a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write doesn?t occur). note: the mssp module must be in an inactive state before the rcen bit is set or the rcen bit will be disregarded.
? 2004 microchip technology inc. preliminary ds39646b-page 237 pic18f8722 family figure 19-21: i 2 c? master mode waveform (transmission, 7 or 10-bit address) sdax sclx sspxif bf (sspxstat<0>) sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared in software service routine sspxbuf is written in software from mssp interrupt after start condition, sen cleared by hardware s sspxbuf written with 7-bit address and r/w , start transmit sclx held low while cpu responds to sspxif sen = 0 of 10-bit address write sspxcon2<0> (sen = 1 ), start condition begins from slave, clear ackstat bit sspxcon2<6> ackstat in sspxcon2 = 1 cleared in software sspxbuf written pen r/w cleared in software
pic18f8722 family ds39646b-page 238 preliminary ? 2004 microchip technology inc. figure 19-22: i 2 c? master mode waveform (reception, 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sdax sclx 12 3 4 5 6 7 8 9 12 3 4 5 678 9 1234 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w = 0 transmit address to slave sspxif bf ack is not sent write to sspxcon2<0> (sen = 1 ), write to sspxbuf occurs here, ack from slave master configured as a receiver by programming sspxcon2<3> (rcen = 1 ) pen bit = 1 written here data shifted in on falling edge of clk cleared in software start xmit sen = 0 sspov sdax = 0 , sclx = 1 , while cpu (sspxstat<0>) ack cleared in software cleared in software set sspxif interrupt at end of receive set p bit (sspxstat<4>) and sspxif ack from master, set sspxif at end set sspxif interrupt at end of acknowledge sequence set sspxif interrupt at end of acknow- ledge sequence of receive set acken, start acknowledge sequence, sdax = ackdt = 1 rcen cleared automatically rcen = 1 , start next receive write to sspxcon2<4> to start acknowledge sequence, sdax = ackdt (sspxcon2<5>) = 0 rcen cleared automatically responds to sspxif acken begin start condition cleared in software sdax = ackdt = 0 last bit is shifted into sspxsr and contents are unloaded into sspxbuf cleared in software sspov is set because sspxbuf is still full
? 2004 microchip technology inc. preliminary ds39646b-page 239 pic18f8722 family 19.4.12 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken (sspxcon2<4>). when this bit is set, the sclx pin is pulled low and the contents of the acknowledge data bit are presented on the sdax pin. if the user wishes to generate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ) and the sclx pin is deasserted (pulled high). when the sclx pin is sampled high (clock arbitration), the baud rate generator counts for t brg . the sclx pin is then pulled low. following this, the acken bit is auto- matically cleared, the baud rate generator is turned off and the mssp module then goes into an inactive state (figure 19-23). 19.4.12.1 wcol status flag if the user writes the sspxbuf when an acknowledge sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). 19.4.13 stop condition timing a stop bit is asserted on the sdax pin at the end of a receive/transmit by setting the stop sequence enable bit, pen (sspxcon2<2>). at the end of a receive/transmit, the sclx line is held low after the falling edge of the ninth clock. when the pen bit is set, the master will assert the sdax line low. when the sdax line is sampled low, the baud rate generator is reloaded and counts down to ? 0 ?. when the baud rate generator times out, the sclx pin will be brought high and one t brg (baud rate generator rollover count) later, the sdax pin will be deasserted. when the sdax pin is sampled high while sclx is high, the p bit (sspxstat<4>) is set. a t brg later, the pen bit is cleared and the sspxif bit is set (figure 19-24). 19.4.13.1 wcol status flag if the user writes the sspxbuf when a stop sequence is in progress, then the wcol bit is set and the contents of the buffer are unchanged (the write doesn?t occur). figure 19-23: acknowledge sequence waveform figure 19-24: stop cond ition receive or transmit mode note: t brg = one baud rate generator period. sdax sclx sspxif set at acknowledge sequence starts here, write to sspxcon2, acken automatically cleared cleared in t brg t brg the end of receive 8 acken = 1 , ackdt = 0 d0 9 sspxif software sspxif set at the end of acknowledge sequence cleared in software ack sclx sdax sdax asserted low before rising edge of clock write to sspxcon2, set pen falling edge of sclx = 1 for t brg , followed by sdax = 1 for t brg 9th clock sclx brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sdax sampled high. p bit (sspxstat<4>) is set. t brg to setup stop condition ack p t brg pen bit (sspxcon2<2>) is cleared by hardware and the sspxif bit is set
pic18f8722 family ds39646b-page 240 preliminary ? 2004 microchip technology inc. 19.4.14 sleep operation while in sleep mode, the i 2 c module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from sleep (if the mssp interrupt is enabled). 19.4.15 effects of a reset a reset disables the mssp module and terminates the current transfer. 19.4.16 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit (sspxstat<4>) is set, or the bus is idle, with both the s and p bits clear. when the bus is busy, enabling the mssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sdax line must be monitored for arbitration to see if the signal level is the expected output level. this check is performed in hardware with the result placed in the bclxif bit. the states where arbitration can be lost are: address transfer data transfer a start condition a repeated start condition an acknowledge condition 19.4.17 multi -master communication, bus collision and bus arbitration multi-master mode support is achieved by bus arbitra- tion. when the master outputs address/data bits onto the sdax pin, arbitration takes place when the master outputs a ? 1 ? on sdax, by letting sdax float high and another master asserts a ? 0 ?. when the sclx pin floats high, data should be stable. if the expected data on sdax is a ? 1 ? and the data sampled on the sdax pin = 0 , then a bus collision has taken place. the master will set the bus collision interrupt flag, bclxif and reset the i 2 c port to its idle state (figure 19-25). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf flag is cleared, the sdax and sclx lines are deasserted and the sspxbuf can be written to. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. if a start, repeated start, stop or acknowledge condition was in progress when the bus collision occurred, the con- dition is aborted, the sdax and sclx lines are deasserted and the respective control bits in the sspxcon2 register are cleared. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. the master will continue to monitor the sdax and sclx pins. if a stop condition occurs, the sspxif bit will be set. a write to the sspxbuf will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the deter- mination of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspxstat register, or the bus is idle and the s and p bits are cleared. figure 19-25: bus collision timing for transmit and acknowledge sdax sclx bclxif sdax released sdax line pulled low by another source sample sdax. while sclx is high, data doesn?t match what is driven bus collision has occurred. set bus collision interrupt (bclxif) by the master. by master data changes while sclx = 0
? 2004 microchip technology inc. preliminary ds39646b-page 241 pic18f8722 family 19.4.17.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sdax or sclx are sampled low at the beginning of the start condition (figure 19-26). b) sclx is sampled low before sdax is asserted low (figure 19-27). during a start condition, both the sdax and the sclx pins are monitored. if the sdax pin is already low, or the sclx pin is already low, then all of the following occur: the start condition is aborted, the bclxif flag is set and the mssp module is reset to its inactive state (figure 19-26). the start condition begins with the sdax and sclx pins deasserted. when the sdax pin is sampled high, the baud rate generator is loaded from sspxadd<6:0> and counts down to ? 0 ?. if the sclx pin is sampled low while sdax is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ? 1 ? during the start condition. if the sdax pin is sampled low during this count, the brg is reset and the sdax line is asserted early (figure 19-28). if, however, a ? 1 ? is sampled on the sdax pin, the sdax pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to ? 0 ?. if the sclx pin is sampled as ? 0 ? during this time, a bus collision does not occur. at the end of the brg count, the sclx pin is asserted low. figure 19-26: bus collision during st art condition (sdax only) note: the reason that bus collision is not a factor during a start condition is that no two bus masters can assert a start condition at the exact same time. therefore, one master will always assert sdax before the other. this condition does not cause a bus colli- sion because the two masters must be allowed to arbitrate the first address following the start condition. if the address is the same, arbitration must be allowed to continue into the data portion, repeated start or stop conditions. sdax sclx sen sdax sampled low before sdax goes low before the sen bit is set. s bit and sspxif set because mssp module reset into idle state. sen cleared automatically because of bus collision. s bit and sspxif set because set sen, enable start condition if sdax = 1 , sclx = 1 sdax = 0 , sclx = 1 . bclxif s sspxif sdax = 0 , sclx = 1 . sspxif and bclxif are cleared in software sspxif and bclxif are cleared in software set bclxif, start condition. set bclxif.
pic18f8722 family ds39646b-page 242 preliminary ? 2004 microchip technology inc. figure 19-27: bus collision d uring start condition (sclx = 0 ) figure 19-28: brg reset due to sdax arbitr ation during start condition sdax sclx sen bus collision occurs. set bclxif. sclx = 0 before sdax = 0 , set sen, enable start sequence if sdax = 1 , sclx = 1 t brg t brg sdax = 0 , sclx = 1 bclxif s sspxif interrupt cleared in software bus collision occurs. set bclxif. sclx = 0 before brg time-out, ? 0 ?? 0 ? ? 0 ? ? 0 ? sdax sclx sen set s less than t brg t brg sdax = 0 , sclx = 1 bclxif s sspxif s interrupts cleared in software set sspxif sdax = 0 , sclx = 1 , sclx pulled low after brg time-out set sspxif ? 0 ? sdax pulled low by other master. reset brg and assert sdax. set sen, enable start sequence if sdax = 1 , sclx = 1
? 2004 microchip technology inc. preliminary ds39646b-page 243 pic18f8722 family 19.4.17.2 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sdax when sclx goes from low level to high level. b) sclx goes low before sdax is asserted low, indicating that another master is attempting to transmit a data ? 1 ?. when the user deasserts sdax and the pin is allowed to float high, the brg is loaded with sspxadd<6:0> and counts down to ? 0 ?. the sclx pin is then deasserted and when sampled high, the sdax pin is sampled. if sdax is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ? 0 ?, figure 19-29). if sdax is sampled high, the brg is reloaded and begins counting. if sdax goes from high-to-low before the brg times out, no bus collision occurs because no two masters can assert sdax at exactly the same time. if sclx goes from high-to-low before the brg times out and sdax has not already been asserted, a bus collision occurs. in this case, another master is attempting to transmit a data ? 1 ? during the repeated start condition (see figure 19-30). if, at the end of the brg time-out, both sclx and sdax are still high, the sdax pin is driven low and the brg is reloaded and begins counting. at the end of the count, regardless of the status of the sclx pin, the sclx pin is driven low and the repeated start condition is complete. figure 19-29: bus collision during a repeat ed start condition (case 1) figure 19-30: bus collision during repeat ed start condition (case 2) sdax sclx rsen bclxif s sspxif sample sdax when sclx goes high. if sdax = 0 , set bclxif and release sdax and sclx. cleared in software ? 0 ? ? 0 ? sdax sclx bclxif rsen s sspxif interrupt cleared in software sclx goes low before sdax, set bclxif. release sdax and sclx. t brg t brg ? 0 ?
pic18f8722 family ds39646b-page 244 preliminary ? 2004 microchip technology inc. 19.4.17.3 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sdax pin has been deasserted and allowed to float high, sdax is sampled low after the brg has timed out. b) after the sclx pin is deasserted, sclx is sampled low before sdax goes high. the stop condition begins with sdax asserted low. when sdax is sampled low, the sclx pin is allowed to float. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspxadd<6:0> and counts down to ? 0 ?. after the brg times out, sdax is sampled. if sdax is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data ? 0 ? (figure 19-31). if the sclx pin is sampled low before sdax is allowed to float high, a bus collision occurs. this is another case of another master attempting to drive a data ? 0 ? (figure 19-32). figure 19-31: bus collision during a stop condition (case 1) figure 19-32: bus collision during a stop condition (case 2) sdax sclx bclxif pen p sspxif t brg t brg t brg sdax asserted low sdax sampled low after t brg , set bclxif ? 0 ? ? 0 ? sdax sclx bclxif pen p sspxif t brg t brg t brg assert sdax sclx goes low before sdax goes high, set bclxif ? 0 ? ? 0 ?
? 2004 microchip technology inc. preliminary ds39646b-page 245 pic18f8722 family table 19-4: registers associated with i 2 c? operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 60 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 60 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 60 pir2 oscfif cmif ? eeif bcl1if hlvdif tmr3if ccp2if 60 pie2 oscfie cmie ? eeie bcl1ie hlvdie tmr3ie ccp2ie 60 ipr2 oscfip cmip ? eeip bcl1ip hlvdip tmr3ip ccp2ip 60 pir3 ssp2if bcl2if rc2if tx2if tmr4if ccp5if ccp4if ccp3if 60 pie3 ssp2ie bcl2ie rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie 60 ipr3 ssp2ip bcl2ip rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip 60 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 60 trisd trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 60 ssp1buf mssp1 receive buffer/transmit register 58 ssp2buf mssp2 receive buffer/transmit register 61 ssp1add mssp1 address register in i 2 c slave mode. mssp1 baud rate reload register in i 2 c master mode. 58 ssp2add mssp2 address register in i 2 c slave mode. mssp2 baud rate reload register in i 2 c master mode. 61 tmr2 timer2 register 58 pr2 timer2 period register 58 ssp1con1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 58 ssp1con2 gcen ackstat ackdt acken rcen pen rsen sen 58 ssp1stat smp cke d/a psr/w ua bf 58 ssp2con1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 61 ssp2con2 gcen ackstat ackdt acken rcen pen rsen sen 61 ssp2stat smp cke d/a psr/w ua bf 61 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the mssp module in i 2 c mode.
pic18f8722 family ds39646b-page 246 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39646b-page 247 pic18f8722 family 20.0 enhanced universal synchronous receiver transmitter (eusart) the enhanced universal synchronous asynchronous receiver transmitter (eusart) module is one of two serial i/o modules. (generically, the usart is also known as a serial communications interface or sci.) the eusart can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as crt terminals and personal computers. it can also be configured as a half- duplex synchronous system that can communicate with peripheral devices, such as a/d or d/a integrated circuits, serial eeproms, etc. the enhanced usart module implements additional features, including automatic baud rate detection and calibration, automatic wake-up on sync break recep- tion and 12-bit break character transmit. these make it ideally suited for use in local interconnect network bus (lin bus) systems. the eusart can be configured in the following modes: asynchronous (full duplex) with: - auto-wake-up on character reception - auto-baud calibration - 12-bit break character transmission synchronous ? master (half duplex) with selectable clock polarity synchronous ? slave (half duplex) with selectable clock polarity the pins of eusart1 and eusart2 are multiplexed with the functions of portc (rc6/tx1/ck1 and rc7/ rx1/dt1) and portg (rg1/tx2/ck2 and rg2/rx2/ dt2), respectively. in order to configure these pins as an eusart: for eusart1: - bit spen (rcsta1<7>) must be set (= 1 ) - bit trisc<7> must be set (= 1 ) - bit trisc<6> must be cleared (= 0 ) for asynchronous and synchronous master modes - bit trisc<6> must be set (= 1 ) for synchronous slave mode for eusart2: - bit spen (rcsta2<7>) must be set (= 1 ) - bit trisg<2> must be set (= 1 ) - bit trisg<1> must be cleared (= 0 ) for asynchronous and synchronous master modes - bit trisc<6> must be set (= 1 ) for synchronous slave mode the operation of each enhanced usart module is controlled through three registers: transmit status and control (txstax) receive status and control (rcstax) baud rate control (baudconx) these are detailed on the following pages in register 20-1, register 20-2 and register 20-3, respectively. note: the eusart control will automatically reconfigure the pin from input to output as needed. note: throughout this section, references to register and bit names that may be associ- ated with a specific eusart module are referred to generically by the use of ?x? in place of the specific module number. thus, ?rcstax? might refer to the receive status register for either eusart1 or eusart2
pic18f8722 family ds39646b-page 248 preliminary ? 2004 microchip technology inc. register 20-1: txstax: transmit status and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-1 r/w-0 csrc tx9 txen sync sendb brgh trmt tx9d bit 7 bit 0 bit 7 csrc: clock source select bit asynchronous mode: don?t care. synchronous mode: 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9: 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen: transmit enable bit 1 = transmit enabled 0 = transmit disabled note: sren/cren overrides txen in sync mode. bit 4 sync: eusart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 sendb: send break character bit asynchronous mode: 1 = send sync break on next transmission (cleared by hardware upon completion) 0 = sync break transmission completed synchronous mode: don?t care. bit 2 brgh: high baud rate select bit asynchronous mode: 1 = high speed 0 = low speed synchronous mode: unused in this mode. bit 1 trmt: transmit shift register status bit 1 = tsrx empty 0 = tsrx full bit 0 tx9d: 9th bit of transmit data can be address/data bit or a parity bit. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39646b-page 249 pic18f8722 family register 20-2: rcstax: receive status and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-x spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 bit 7 spen: serial port enable bit 1 = serial port enabled (configures rxx/dtx and txx/ckx pins as serial port pins) 0 = serial port disabled (held in reset) bit 6 rx9: 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren: single receive enable bit asynchronous mode: don?t care. synchronous mode ? m aster: 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode ? s lave: don?t care. bit 4 cren: continuous receive enable bit asynchronous mode: 1 = enables receiver 0 = disables receiver synchronous mode: 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden: address detect enable bit asynchronous mode 9-bit (rx9 = 1 ): 1 = enables address detection, enables interrupt and loads the receive buffer when rsrx<8> is set 0 = disables address detection, all bytes are received and ninth bit can be used as parity bit asynchronous mode 9-bit (rx9 = 0 ): don?t care. bit 2 ferr: framing error bit 1 = framing error (can be updated by reading rcregx register and receiving next valid byte) 0 = no framing error bit 1 oerr: overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: 9th bit of received data this can be address/data bit or a parity bit and must be calculated by user firmware. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 250 preliminary ? 2004 microchip technology inc. register 20-3: baudconx: baud rate control register r/w-0 r-1 u-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 abdovf rcidl ? sckp brg16 ? wue abden bit 7 bit 0 bit 7 abdovf : auto-baud acquisition rollover status bit 1 = a brg rollover has occurred during auto-baud rate detect mode (must be cleared in software) 0 = no brg rollover has occurred bit 6 rcidl : receive operation idle status bit 1 = receive operation is inactive 0 = receive operation is active bit 5 unimplemented: read as ? 0 ? bit 4 sckp : synchronous clock polarity select bit asynchronous mode: unused in this mode. synchronous mode: 1 = idle state for clock (ckx) is a high level 0 = idle state for clock (ckx) is a low level bit 3 brg16: 16-bit baud rate register enable bit 1 = 16-bit baud rate generator ? spbrghx and spbrgx 0 = 8-bit baud rate generator ? spbrgx only (compatible mode), spbrghx value ignored bit 2 unimplemented: read as ? 0 ? bit 1 wue: wake-up enable bit asynchronous mode: 1 = eusart will continue to sample the rxx pin ? interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = rxx pin not monitored or rising edge detected synchronous mode: unused in this mode. bit 0 abden : auto-baud detect enable bit asynchronous mode: 1 = enable baud rate measurement on the next character. requires reception of a sync field (55h); cleared in hardware upon completion. 0 = baud rate measurement disabled or completed synchronous mode: unused in this mode. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39646b-page 251 pic18f8722 family 20.1 baud rate generator (brg) the brg is a dedicated 8-bit or 16-bit generator that supports both the asynchronous and synchronous modes of the eusart. by default, the brg operates in 8-bit mode; setting the brg16 bit (baudconx<3>) selects 16-bit mode. the spbrghx:spbrgx register pair controls the period of a free running timer. in asynchronous mode, bits brgh (txstax<2>) and brg16 (baudconx<3>) also control the baud rate. in synchronous mode, brgh is ignored. table 20-1 shows the formula for computation of the baud rate for different eusart modes which only apply in master mode (internally generated clock). given the desired baud rate and f osc , the nearest integer value for the spbrghx:spbrgx registers can be calculated using the formulas in table 20-1. from this, the error in baud rate can be determined. an example calculation is shown in example 20-1. typical baud rates and error values for the various asynchro- nous modes are shown in table 20-2. it may be advantageous to use the high baud rate (brgh = 1 ) or the 16-bit brg to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. writing a new value to the spbrghx:spbrgx regis- ters causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer overflow before outputting the new baud rate. 20.1.1 operation in power-managed modes the device clock is used to generate the desired baud rate. when one of the power-managed modes is entered, the new clock source may be operating at a different frequency. this may require an adjustment to the value in the spbrgx register pair. 20.1.2 sampling the data on the rxx pin (either rc7/rx1/dt1 or rg2/ rx2/dt2) is sampled three times by a majority detect circuit to determine if a high or a low level is present at the rxx pin. table 20-1: baud rate formulas configuration bits brg/eusart mode baud rate formula sync brg16 brgh 000 8-bit/asynchronous f osc /[64 (n + 1)] 001 8-bit/asynchronous f osc /[16 (n + 1)] 010 16-bit/asynchronous 011 16-bit/asynchronous f osc /[4 (n + 1)] 10x 8-bit/synchronous 11x 16-bit/synchronous legend: x = don?t care, n = value of spbrghx:spbrgx register pair
pic18f8722 family ds39646b-page 252 preliminary ? 2004 microchip technology inc. example 20-1: calculating baud rate error table 20-2: registers associated with baud rate generator for a device with f osc of 16 mhz, desired baud rate of 9600, asynchronous mode, 8-bit brg: desired baud rate = f osc /(64 ([spbrghx:spbrgx] + 1)) solving for spbrghx:spbrgx: x=((f osc /desired baud rate)/64) ? 1 = ((16000000/9600)/64) ? 1 = [25.042] = 25 calculated baud rate = 16000000/(64 (25 + 1)) = 9615 error = (calculated baud rate ? desi red baud rate)/de sired baud rate = (9615 ? 9600)/9600 = 0.16% name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page txstax csrc tx9 txen sync sendb brgh trmt tx9d 59 rcstax spen rx9 sren cren adden ferr oerr rx9d 59 baudconx abdovf rcidl ? sckp brg16 ? wue abden 61 spbrghx eusartx baud rate generator register high byte 59 spbrgx eusartx baud rate generator register low byte 59 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the brg.
? 2004 microchip technology inc. preliminary ds39646b-page 253 pic18f8722 family table 20-3: baud rates for asynchronous modes baud rate (k) sync = 0 , brgh = 0 , brg16 = 0 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3???????????? 1.2 ? ? ? 1.221 1.73 255 1.202 0.16 129 1201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 ? ? ? 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 ? ? ? 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 ? ? ? baud rate (k) sync = 0 , brgh = 0 , brg16 = 0 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.16 207 300 -0.16 103 300 -0.16 51 1.2 1.202 0.16 51 1201 -0.16 25 1201 -0.16 12 2.4 2.404 0.16 25 2403 -0.16 12 ? ? ? 9.6 8.929 -6.99 6 ? ? ? ? ? ? 19.2 20.833 8.51 2 ? ? ? ? ? ? 57.6 62.500 8.51 0 ? ? ? ? ? ? 115.2 62.500 -45.75 0 ? ? ? ? ? ? baud rate (k) sync = 0 , brgh = 1 , brg16 = 0 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3???????????? 1.2???????????? 2.4 ? ? ? ? ? ? 2.441 1.73 255 2403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 ? ? ? baud rate (k) sync = 0 , brgh = 1 , brg16 = 0 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 ? ? ? ? ? ? 300 -0.16 207 1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51 2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25 9.6 9.615 0.16 25 9615 -0.16 12 ? ? ? 19.2 19.231 0.16 12 ? ? ? ? ? ? 57.6 62.500 8.51 3 ? ? ? ? ? ? 115.2 125.000 8.51 1 ? ? ? ? ? ?
pic18f8722 family ds39646b-page 254 preliminary ? 2004 microchip technology inc. baud rate (k) sync = 0 , brgh = 0 , brg16 = 1 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 300 -0.04 1665 1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1201 -0.16 415 2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2403 -0.16 207 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 ? ? ? baud rate (k) sync = 0 , brgh = 0 , brg16 = 1 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.04 832 300 -0.16 415 300 -0.16 207 1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51 2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25 9.6 9.615 0.16 25 9615 -0.16 12 ? ? ? 19.2 19.231 0.16 12 ? ? ? ? ? ? 57.6 62.500 8.51 3 ? ? ? ? ? ? 115.2 125.000 8.51 1 ? ? ? ? ? ? baud rate (k) sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 300 -0.01 6665 1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1200 -0.04 1665 2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2400 -0.04 832 9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9615 -0.16 207 19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19230 -0.16 103 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117647 -2.12 16 baud rate (k) sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.01 3332 300 -0.04 1665 300 -0.04 832 1.2 1.200 0.04 832 1201 -0.16 415 1201 -0.16 207 2.4 2.404 0.16 415 2403 -0.16 207 2403 -0.16 103 9.6 9.615 0.16 103 9615 -0.16 51 9615 -0.16 25 19.2 19.231 0.16 51 19230 -0.16 25 19230 -0.16 12 57.6 58.824 2.12 16 55555 3.55 8 ? ? ? 115.2 111.111 -3.55 8 ? ? ? ? ? ? table 20-3: baud rates for asynchronous modes (continued)
? 2004 microchip technology inc. preliminary ds39646b-page 255 pic18f8722 family 20.1.3 auto-baud rate detect the enhanced usart module supports the automatic detection and calibration of baud rate. this feature is active only in asynchronous mode and while the wue bit is clear. the automatic baud rate measurement sequence (figure 20-1) begins whenever a start bit is received and the abden bit is set. the calculation is self-averaging. in the auto-baud rate detect (abd) mode, the clock to the brg is reversed. rather than the brg clocking the incoming rxx signal, the rxx signal is timing the brg. in abd mode, the internal baud rate generator is used as a counter to time the bit period of the incoming serial byte stream. once the abden bit is set, the state machine will clear the brg and look for a start bit. the auto-baud rate detect must receive a byte with the value 55h (ascii ?u?, which is also the lin bus sync character) in order to calculate the proper bit rate. the measurement is taken over both a low and a high bit time in order to minimize any effects caused by asymmetry of the incoming signal. after a start bit, the spbrgx begins counting up, using the preselected clock source on the first rising edge of rxx. after eight bits on the rxx pin or the fifth rising edge, an accumulated value totalling the proper brg period is left in the spbrghx:spbrgx register pair. once the 5th edge is seen (this should correspond to the stop bit), the abden bit is automatically cleared. if a rollover of the brg occurs (an overflow from ffffh to 0000h), the event is trapped by the abdovf status bit (baudconx<7>). it is set in hardware by brg roll- overs and can be set or cleared by the user in software. abd mode remains active after rollover events and the abden bit remains set (figure 20-2). while calibrating the baud rate period, the brg regis- ters are clocked at 1/8th the preconfigured clock rate. note that the brg clock will be configured by the brg16 and brgh bits. independent of the brg16 bit setting, both the spbrgx and spbrghx will be used as a 16-bit counter. this allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the spbrghx register. refer to table 20-4 for counter clock rates to the brg. while the abd sequence takes place, the eusart state machine is held in idle. the rcxif interrupt is set once the fifth rising edge on rxx is detected. the value in the rcregx needs to be read to clear the rcxif interrupt. the contents of rcregx should be discarded. table 20-4: brg counter clock rates 20.1.3.1 abd and eusart transmission since the brg clock is reversed during abd acquisi- tion, the eusart transmitter cannot be used during abd. this means that whenever the abden bit is set, txregx cannot be written to. users should also ensure that abden does not become set during a transmit sequence. failing to do this may result in unpredictable eusart operation. note 1: if the wue bit is set with the abden bit, auto-baud rate detection will occur on the byte following the break character. 2: it is up to the user to determine that the incoming character baud rate is within the range of the selected brg clock source. some combinations of oscillator frequency and eusart baud rates are not possible due to bit error rates. overall system timing and communication baud rates must be taken into consideration when using the auto-baud rate detection feature. brg16 brgh brg counter clock 00 f osc /512 01 f osc /128 10 f osc /128 11 f osc /32 note: during the abd sequence, spbrgx and spbrghx are both used as a 16-bit counter, independent of brg16 setting.
pic18f8722 family ds39646b-page 256 preliminary ? 2004 microchip technology inc. figure 20-1: automatic baud rate calculation figure 20-2: brg overflow sequence brg value rxx pin abden bit rcxif bit bit 0 bit 1 (interrupt) read rcregx brg clock start auto-cleared set by user xxxxh 0000h edge #1 bit 2 bit 3 edge #2 bit 4 bit 5 edge #3 bit 6 bit 7 edge #4 stop bit edge #5 001ch note: the abd sequence requires the eusart module to be configured in asynchronous mode and wue = 0 . spbrgx xxxxh 1ch spbrghx xxxxh 00h start bit 0 xxxxh 0000h 0000h ffffh brg clock abden bit rxx pin abdovf bit brg value
? 2004 microchip technology inc. preliminary ds39646b-page 257 pic18f8722 family 20.2 eusart asynchronous mode the asynchronous mode of operation is selected by clearing the sync bit (txstax<4>). in this mode, the eusart uses standard non-return-to-zero (nrz) format (one start bit, eight or nine data bits and one stop bit). the most common data format is 8 bits. an on-chip dedicated 8-bit/16-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. the eusart transmits and receives the lsb first. the eusart?s transmitter and receiver are functionally independent, but use the same data format and baud rate. the baud rate generator produces a clock, either x16 or x64 of the bit shift rate depending on the brgh and brg16 bits (txstax<2> and baudconx<3>). parity is not supported by the hardware, but can be implemented in software and stored as the 9th data bit. when operating in asynchronous mode, the eusart module consists of the following important elements: baud rate generator sampling circuit asynchronous transmitter asynchronous receiver auto-wake-up on sync break character 12-bit break character transmit auto-baud rate detection 20.2.1 eusart asynchronous transmitter the eusart transmitter block diagram is shown in figure 20-3. the heart of the transmitter is the transmit (serial) shift register (tsrx). the shift register obtains its data from the read/write transmit buffer register, txregx. the txregx register is loaded with data in software. the tsrx register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsrx is loaded with new data from the txregx register (if available). once the txregx register transfers the data to the tsrx register (occurs in one t cy ), the txregx register is empty and the txxif flag bit (pir1<4>) is set. this interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, txxie (pie1<4>). txxif will be set regardless of the state of txxie; it cannot be cleared in software. txxif is also not cleared immediately upon loading txregx, but becomes valid in the second instruction cycle following the load instruction. polling txxif immediately following a load of txregx will return invalid results. while txxif indicates the status of the txregx regis- ter, another bit, trmt (txstax<1>), shows the status of the tsrx register. trmt is a read-only bit which is set when the tsrx register is empty. no interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the tsrx register is empty. to set up an asynchronous transmission: 1. initialize the spbrghx:spbrgx registers for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, set enable bit txxie. 4. if 9-bit transmission is desired, set transmit bit tx9. can be used as address/data bit. 5. enable the transmission by setting bit txen which will also set bit txxif. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. load data to the txregx register (starts transmission). 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. note 1: the tsrx register is not mapped in data memory so it is not available to the user. 2: flag bit txxif is set when enable bit txen is set.
pic18f8722 family ds39646b-page 258 preliminary ? 2004 microchip technology inc. figure 20-3: eusart transmit block diagram figure 20-4: asynchronous transmission figure 20-5: asynchronous transmission (back to back) txxif txxie interrupt txen baud rate clk spbrgx baud rate generator tx9d msb lsb data bus txregx register tsrx register (8) 0 tx9 trmt spen txx pin pin buffer and control 8 ? ? ? spbrghx brg16 word 1 word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txregx brg output (shift clock) txx (pin) txxif bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) 1 t cy stop bit word 1 transmit shift reg. write to txregx brg output (shift clock) txx (pin) txxif bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. 1 t cy 1 t cy start bit
? 2004 microchip technology inc. preliminary ds39646b-page 259 pic18f8722 family table 20-5: registers associated with asynchronous transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 60 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 60 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 60 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 60 trisg ? ? ? trisg4 trisg3 trisg2 trisg1 trisg0 60 rcstax spen rx9 sren cren adden ferr oerr rx9d 59 txregx eusartx transmit register 59 txstax csrc tx9 txen sync sendb brgh trmt tx9d 59 baudconx abdovf rcidl ? sckp brg16 ? wue abden 61 spbrghx eusartx baud rate generator register high byte 61 spbrgx eusartx baud rate generator register low byte 59 legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous transmission.
pic18f8722 family ds39646b-page 260 preliminary ? 2004 microchip technology inc. 20.2.2 eusart asynchronous receiver the receiver block diagram is shown in figure 20-6. the data is received on the rxx pin and drives the data recovery block. the data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at f osc . this mode would typically be used in rs-232 systems. to set up an asynchronous reception: 1. initialize the spbrghx:spbrgx registers for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, set enable bit rcxie. 4. if 9-bit reception is desired, set bit rx9. 5. enable the reception by setting bit cren. 6. flag bit, rcxif, will be set when reception is complete and an interrupt will be generated if enable bit, rcxie, was set. 7. read the rcstax register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcregx register. 9. if any error occurred, clear the error by clearing enable bit cren. 10. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. 20.2.3 setting up 9-bit mode with address detect this mode would typically be used in rs-485 systems. to set up an asynchronous reception with address detect enable: 1. initialize the spbrghx:spbrgx registers for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if interrupts are required, set the rcen bit and select the desired priority level with the rcxip bit. 4. set the rx9 bit to enable 9-bit reception. 5. set the adden bit to enable address detect. 6. enable reception by setting the cren bit. 7. the rcxif bit will be set when reception is complete. the interrupt will be acknowledged if the rcxie and gie bits are set. 8. read the rcstax register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. read rcregx to determine if the device is being addressed. 10. if any error occurred, clear the cren bit. 11. if the device has been addressed, clear the adden bit to allow all received data into the receive buffer and interrupt the cpu. figure 20-6: eusart receiv e block diagram x64 baud rate clk baud rate generator rxx pin buffer and control spen data recovery cren oerr ferr rsrx register msb lsb rx9d rcregx register fifo interrupt rcxif rcxie data bus 8 64 16 or stop start (8) 7 1 0 rx9 ? ? ? spbrgx spbrghx brg16 or 4
? 2004 microchip technology inc. preliminary ds39646b-page 261 pic18f8722 family figure 20-7: asynchronous reception table 20-6: registers associated with asynchronous reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 60 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 60 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 60 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 60 trisg ? ? ? trisg4 trisg3 trisg2 trisg1 trisg0 60 rcstax spen rx9 sren cren adden ferr oerr rx9d 59 rcregx eusartx receive register 59 txstax csrc tx9 txen sync sendb brgh trmt tx9d 59 baudconx abdovf rcidl ? sckp brg16 ? wue abden 61 spbrghx eusartx baud rate generator register high byte 61 spbrgx eusartx baud rate generator register low byte 59 legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous reception. start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit start bit bit 7/8 stop bit rxx (pin) rcv buffer reg rcv shift reg read rcv buffer reg rcregx rcxif (interrupt flag) oerr bit cren word 1 rcregx word 2 rcregx stop bit note: this timing diagram shows three words appearing on the rxx input. the rcregx (receive buffer) is read after the third word causing the oerr (overrun) bit to be set.
pic18f8722 family ds39646b-page 262 preliminary ? 2004 microchip technology inc. 20.2.4 auto-wake-up on sync break character during sleep mode, all clocks to the eusart are suspended. because of this, the baud rate generator is inactive and a proper byte reception cannot be performed. the auto-wake-up feature allows the controller to wake-up due to activity on the rxx/dtx line, while the eusart is operating in asynchronous mode. the auto-wake-up feature is enabled by setting the wue bit (baudconx<1>). once set, the typical receive sequence on rxx/dtx is disabled and the eusart remains in an idle state, monitoring for a wake-up event independent of the cpu mode. a wake-up event consists of a high-to-low transition on the rxx/dtx line. (this coincides with the start of a sync break or a wake-up signal character for the lin protocol.) following a wake-up event, the module generates an rcxif interrupt. the interrupt is generated synchro- nously to the q clocks in normal operating modes (figure 20-8) and asynchronously, if the device is in sleep mode (figure 20-9). the interrupt condition is cleared by reading the rcregx register. the wue bit is automatically cleared once a low-to- high transition is observed on the rxx line following the wake-up event. at this point, the eusart module is inactive and returns to normal operation. this signals to the user that the sync break event is over. 20.2.4.1 special considerations using auto-wake-up since auto-wake-up functions by sensing rising edge transitions on rxx/dtx, information with any state changes before the stop bit may signal a false end-of- character and cause data or framing errors. to work properly, therefore, the initial character in the transmis- sion must be all ? 0 ?s. this can be 00h (8 bytes) for standard rs-232 devices or 000h (12 bits) for lin bus. oscillator start-up time must also be considered, especially in applications using oscillators with longer start-up intervals (i.e., xt or hs mode). the sync break (or wake-up signal) character must be of sufficient length and be followed by a sufficient interval to allow enough time for the selected oscillator to start and provide proper initialization of the eusart. 20.2.4.2 special considerations using the wue bit the timing of wue and rcxif events may cause some confusion when it comes to determining the validity of received data. as noted, setting the wue bit places the eusart in an inactive state. the wake-up event causes a receive interrupt by setting the rcxif bit. the wue bit is cleared after this when a rising edge is seen on rxx/dtx. the interrupt condition is then cleared by reading the rcregx register. ordinarily, the data in rcregx will be dummy data and should be discarded. the fact that the wue bit has been cleared (or is still set) and the rcxif flag is set should not be used as an indicator of the integrity of the data in rcregx. users should consider implementing a parallel method in firmware to verify received data integrity. to assure that no actual data is lost, check the rcidl bit to verify that a receive operation is not in process. if a receive operation is not occurring, the wue bit may then be set just prior to entering the sleep mode. figure 20-8: auto-wake-up bit (wue) timings during normal operation figure 20-9: auto-wake-up bit (wue) timings during sleep q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit (1) rxx/dtx line rcxif note 1: the eusart remains inactive while the wue bit is set. bit set by user cleared due to user read of rcregx auto-cleared q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit (2) rxx/dtx line rcxif cleared due to user read of rcregx sleep command executed note 1: if the wake-up event requires long oscillator warm-up time, the auto-clear of the wue bit can occur before the oscillator is re ady. this sequence should not depend on the presence of q clocks. 2: the eusart remains inactive while the wue bit is set. sleep ends note 1 auto-cleared bit set by user
? 2004 microchip technology inc. preliminary ds39646b-page 263 pic18f8722 family 20.2.5 break character sequence the eusart module has the capability of sending the special break character sequences that are required by the lin bus standard. the break character transmit consists of a start bit, followed by twelve ? 0 ? bits and a stop bit. the frame break character is sent whenever the sendb and txen bits (txstax<3> and txstax<5>) are set while the transmit shift register is loaded with data. note that the value of data written to txregx will be ignored and all ? 0 ?s will be transmitted. the sendb bit is automatically reset by hardware after the corresponding stop bit is sent. this allows the user to preload the transmit fifo with the next transmit byte following the break character (typically, the sync character in the lin specification). note that the data value written to the txregx for the break character is ignored. the write simply serves the purpose of initiating the proper sequence. the trmt bit indicates when the transmit operation is active or idle, just as it does during normal transmis- sion. see figure 20-10 for the timing of the break character sequence. 20.2.5.1 break and sync transmit sequence the following sequence will send a message frame header made up of a break, followed by an auto-baud sync byte. this sequence is typical of a lin bus master. 1. configure the eusart for the desired mode. 2. set the txen and sendb bits to set up the break character. 3. load the txregx with a dummy character to initiate transmission (the value is ignored). 4. write ?55h? to txregx to load the sync character into the transmit fifo buffer. 5. after the break has been sent, the sendb bit is reset by hardware. the sync character now transmits in the preconfigured mode. when the txregx becomes empty, as indicated by the txxif, the next data byte can be written to txregx. 20.2.6 receiving a break character the enhanced usart module can receive a break character in two ways. the first method forces configuration of the baud rate at a frequency of 9/13 the typical speed. this allows for the stop bit transition to be at the correct sampling loca- tion (13 bits for break versus start bit and 8 data bits for typical data). the second method uses the auto-wake-up feature described in section 20.2.4 ?auto-wake-up on sync break character? . by enabling this feature, the eusart will sample the next two transitions on rxx/ dtx, cause an rcxif interrupt and receive the next data byte followed by another interrupt. note that following a break character, the user will typically want to enable the auto-baud rate detect feature. for both methods, the user can set the abd bit once the txxif interrupt is observed. figure 20-10: send break character sequence write to txregx brg output (shift clock) start bit bit 0 bit 1 bit 11 stop bit break txxif bit (transmit buffer reg. empty flag) txx (pin) trmt bit (transmit shift reg. empty flag) sendb (transmit shift reg. empty flag) sendb sampled here auto-cleared dummy write
pic18f8722 family ds39646b-page 264 preliminary ? 2004 microchip technology inc. 20.3 eusart synchronous master mode the synchronous master mode is entered by setting the csrc bit (txstax<7>). in this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit sync (txstax<4>). in addition, enable bit spen (rcstax<7>) is set in order to configure the txx and rxx pins to ckx (clock) and dtx (data) lines, respectively. the master mode indicates that the processor trans- mits the master clock on the ckx line. clock polarity is selected with the sckp bit (baudconx<4>); setting sckp sets the idle state on ckx as high, while clearing the bit sets the idle state as low. this option is provided to support microwire devices with this module. 20.3.1 eusart synchronous master transmission the eusart transmitter block diagram is shown in figure 20-3. the heart of the transmitter is the transmit (serial) shift register (tsrx). the shift register obtains its data from the read/write transmit buffer register, txregx. the txregx register is loaded with data in software. the tsrx register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsrx is loaded with new data from the txregx (if available). once the txregx register transfers the data to the tsrx register (occurs in one t cy ), the txregx is empty and the txxif flag bit is set. the interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, txxie. txxif is set regardless of the state of enable bit txxie; it cannot be cleared in software. it will reset only when new data is loaded into the txregx register. while flag bit txxif indicates the status of the txregx register, another bit, trmt (txstax<1>), shows the status of the tsrx regist er. trmt is a read-only bit which is set when the tsrx is empty. no interrupt logic is tied to this bit, so the user must poll this bit in order to determine if the tsrx register is empty. the tsrx is not mapped in data memory so it is not available to the user. to set up a synchronous master transmission: 1. initialize the spbrghx:spbrgx registers for the appropriate baud rate. set or clear the brg16 bit, as required, to achieve the desired baud rate. 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. if interrupts are desired, set enable bit txxie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txregx register. 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 20-11: synchronous transmission bit 0 bit 1 bit 7 word 1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bit 2 bit 0 bit 1 bit 7 dtx ckx pin write to txregx reg txxif bit (interrupt flag) txen bit ? 1 ? ? 1 ? word 2 trmt bit write word 1 write word 2 note: sync master mode, spbrgx = 0 , continuous transmission of two 8-bit words. ckx pin (sckp = 0 ) (sckp = 1 )
? 2004 microchip technology inc. preliminary ds39646b-page 265 pic18f8722 family figure 20-12: synchronous transmis sion (through txen) table 20-7: registers associated with synchronous master transmission dtx pin ckx pin write to txregx reg txxif bit trmt bit bit 0 bit 1 bit 2 bit 6 bit 7 txen bit name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 60 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 60 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 60 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 60 trisg ? ? ? trisg4 trisg3 trisg2 trisg1 trisg0 60 rcstax spen rx9 sren cren adden ferr oerr rx9d 59 txregx eusartx transmit register 59 txstax csrc tx9 txen sync sendb brgh trmt tx9d 59 baudconx abdovf rcidl ?sckpbrg16 ? wue abden 61 spbrghx eusartx baud rate generator register high byte 61 spbrgx eusartx baud rate generator register low byte 59 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master transmission.
pic18f8722 family ds39646b-page 266 preliminary ? 2004 microchip technology inc. 20.3.2 eusart synchronous master reception once synchronous mode is selected, reception is enabled by setting either the single receive enable bit, sren (rcstax<5>), or the continuous receive enable bit, cren (rcstax<4>). data is sampled on the rxx pin on the falling edge of the clock. if enable bit sren is set, only a single word is received. if enable bit cren is set, the reception is continuous until cren is cleared. if both bits are set, then cren takes precedence. to set up a synchronous master reception: 1. initialize the spbrghx:spbrgx registers for the appropriate baud rate. set or clear the brg16 bit, as required, to achieve the desired baud rate. 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. ensure bits cren and sren are clear. 4. if interrupts are desired, set enable bit rcxie. 5. if 9-bit reception is desired, set bit rx9. 6. if a single reception is required, set bit sren. for continuous reception, set bit cren. 7. interrupt flag bit, rcxif, will be set when recep- tion is complete and an interrupt will be generated if the enable bit, rcxie, was set. 8. read the rcstax register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcregx register. 10. if any error occurred, clear the error by clearing bit cren. 11. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 20-13: synchronous reception (master mode, sren) cren bit dtx pin ckx pin write to bit sren sren bit rcxif bit (interrupt) read rcregx q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 ? 0 ? bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ? 0 ? q1 q2 q3 q4 note: timing diagram demonstrates sync master mode with bit sren = 1 and bit brgh = 0 . ckx pin (sckp = 0 ) (sckp = 1 )
? 2004 microchip technology inc. preliminary ds39646b-page 267 pic18f8722 family table 20-8: registers associated with synchronous master reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie /giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 60 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 60 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 60 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 60 trisg ? ? ? trisg4 trisg3 trisg2 trisg1 trisg0 60 rcstax spen rx9 sren cren adden ferr oerr rx9d 59 rcregx eusartx receive register 59 txstax csrc tx9 txen sync sendb brgh trmt tx9d 59 baudconx abdovf rcidl ? sckp brg16 ? wue abden 61 spbrghx eusartx baud rate generator register high byte 61 spbrgx eusartx baud rate generator register low byte 59 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master reception.
pic18f8722 family ds39646b-page 268 preliminary ? 2004 microchip technology inc. 20.4 eusart synchronous slave mode synchronous slave mode is entered by clearing bit, csrc (txstax<7>). this mode differs from the synchronous master mode in that the shift clock is supplied externally at the ckx pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in any low-power mode. 20.4.1 eusart synchronous slave transmission the operation of the synchronous master and slave modes is identical, except in the case of sleep mode. if two words are written to the txregx and then the sleep instruction is executed, the following will occur: a) the first word will immediately transfer to the tsrx register and transmit. b) the second word will remain in the txregx register. c) flag bit, txxif, will not be set. d) when the first word has been shifted out of tsrx, the txregx register will transfer the second word to the tsrx and flag bit, txxif, will now be set. e) if enable bit txxie is set, the interrupt will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave transmission: 1. enable the synchronous slave serial port by setting bits sync and spen and clearing bit csrc. 2. clear bits cren and sren. 3. if interrupts are desired, set enable bit txxie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting enable bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txregx register. 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. table 20-9: registers associated with synchronous slave transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 60 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 60 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 60 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 60 trisg ? ? ? trisg4 trisg3 trisg2 trisg1 trisg0 60 rcstax spen rx9 sren cren adden ferr oerr rx9d 59 txregx eusartx transmit register 59 txstax csrc tx9 txen sync sendb brgh trmt tx9d 59 baudconx abdovf rcidl ? sckp brg16 ? wue abden 61 spbrghx eusartx baud rate generator register high byte 61 spbrgx eusartx baud rate generator register low byte 59 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave transmission.
? 2004 microchip technology inc. preliminary ds39646b-page 269 pic18f8722 family 20.4.2 eusart synchronous slave reception the operation of the synchronous master and slave modes is identical, except in the case of sleep, or any idle mode and bit sren, which is a ?don?t care? in slave mode. if receive is enabled by setting the cren bit prior to entering sleep or any idle mode, then a word may be received while in this low-power mode. once the word is received, the rsrx register will transfer the data to the rcregx register; if the rcxie enable bit is set, the interrupt generated will wake the chip from the low- power mode. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave reception: 1. enable the synchronous master serial port by setting bits sync and spen and clearing bit csrc. 2. if interrupts are desired, set enable bit rcxie. 3. if 9-bit reception is desired, set bit rx9. 4. to enable reception, set enable bit cren. 5. flag bit, rcxif, will be set when reception is complete. an interrupt will be generated if enable bit, rcxie, was set. 6. read the rcstax register to get the 9th bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcregx register. 8. if any error occurred, clear the error by clearing bit cren. 9. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. table 20-10: registers associated with synchronous slave reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 60 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 60 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 60 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 60 trisg ? ? ? trisg4 trisg3 trisg2 trisg1 trisg0 60 rcstax spen rx9 sren cren adden ferr oerr rx9d 59 rcregx eusartx receive register 59 txstax csrc tx9 txen sync sendb brgh trmt tx9d 59 baudconx abdovf rcidl ? sckp brg16 ? wue abden 61 spbrghx eusartx baud rate generator register high byte 61 spbrgx eusartx baud rate generator register low byte 59 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave reception.
pic18f8722 family ds39646b-page 270 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39646b-page 271 pic18f8722 family 21.0 10-bit analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has 12 inputs for the 64-pin devices and 16 for the 80-pin devices. this module allows conversion of an analog input signal to a corresponding 10-bit digital number. the module has five registers: a/d result high register (adresh) a/d result low register (adresl) a/d control register 0 (adcon0) a/d control register 1 (adcon1) a/d control register 2 (adcon2) the adcon0 register, shown in register 21-1, controls the operation of the a/d module. the adcon1 register, shown in register 21-2, configures the functions of the port pins. the adcon2 register, shown in register 21-3, configures the a/d clock source, programmed acquisition time and justification. register 21-1: adcon0: a/d control register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? chs3 chs2 chs1 chs0 go/done adon bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-2 chs3:chs0: analog channel select bits 0000 = channel 0 (an0) 0001 = channel 1 (an1) 0010 = channel 2 (an2) 0011 = channel 3 (an3) 0100 = channel 4 (an4) 0101 = channel 5 (an5) 0110 = channel 6 (an6) 0111 = channel 7 (an7) 1000 = channel 8 (an8) 1001 = channel 9 (an9) 1010 = channel 10 (an10) 1011 = channel 11 (an11) 1100 = channel 12 (an12) (1) 1101 = channel 13 (an13) (1) 1110 = channel 14 (an14) (1) 1111 = channel 15 (an15) (1) note 1: these channels are not implemented on 64-pin devices. bit 1 go/done : a/d conversion status bit when adon = 1 : 1 = a/d conversion in progress 0 = a/d idle bit 0 adon: a/d on bit 1 = a/d converter module is enabled 0 = a/d converter module is disabled legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 272 preliminary ? 2004 microchip technology inc. register 21-2: adcon1: a/d control register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-4 vcfg1:vcfg0: voltage reference configuration bits bit 3-0 pcfg3:pcfg0: a/d port configuration control bits: legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown a/d v ref + a/d v ref - 00 av dd av ss 01 external v ref +av ss 10 av dd external v ref - 11 external v ref + external v ref - a = analog input d = digital i/o note 1: an15 through an12 are available only on 80-pin devices. pcfg3: pcfg0 an15 (1) an14 (1) an13 (1) an12 (1) an11 an10 an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 0000 a a aaa aaa a a aaaaaa 0001 d d aaa aaa a a aaaaaa 0010 d ddaa aaa a a aaaaaa 0011 d ddda aaa a a aaaaaa 0100 d dddd aaa a a aaaaaa 0101 d dddddaa a a aaaaaa 0110 d dddddda a a aaaaaa 0111 d ddddddd a a aaaaaa 1000 d dddddddda aaaaaa 1001 d dddddddddaaaaaa 1010 d ddddddddddaaaaa 1011 d dddddddddddaaaa 1100 d d ddd ddd d d dddaaa 1101 d d ddd ddd d d ddd da a 1110 d d ddd ddd d d ddddda 1111 d d ddd ddd d d dddddd
? 2004 microchip technology inc. preliminary ds39646b-page 273 pic18f8722 family register 21-3: adcon2: a/d control register 2 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 bit 7 bit 0 bit 7 adfm: a/d result format select bit 1 = right justified 0 = left justified bit 6 unimplemented: read as ? 0 ? bit 5-3 acqt2:acqt0: a/d acquisition time select bits 111 = 20 t ad 110 = 16 t ad 101 = 12 t ad 100 = 8 t ad 011 = 6 t ad 010 = 4 t ad 001 = 2 t ad 000 = 0 t ad (1) bit 2-0 adcs2:adcs0: a/d conversion clock select bits 111 = f rc (clock derived from a/d rc oscillator) (1) 110 = f osc /64 101 = f osc /16 100 = f osc /4 011 = f rc (clock derived from a/d rc oscillator) (1) 010 = f osc /32 001 = f osc /8 000 = f osc /2 note 1: if the a/d f rc clock source is selected, a delay of one t cy (instruction cycle) is added before the a/d clock starts. this allows the sleep instruction to be executed before starting a conversion. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 274 preliminary ? 2004 microchip technology inc. the analog reference voltage is software selectable to either the device?s positive and negative supply voltage (v dd and v ss ), or the voltage level on the ra3/an3/ v ref + and ra2/an2/v ref - pins. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to oper- ate in sleep, the a/d conversion clock must be derived from the a/d?s internal rc oscillator. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. a device reset forces all registers to their reset state. this forces the a/d module to be turned off and any conversion in progress is aborted. each port pin associated with the a/d converter can be configured as an analog input, or as a digital i/o. the adresh and adresl registers contain the result of the a/d conversion. when the a/d conversion is com- plete, the result is loaded into the adresh:adresl register pair, the go/done bit (adcon0 register) is cleared and a/d interrupt flag bit, adif (pir1<6>), is set. the block diagram of the a/d module is shown in figure 21-1. figure 21-1: a/d block diagram (input voltage) v ain v ref + reference voltage av dd vcfg1:vcfg0 chs3:chs0 an7 an6 an5 an4 an3 an2 an1 an0 0111 0110 0101 0100 0011 0010 0001 0000 10-bit converter v ref - av ss a/d an12 (1) an11 an10 an9 an8 1100 1011 1010 1001 1000 note 1: channels an12 through an15 are not available on 64-pin devices. 2: i/o pins have diode protection to v dd and v ss . 0 x 1 x x 1 x 0 an15 (1) an14 (1) an13 (1) 1111 1110 1101
? 2004 microchip technology inc. preliminary ds39646b-page 275 pic18f8722 family the value in the adresh:adresl registers is not modified for a power-on reset. the adresh:adresl registers will contain unknown data after a power-on reset. after the a/d module has been configured as desired, the selected channel must be acquired before the conversion is started. the analog input channels must have their corresponding tris bits selected as an input. to determine acquisition time, see section 21.1 ?a/d acquisition requirements? . after this acquisi- tion time has elapsed, the a/d conversion can be started. an acquisition time can be programmed to occur between setting the go/done bit and the actual start of the conversion. the following steps should be followed to perform an a/d conversion: 1. configure the a/d module: configure analog pins, voltage reference and digital i/o (adcon1) select a/d input channel (adcon0) select a/d acquisition time (adcon2) select a/d conversion clock (adcon2) turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): clear adif bit set adie bit set gie bit 3. wait the required acquisition time (if required). 4. start conversion: set go/done bit (adcon0 register) 5. wait for a/d conversion to complete, by either: polling for the go/done bit to be cleared or waiting for the a/d interrupt 6. read a/d result registers (adresh:adresl); clear bit adif, if required. 7. for next conversion, go to step 1 or step 2, as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2 t ad is required before the next acquisition starts. figure 21-2: a/d transfer function figure 21-3: analog input model digital code output 3feh 003h 002h 001h 000h 0.5 lsb 1 lsb 1.5 lsb 2 lsb 2.5 lsb 1022 lsb 1022.5 lsb 3 lsb analog input voltage 3ffh 1023 lsb 1023.5 lsb v ain c pin rs anx 5 pf v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = 25 pf v ss v dd 100 na legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions = sampling switch resistance r ss v dd 6v sampling switch 5v 4v 3v 2v 123 4 (k ? )
pic18f8722 family ds39646b-page 276 preliminary ? 2004 microchip technology inc. 21.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 21-3. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ). the source impedance affects the offset voltage at the analog input (due to pin leakage current). the maximum recommended impedance for analog sources is 2.5 k ? . after the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. to calculate the minimum acquisition time, equation 21-1 may be used. this equation assumes that 1/2 lsb error is used (1024 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. example 21-3 shows the calculation of the minimum required acquisition time t acq . this calculation is based on the following application system assumptions: c hold = 25 pf rs = 2.5 k ? conversion error 1/2 lsb v dd =5v rss = 2 k ? temperature = 85 c (system max.) equation 21-1: acquisition time equation 21-2: a/d minimum charging time equation 21-3: calculating the minimum required acquisition time note: when the conversion is started, the holding capacitor is disconnected from the input pin. t acq = amplifier settling time + holding capacitor charging time + temperature coefficient =t amp + t c + t coff v hold = (v ref ? (v ref /2048)) (1 ? e (-t c /c hold (r ic + r ss + r s )) ) or t c = -(c hold )(r ic + r ss + r s ) ln(1/2048) t acq =t amp + t c + t coff t amp =0.2 s t coff = (temp ? 25 c)(0.02 s/ c) (85 c ? 25 c)(0.02 s/ c) 1.2 s temperature coefficient is only required for temperatures > 25 c. below 25 c, t coff = 0 ms. t c = -(c hold )(r ic + r ss + r s ) ln(1/2047) s -(25 pf) (1 k ? + 2 k ? + 2.5 k ? ) ln(0.0004883) s 1.05 s t acq =0.2 s + 1 s + 1.2 s 2.4 s
? 2004 microchip technology inc. preliminary ds39646b-page 277 pic18f8722 family 21.2 selecting and configuring acquisition time the adcon2 register allows the user to select an acquisition time that occurs each time the go/done bit is set. it also gives users the option to use an automatically determined acquisition time. acquisition time may be set with the acqt2:acqt0 bits (adcon2<5:3>) which provides a range of 2 to 20 t ad . when the go/done bit is set, the a/d module continues to sample the input for the selected acquisi- tion time, then automatically begins a conversion. since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the go/done bit. manual acquisition is selected when acqt2:acqt0 = 000 . when the go/done bit is set, sampling is stopped and a conversion begins. the user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the go/done bit. this option is also the default reset state of the acqt2:acqt0 bits and is compatible with devices that do not offer programmable acquisition times. in either case, when the conversion is completed, the go/done bit is cleared, the adif flag is set and the a/d begins sampling the currently selected channel again. if an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. 21.3 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 11 t ad per 10-bit conversion. the source of the a/d conversion clock is software selectable. there are seven possible options for t ad : 2 t osc 4 t osc 8 t osc 16 t osc 32 t osc 64 t osc internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be as short as possible, but greater than the minimum t ad (see parameter 130, table 28-27 for more information). table 21-1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. table 21-1: t ad vs. device operating frequencies ad clock source (t ad ) maximum device frequency operation adcs2:adcs0 pic18fxxxx pic18lfxxxx (4) 2 t osc 000 2.86 mhz 1.43 khz 4 t osc 100 5.71 mhz 2.86 mhz 8 t osc 001 11.43 mhz 5.72 mhz 16 t osc 101 22.86 mhz 11.43 mhz 32 t osc 010 40.0 mhz 22.86 mhz 64 t osc 110 40.0 mhz 22.86 mhz rc (3) x11 1.00 mhz (1) 1.00 mhz (2) note 1: the rc source has a typical t ad time of 1.2 s. 2: the rc source has a typical t ad time of 2.5 s. 3: for device frequencies above 1 mhz, the device must be in sleep for the entire conversion or the a/d accuracy may be out of specification. 4: low-power (pic18lfxxxx) devices only.
pic18f8722 family ds39646b-page 278 preliminary ? 2004 microchip technology inc. 21.4 operation in power-managed modes the selection of the automatic acquisition time and a/d conversion clock is determined in part by the clock source and frequency while in a power-managed mode. if the a/d is expected to operate while the device is in a power-managed mode, the acqt2:acqt0 and adcs2:adcs0 bits in adcon2 should be updated in accordance with the clock source to be used in that mode. after entering the mode, an a/d acquisition or conversion may be started. once started, the device should continue to be clocked by the same clock source until the conversion has been completed. if desired, the device may be placed into the corresponding idle mode during the conversion. if the device clock frequency is less than 1 mhz, the a/d rc clock source should be selected. operation in the sleep mode requires the a/d f rc clock to be selected. if bits acqt2:acqt0 are set to ? 000 ? and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the sleep instruction and entry to sleep mode. the idlen bit (osccon<7>) must have already been cleared prior to starting the conversion. 21.5 configuring analog port pins the adcon1, trisa, trisf and trish registers all configure the a/d port pins. the port pins needed as analog inputs must have their corresponding tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs3:chs0 bits and the tris bits. note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). pins con- figured as digital inputs will convert as analog inputs. analog levels on a digitally configured input will be accurately converted. 2: analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device?s specification limits.
? 2004 microchip technology inc. preliminary ds39646b-page 279 pic18f8722 family 21.6 a/d conversions figure 21-4 shows the operation of the a/d converter after the go/done bit has been set and the acqt2:acqt0 bits are cleared. a conversion is started after the following instruction to allow entry into sleep mode before the conversion begins. figure 21-5 shows the operation of the a/d converter after the go/done bit has been set, the acqt2:acqt0 bits are set to ? 010 ? and a 4 t ad acquisition time is selected before the conversion starts. clearing the go/done bit during a conversion will abort the current conversion. the a/ d result register pair will not be updated with the partially completed a/d conversion sample. this means the adresh:adresl registers will continue to contain the value of the last completed conversion (or the last value written to the adresh:adresl registers). after the a/d conversion is completed or aborted, a 2t ad wait is required before the next acquisition can be started. after this wait, acquisition on the selected channel is automatically started. 21.7 discharge the discharge phase is used to initialize the value of the capacitor array. the array is discharged before every sample. this feature helps to optimize the unity- gain amplifier, as the circuit always needs to charge the capacitor array, rather than charge/discharge based on previous measure values. figure 21-4: a/d conversion t ad cycles (acqt<2:0> = 000 , t acq = 0 ) figure 21-5: a/d conversion t ad cycles (acqt<2:0> = 010 , t acq = 4 t ad ) note: the go/done bit should not be set in the same instruction that turns on the a/d. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go/done bit holding capacitor is disconnected from analog input (typically 100 ns) t ad 9 t ad 10 t cy - t ad adresh:adresl are loaded, go/done bit is cleared, adif bit is set, holding capacitor is connected to analog input. conversion starts b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 on the following cycle: t ad 1 discharge 1 2 3 4 5 6 7 8 11 set go/done bit (holding capacitor is disconnected) 9 10 conversion starts 1 2 3 4 (holding capacitor continues acquiring input) t acqt cycles t ad cycles automatic acquisition time b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 adresh:adresl are loaded, go/done bit is cleared, adif bit is set, holding capacitor is connected to analog input. on the following cycle: t ad 1 discharge
pic18f8722 family ds39646b-page 280 preliminary ? 2004 microchip technology inc. 21.8 use of the eccp2 trigger an a/d conversion can be started by the special event trigger of the eccp2 module. this requires that the ccp2m3:ccp2m0 bits (ccp2con<3:0>) be programmed as ? 1011 ? and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, starting the a/d acquisition and conversion and the timer1 (or timer3) counter will be reset to zero. timer1 (or timer3) is reset to automat- ically repeat the a/d acquisition period with minimal software overhead (moving adresh:adresl to the desired location). the appropriate analog input chan- nel must be selected and the minimum acquisition period is either timed by the user, or an appropriate t acq time selected before the special event trigger sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), the special event trigger will be ignored by the a/d module but will still reset the timer1 (or timer3) counter. table 21-2: registers associated with a/d operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 60 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 60 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 60 pir2 oscfif cmif ? eeif bcl1if hlvdif tmr3if ccp2if 60 pie2 oscfie cmie ? eeie bcl1ie hlvdie tmr3ie ccp2ie 60 ipr2 oscfip cmip ? eeip bcl1ip hlvdip tmr3ip ccp2ip 60 adresh a/d result register high byte 59 adresl a/d result register low byte 59 adcon0 ? ? chs3 chs2 chs1 chs0 go/done adon 59 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 59 adcon2 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 59 trisa trisa7 (1) trisa6 (1) trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 60 trisf trisf7 trisf6 trisf5 trisf 4 trisf3 trisf2 trisf1 trisf0 60 trish (2) trish7 trish6 trish5 trish4 trish3 trish2 trish1 trish0 60 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for a/d conversion. note 1: porta<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. when disabled, these bits read as ? 0 ?. 2: these registers are not implemented on 64-pin devices.
? 2004 microchip technology inc. preliminary ds39646b-page 281 pic18f8722 family 22.0 comparator module the analog comparator module contains two comparators that can be configured in a variety of ways. the inputs can be selected from the analog inputs multiplexed with pins rf3 through rf6, as well as the on-chip voltage reference (see section 23.0 ?comparator voltage reference module? ). the digital outputs (normal or inverted) are available on rf1 and rf2 and can also be read through the control register. the cmcon register (register 22-1) selects the comparator input and output configuration. block diagrams of the various comparator configurations are shown in figure 22-1. register 22-1: cmcon: comparator module control register r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-1 c2out c1out c2inv c1inv cis cm2 cm1 cm0 bit 7 bit 0 bit 7 c2out : comparator 2 output bit when c2inv = 0 : 1 = c2 v in + > c2 v in - 0 = c2 v in + < c2 v in - when c2inv = 1 : 1 = c2 v in + < c2 v in - 0 = c2 v in + > c2 v in - bit 6 c1out : comparator 1 output bit when c1inv = 0 : 1 = c1 v in + > c1 v in - 0 = c1 v in + < c1 v in - when c1inv = 1 : 1 = c1 v in + < c1 v in - 0 = c1 v in + > c1 v in - bit 5 c2inv : comparator 2 output inversion bit 1 = c2 output inverted 0 = c2 output not inverted bit 4 c1inv : comparator 1 output inversion bit 1 = c1 output inverted 0 = c1 output not inverted bit 3 cis : comparator input switch bit when cm2:cm0 = 110 : 1 =c1 v in - connects to rf5/an10/cv ref c2 v in - connects to rf3/an8 0 =c1 v in - connects to rf6/an11 c2 v in - connects to rf4/an9 bit 2-0 cm2:cm0 : comparator mode bits figure 22-1 shows the comparator modes and the cm2:cm0 bit settings. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 282 preliminary ? 2004 microchip technology inc. 22.1 comparator configuration there are eight modes of operation for the compara- tors, shown in figure 22-1. bits cm2:cm0 of the cmcon register are used to select these modes. the trisf register controls the data direction of the comparator pins for each mode. if the comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in section 28.0 ?electrical characteristics? . figure 22-1: comparator i/o operating modes note: comparator interrupts should be disabled during a comparator mode change; otherwise, a false interrupt may occur. c1 rf6/an11 v in - v in + rf5/an10/ off (read as ? 0 ?) comparators reset a a cm2:cm0 = 000 c2 rf4/an9 v in - v in + rf3/an8 off (read as ? 0 ?) a a c1 v in - v in + c1out two independent comparators a a cm2:cm0 = 010 c2 v in - v in + c2out a a c1 v in - v in + c1out two common reference comparators a a cm2:cm0 = 100 c2 v in - v in + c2out a d c2 v in - v in + off (read as ? 0 ?) one independent comparator with output d d cm2:cm0 = 001 c1 v in - v in + c1out a a c1 v in - v in + off (read as ? 0 ?) comparators off (por default value) d d cm2:cm0 = 111 c2 v in - v in + off (read as ? 0 ?) d d c1 v in - v in + c1out four inputs multiplexed to two comparators a a cm2:cm0 = 110 c2 v in - v in + c2out a a from v ref module cis = 0 cis = 1 cis = 0 cis = 1 c1 v in - v in + c1out two common reference comparators with outputs a a cm2:cm0 = 101 c2 v in - v in + c2out a d a = analog input, port reads zeros always d = digital input cis (cmcon<3>) is the comparator input switch cv ref c1 v in - v in + c1out two independent comparators with outputs a a cm2:cm0 = 011 c2 v in - v in + c2out a a rf1/an6/c2out* rf6/an11 rf5/an10 rf4/an9 rf3/an8 rf2/an7/c1out* rf1/an6/c2out* rf2/an7/ * setting the trisf<2:1> bits will disable the comparator outputs by configuring the pins as inputs. cv ref rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref rf2/an7/ rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref rf6/an11 rf5/an10/ cv ref rf4/an9 rf3/an8 c1out* c1out*
? 2004 microchip technology inc. preliminary ds39646b-page 283 pic18f8722 family 22.2 comparator operation a single comparator is shown in figure 22-2, along with the relationship between the analog input levels and the digital output. when the analog input at v in + is less than the analog input v in -, the output of the comparator is a digital low level. when the analog input at v in + is greater than the analog input v in -, the output of the comparator is a digital high level. the shaded areas of the output of the comparator in figure 22-2 represent the uncertainty, due to input offsets and response time. 22.3 comparator reference depending on the comparator operating mode, either an external or internal voltage reference may be used. the analog signal present at v in - is compared to the signal at v in + and the digital output of the comparator is adjusted accordingly (figure 22-2). figure 22-2: single comparator 22.3.1 external reference signal when external voltage references are used, the comparator module can be configured to have the com- parators operate from the same or different reference sources. however, threshold detector applications may require the same reference. the reference signal must be between v ss and v dd and can be applied to either pin of the comparator(s). 22.3.2 internal reference signal the comparator module also allows the selection of an internally generated voltage reference from the comparator voltage reference module. this module is described in more detail in section 23.0 ?comparator voltage reference module? . the internal reference is only available in the mode where four inputs are multiplexed to two comparators (cm2:cm0 = 110 ). in this mode, the internal voltage reference is applied to the v in + pin of both comparators. 22.4 comparator response time response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. if the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. otherwise, the maximum delay of the comparators should be used (see section 28.0 ?electrical characteristics? ). 22.5 comparator outputs the comparator outputs are read through the cmcon register. these bits are read-only. the comparator outputs may also be directly output to the rf1 and rf2 i/o pins. when enabled, multiplexors in the output path of the rf1 and rf2 pins will switch and the output of each pin will be the unsynchronized output of the comparator. the uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. figure 22-3 shows the comparator output block diagram. the trisf bits will still function as an output enable/ disable for the rf1 and rf2 pins while in this mode. the polarity of the comparator outputs can be changed using the c2inv and c1inv bits (cmcon<5:4>). ? + v in + v in - output output v in - v in + note 1: when reading the port register, all pins configured as analog inputs will read as a ? 0 ?. pins configured as digital inputs will convert an analog input according to the schmitt trigger input specification. 2: analog levels on any pin defined as a digital input may cause the input buffer to consume more current than is specified.
pic18f8722 family ds39646b-page 284 preliminary ? 2004 microchip technology inc. figure 22-3: comparator output block diagram 22.6 comparator interrupts the comparator interrupt flag is set whenever there is a change in the output value of either comparator. software will need to maintain information about the status of the output bits, as read from cmcon<7:6>, to determine the actual change that occurred. the cmif bit (pir2<6>) is the comparator interrupt flag. the cmif bit must be reset by clearing it. since it is also possible to write a ? 1 ? to this register, a simulated interrupt may be initiated. both the cmie bit (pie2<6>) and the peie bit (intcon<6>) must be set to enable the interrupt. in addition, the gie bit (intcon<7>) must also be set. if any of these bits are clear, the interrupt is not enabled, though the cmif bit will still be set if an interrupt condition occurs. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of cmcon will end the mismatch condition. b) clear flag bit cmif. a mismatch condition will continue to set flag bit cmif. reading cmcon will end the mismatch condition and allow flag bit cmif to be cleared. 22.7 comparator operation during sleep when a comparator is active and the device is placed in sleep mode, the comparator remains active and the interrupt is functional if enabled. this interrupt will wake-up the device from sleep mode, when enabled. each operational comparator will consume additional current, as shown in the comparator specifications. to minimize power consumption while in sleep mode, turn off the comparators (cm2:cm0 = 111 ) before entering sleep. if the device wakes up from sleep, the contents of the cmcon register are not affected. 22.8 effects of a reset a device reset forces the cmcon register to its reset state, causing the comparator modules to be turned off (cm2:cm0 = 111) . however, the input pins (rf3 through rf6) are configured as analog inputs by default on device reset. the i/o configuration for these pins is also determined by the setting of the pcfg3:pcfg0 bits (adcon1<3:0>). therefore, device current is minimized when analog inputs are present at reset time. dq en cxout bus data set multiplex cmif bit -+ port pins read cmcon reset from other comparator cxinv dq en cl note: if a change in the cmcon register (c1out or c2out) should occur when a read operation is being executed (start of the q2 cycle), then the cmif (pir2 register) interrupt flag may not get set.
? 2004 microchip technology inc. preliminary ds39646b-page 285 pic18f8722 family 22.9 analog input connection considerations a simplified circuit for an analog input is shown in figure 22-4. since the analog pins are connected to a digital output, they have reverse biased diodes to v dd and v ss . the analog input, therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6v in either direction, one of the diodes is forward biased and a latch-up condition may occur. a maximum source impedance of 10 k ? is recommended for the analog sources. any external component connected to an analog input pin, such as a capacitor or a zener diode, should have very little leakage current. figure 22-4: comparator analog input model table 22-1: registers associated with comparator module va r s < 10k a in c pin 5 pf v dd v t = 0.6v v t = 0.6v r ic i leakage 500 na v ss legend: c pin = input capacitance v t = threshold voltage i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance r s = source impedance va = analog voltage comparator input name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 59 cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 59 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 60 pir2 oscfif cmif ? eeif bcl1if hlvdif tmr3if ccp2if 60 pie2 oscfie cmie ? eeie bcl1ie hlvdie tmr3ie ccp2ie 60 ipr2 oscfip cmip ? eeip bcl1ip hlvdip tmr3ip ccp2ip 60 trisf trisf7 trisf6 trisf5 trisf 4trisf3trisf2trisf1trisf0 60 legend: ? = unimplemented, read as ? 0 ?. shaded cells are unused by the comparator module.
pic18f8722 family ds39646b-page 286 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39646b-page 287 pic18f8722 family 23.0 comparator voltage reference module the comparator voltage reference is a 16-tap resistor ladder network that provides a selectable reference voltage. although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. a block diagram of the module is shown in figure 23-1. the resistor ladder is segmented to provide two ranges of cv ref values and has a power-down function to conserve power when the reference is not being used. the module?s supply reference can be provided from either device v dd /v ss or an external voltage reference. 23.1 configuring the comparator voltage reference the voltage reference module is controlled through the cvrcon register (register 23-1). the comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. the range to be used is selected by the cvrr bit (cvrcon<5>). the primary difference between the ranges is the size of the steps selected by the cv ref selection bits (cvr3:cvr0), with one range offering finer resolution. the equations used to calculate the output of the comparator voltage reference are as follows: if cvrr = 1 : cv ref = ((cvr3:cvr0)/24) x (cv rsrc ) if cvrr = 0 : cv ref =(cv rsrc /4) + ((cvr3:cvr0)/32) x (cv rsrc ) the comparator reference supply voltage can come from either v dd and v ss , or the external v ref + and v ref - that are multiplexed with ra2 and ra3. the voltage source is selected by the cvrss bit (cvrcon<4>). the settling time of the comparator voltage reference must be considered when changing the cv ref output (see table 28-3 in section 28.0 ?electrical characteristics? ). register 23-1: cvrcon: comparator voltage refe rence control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cvren cvroe (1) cvrr cvrss cvr3 cvr2 cvr1 cvr0 bit 7 bit 0 bit 7 cvren : comparator voltage reference enable bit 1 =cv ref circuit powered on 0 =cv ref circuit powered down bit 6 cvroe : comparator v ref output enable bit (1) 1 =cv ref voltage level is also output on the rf5/an10/cv ref pin 0 =cv ref voltage is disconnected from the rf5/an10/cv ref pin note 1: cvroe overrides the trisf<5> bit setting. bit 5 cvrr : comparator v ref range selection bit 1 = 0 to 0.667 cv rsrc , with cv rsrc /24 step size (low range) 0 = 0.25 cv rsrc to 0.75 cv rsrc , with cv rsrc /32 step size (high range) bit 4 cvrss : comparator v ref source selection bit 1 = comparator reference source, cv rsrc = (v ref +) ? (v ref -) 0 = comparator reference source, cv rsrc = av dd ? av ss bit 3-0 cvr3:cvr0: comparator v ref value selection bits (0 (cvr3:cvr0) 15) when cvrr = 1 : cv ref = ((cvr3:cvr0)/24) x (cv rsrc ) when cvrr = 0 : cv ref = (cv rsrc /4) + ((cvr3:cvr0)/32) x (cv rsrc ) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 288 preliminary ? 2004 microchip technology inc. figure 23-1: comparator voltage reference block diagram 23.2 voltage reference accuracy/error the full range of voltage reference cannot be realized due to the construction of the module. the transistors on the top and bottom of the resistor ladder network (figure 23-1) keep cv ref from approaching the refer- ence source rails. the voltage reference is derived from the reference source; therefore, the cv ref output changes with fluctuations in that source. the tested absolute accuracy of the voltage reference can be found in section 28.0 ?electrical characteristics? . 23.3 operation during sleep when the device wakes up from sleep through an interrupt or a watchdog timer time-out, the contents of the cvrcon register are not affected. to minimize current consumption in sleep mode, the voltage reference should be disabled. 23.4 effects of a reset a device reset disables the voltage reference by clearing bit, cvren (cvrcon<7>). this reset also disconnects the reference from the rf5 pin by clearing bit, cvroe (cvrcon<6>) and selects the high-voltage range by clearing bit, cvrr (cvrcon<5>). the cvr value select bits are also cleared. 23.5 connection considerations the voltage reference module operates independently of the comparator module. the output of the reference generator may be connected to the rf5 pin if the cvroe bit is set. enabling the voltage reference out- put onto rf5 when it is configured as a digital input will increase current consumption. connecting rf5 as a digital output with cvrss enabled will also increase current consumption. the rf5 pin can be used as a simple d/a output with limited drive capability. due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to v ref . figure 23-2 shows an example buffering technique. 16-to-1 mux cvr3:cvr0 8r r cvren cvrss = 0 av dd v ref + cvrss = 1 8r cvrss = 0 v ref - cvrss = 1 r r r r r r 16 steps cvrr cv ref av ss
? 2004 microchip technology inc. preliminary ds39646b-page 289 pic18f8722 family figure 23-2: comparator voltage reference output buffer example table 23-1: registers associated with comparator voltage reference cv ref output + ? cv ref module voltage reference output impedance r (1) rf5 note 1: r is dependent upon the voltage reference confi guration bits, cvrcon<3:0> and cvrcon<5>. pic18fxxxx name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 59 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 59 trisf trisf7 trisf6 trisf5 trisf 4 trisf3 trisf2 trisf1 trisf0 60 legend: shaded cells are not used with the comparator voltage reference.
pic18f8722 family ds39646b-page 290 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39646b-page 291 pic18f8722 family 24.0 high/low-voltage detect (hlvd) the pic18f8722 family of devices have a high/low-voltage detect module (hlvd). this is a pro- grammable circuit that allows the user to specify both a device voltage trip point and the direction of change from that point. if the device experiences an excursion past the trip point in that direction, an interrupt flag is set. if the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. the high/low-voltage detect control register (register 24-1) completely controls the operation of the hlvd module. this allows the circuitry to be ?turned off? by the user under software control, which minimizes the current consumption for the device. the block diagram for the hlvd module is shown in figure 24-1. register 24-1: hlvdcon: high/low-voltage de tect control register r/w-0 u-0 r-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-1 vdirmag ? irvst hlvden hlvdl3 (1) hlvdl2 (1) hlvdl1 (1) hlvdl0 (1) bit 7 bit 0 bit 7 vdirmag: voltage direction magnitude select bit 1 = event occurs when voltage equals or exceeds trip point (hlvdl3:hldvl0) 0 = event occurs when voltage equals or falls below trip point (hlvdl3:hlvdl0) bit 6 unimplemented: read as ? 0 ? bit 5 irvst: internal reference voltage stable flag bit 1 = indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range 0 = indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage range and the hlvd interrupt should not be enabled bit 4 hlvden: high/low-voltage detect power enable bit 1 = hlvd enabled 0 = hlvd disabled bit 3-0 hlvdl3:hlvdl0: voltage detection limit bits (1) 1111 = external analog input is used (input comes from the hlvdin pin) 1110 = maximum setting . . . 0000 = minimum setting note 1: see table 28-4 for specifications. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f8722 family ds39646b-page 292 preliminary ? 2004 microchip technology inc. the module is enabled by setting the hlvden bit. each time that the hlvd module is enabled, the circuitry requires some time to stabilize. the irvst bit is a read-only bit and is used to indicate when the circuit is stable. the module can only generate an interrupt after the circuit is stable and irvst is set. the vdirmag bit determines the overall operation of the module. when vdirmag is cleared, the module monitors for drops in v dd below a predetermined set point. when the bit is set, the module monitors for rises in v dd above the set point. 24.1 operation when the hlvd module is enabled, a comparator uses an internally generated reference voltage as the set point. the set point is compared with the trip point, where each node in the resistor divider represents a trip point voltage. the ?trip point? voltage is the voltage level at which the device detects a high or low-voltage event, depending on the configuration of the module. when the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the internal reference voltage generated by the voltage reference module. the comparator then generates an interrupt signal by setting the hlvdif bit. the trip point voltage is software programmable to any one of 16 values. the trip point is selected by programming the hlvdl3:hlvdl0 bits (hlvdcon<3:0>). the hlvd module has an additional feature that allows the user to supply the trip voltage to the module from an external source. this mode is enabled when bits hlvdl3:hlvdl0 are set to ? 1111 ?. in this state, the comparator input is multiplexed from the external input pin, hlvdin. this gives users flexibility because it allows them to configure the high/low-voltage detect interrupt to occur at any voltage in the valid operating range. figure 24-1: hlvd module block diagram (with external input) set v dd 16-to-1 mux hlvden hlvdcon hlvdl3:hlvdl0 register hlvdin v dd externally generated trip point hlvdif hlvden boren internal voltage reference vdirmag 1.2v typical
? 2004 microchip technology inc. preliminary ds39646b-page 293 pic18f8722 family 24.2 hlvd setup the following steps are needed to set up the hlvd module: 1. write the value to the hlvdl3:hlvdl0 bits that selects the desired hlvd trip point. 2. set the vdirmag bit to detect high voltage (vdirmag = 1 ) or low voltage (vdirmag = 0 ). 3. enable the hlvd module by setting the hlvden bit. 4. clear the hlvd interrupt flag (pir2<2>), which may have been set from a previous interrupt. 5. enable the hlvd interrupt if interrupts are desired by setting the hlvdie and gie bits (pie2<2> and intcon<7>). an interrupt will not be generated until the irvst bit is set. 24.3 current consumption when the module is enabled, the hlvd comparator and voltage divider are enabled and will consume static current. the total current consumption, when enabled, is specified in electrical specification parameter d022b ( section 28.2 ?dc characteristics? ). depending on the application, the hlvd module does not need to be operating constantly. to decrease the current requirements, the hlvd circuitry may only need to be enabled for short periods where the voltage is checked. after doing the check, the hlvd module may be disabled. 24.4 hlvd start-up time the internal reference voltage of the hlvd module, specified in electrical specification parameter d420 ( section 28.2 ?dc characteristics? ), may be used by other internal circuitry, such as the programmable brown-out reset. if the hlvd or other circuits using the voltage reference are disabled to lower the device?s current consumption, the reference voltage circuit will require time to become stable before a low or high-voltage condition can be reliably detected. this start-up time, t irvst , is an interval that is independent of device clock speed. it is specified in electrical specification parameter 36 (table 28-12). the hlvd interrupt flag is not enabled until t irvst has expired and a stable reference voltage is reached. for this reason, brief excursions beyond the set point may not be detected during this interval. refer to figure 24-2 or figure 24-3. figure 24-2: low-voltage detect operation (vdirmag = 0 ) v hlvd v dd hlvdif v hlvd v dd enable hlvd t irvst hlvdif may not be set enable hlvd hlvdif hlvdif cleared in software hlvdif cleared in software hlvdif cleared in software, case 1: case 2: hlvdif remains set since hlvd condition still exists t irvst internal reference is stable internal reference is stable irvst irvst
pic18f8722 family ds39646b-page 294 preliminary ? 2004 microchip technology inc. figure 24-3: high-voltage detect operation (vdirmag = 1 ) 24.5 applications in many applications, the ability to detect a drop below or rise above a particular threshold is desirable. for example, the hlvd module could be periodically enabled to detect universal serial bus (usb) attach or detach. this assumes the device is powered by a lower voltage source than the usb when detached. an attach would indicate a high-voltage detect from, for example, 3.3v to 5v (the voltage on usb) and vice versa for a detach. this feature could save a design a few extra components and an attach signal (input pin). for general battery applications, figure 24-4 shows a possible voltage curve. over time, the device voltage decreases. when the device voltage reaches voltage v a , the hlvd logic generates an interrupt at time t a . the interrupt could cause the execution of an isr, which would allow the application to perform ?house- keeping tasks? and perform a controlled shutdown before the device voltage exits the valid operating range at t b . the hlvd, thus, would give the applica- tion a time window, represented by the difference between t a and t b , to safely exit. figure 24-4: typical low-voltage detect application v hlvd v dd hlvdif v hlvd v dd enable hlvd t irvst hlvdif may not be set enable hlvd hlvdif hlvdif cleared in software hlvdif cleared in software hlvdif cleared in software, case 1: case 2: hlvdif remains set since hlvd condition still exists t irvst irvst internal reference is stable internal reference is stable irvst time voltage v a v b t a t b v a = hlvd trip point v b = minimum valid device operating voltage legend:
? 2004 microchip technology inc. preliminary ds39646b-page 295 pic18f8722 family 24.6 operation during sleep when enabled, the hlvd circuitry continues to operate during sleep. if the device voltage crosses the trip point, the hlvdif bit will be set and the device will wake-up from sleep. device execution will continue from the interrupt vector address if interrupts have been globally enabled. 24.7 effects of a reset a device reset forces all registers to their reset state. this forces the hlvd module to be turned off. table 24-1: registers associated with high/low-voltage detect module name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page hlvdcon vdirmag ? irvst hlvden hlvdl3 hlvdl2 hlvdl1 hlvdl0 58 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir2 oscfif cmif ? eeif bcl1if hlvdif tmr3if ccp2if 60 pie2 oscfie cmie ? eeie bcl1ie hlvdie tmr3ie ccp2ie 60 ipr2 oscfip cmip ? eeip bcl1ip hlvdip tmr3ip ccp2ip 60 trisa trisa7 (1) trisa6 (1) trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 60 legend: ? = unimplemented, read as ? 0 ?. shaded cells are unused by the hlvd module. note 1: porta<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. when disabled, these bits read as ? 0 ?.
pic18f8722 family ds39646b-page 296 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39646b-page 297 pic18f8722 family 25.0 special features of the cpu the pic18f8722 family of devices include several fea- tures intended to maximize reliability and minimize cost through elimination of external components. these are: oscillator selection resets: - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) interrupts watchdog timer (wdt) fail-safe clock monitor two-speed start-up code protection id locations in-circuit serial programming the oscillator can be configured for the application depending on frequency, power, accuracy and cost. all of the options are discussed in detail in section 2.0 ?oscillator configurations? . a complete discussion of device resets and interrupts is available in previous sections of this data sheet. in addition to their power-up and oscillator start-up timers provided for resets, the pic18f8722 family of devices has a watchdog timer, which is either perma- nently enabled via the configuration bits or software controlled (if configured as disabled). the inclusion of an internal rc oscillator also provides the additional benefits of a fail-safe clock monitor (fscm) and two-speed start-up. fscm provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. two- speed start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. all of these features are enabled and configured by setting the appropriate configuration register bits. 25.1 configuration bits the configuration bits can be programmed (read as ? 0 ?) or left unprogrammed (read as ? 1 ?) to select various device configurations. these bits are mapped starting at program memory location 300000h. the user will note that address 300000h is beyond the user program memory space. in fact, it belongs to the configuration memory space (300000h-3fffffh), which can only be accessed using table reads and table writes. programming the configuration registers is done in a manner similar to programming the flash memory. the wr bit in the eecon1 register starts a self-timed write to the configuration register. in normal operation mode, a tblwt instruction with the tblptr pointing to the configuration register sets up the address and the data for the configuration register write. setting the wr bit starts a long write to the configuration register. the configuration registers are written a byte at a time. to write or erase a configuration cell, a tblwt instruction can write a ? 1 ? or a ? 0 ? into the cell. for additional details on flash programming, refer to section 6.5 ?writing to flash program memory? .
pic18f8722 family ds39646b-page 298 preliminary ? 2004 microchip technology inc. table 25-1: configuration bits and device ids file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default/ unprogrammed value 300001h config1h ieso fcmen ? ? fosc3 fosc2 fosc1 fosc0 00-- 0111 300002h config2l ? ? ? borv1 borv0 boren1 boren0 pwrten ---1 1111 300003h config2h ? ? ? wdtps3 wdtps2 wdtps1 wdtps0 wdten ---1 1111 300004h config3l (5) wait bw abw1 abw0 ? ?pm1pm0 1111 --11 300005h config3h mclre ? ? ? ? lpt1osc eccpmx (5) ccp2mx 1--- -011 300006h config4l debug xinst bbsiz1 bbsiz0 ?lvp ?stvren 1000 -1-1 300008h config5l cp7 (1) cp6 (1) cp5 (2) cp4 (2) cp3 (3) cp2 cp1 cp0 1111 1111 300009h config5h cpd cpb ? ? ? ? ? ? 11-- ---- 30000ah config6l wrt7 (1) wrt6 (1) wrt5 (2) wrt4 (2) wrt3 (3) wrt2 wrt1 wrt0 1111 1111 30000bh config6h wrtd wrtb wrtc ? ? ? ? ? 111- ---- 30000ch config7l ebrt7 (1) ebrt6 (1) ebtr5 (2) ebtr4 (2) ebtr3 (3) ebtr2 ebtr1 ebtr0 1111 1111 30000dh config7h ?ebtrb ? ? ? ? ? ? -1-- ---- 3ffffeh devid1 (4) dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 xxxx xxxx 3fffffh devid2 (4) dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 xxxx xxxx legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. shaded cells are unimplemented, read as ? 0 ?. note 1: unimplemented in pic18f6527/6622/6627/8527/8622/8627 devices. 2: unimplemented in pic18f6527/6622/8527/8622 devices. 3: unimplemented in pic18f6527/8527 devices. 4: see register 25-13 for devid1 values. devid register s are read-only and cannot be programmed by the user. 5: unimplemented in pic18f6527/6622/6627/6722 devices.
? 2004 microchip technology inc. preliminary ds39646b-page 299 pic18f8722 family register 25-1: config1h: configuration register 1 high (byte address 300001h) r/p-0 r/p-0 u-0 u-0 r/p-0 r/p-1 r/p-1 r/p-1 ieso fcmen ? ? fosc3 fosc2 fosc1 fosc0 bit 7 bit 0 bit 7 ieso: internal/external oscillator switchover bit 1 = two-speed start-up enabled 0 = two-speed start-up disabled bit 6 fcmen: fail-safe clock monitor enable bit 1 = fail-safe clock monitor enabled 0 = fail-safe clock monitor disabled bit 5-4 unimplemented: read as ? 0 ? bit 3-0 fosc3:fosc0: oscillator selection bits 11xx = external rc oscillator, clko function on ra6 101x = external rc oscillator, clko function on ra6 1001 = internal oscillator block, clko function on ra6, port function on ra7 1000 = internal oscillator block, port function on ra6 and ra7 0111 = external rc oscillator, port function on ra6 0110 = hs oscillator, pll enabled (clock frequency = 4 x fosc1) 0101 = ec oscillator, port function on ra6 0100 = ec oscillator, clko function on ra6 0011 = external rc oscillator, clko function on ra6 0010 = hs oscillator 0001 = xt oscillator 0000 = lp oscillator legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
pic18f8722 family ds39646b-page 300 preliminary ? 2004 microchip technology inc. register 25-2: config2l: configuration register 2 low (byte address 300002h) u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ?borv1 (1) borv0 (1) boren1 (2) boren0 (2) pwrten (2) bit 7 bit 0 bit 7-5 unimplemented: read as ? 0 ? bit 4-3 borv1:borv0: brown-out reset voltage bits (1) 11 = minimum setting . . . 00 = maximum setting bit 2-1 boren1:boren0: brown-out reset enable bits (2) 11 = brown-out reset enabled in hardware only (sboren is disabled) 10 = brown-out reset enabled in hardware only and disabled in sleep mode (sboren is disabled) 01 = brown-out reset enabled and controlled by software (sboren is enabled) 00 = brown-out reset disabled in hardware and software bit 0 pwrten : power-up timer enable bit (2) 1 = pwrt disabled 0 = pwrt enabled note 1: see section 28.1 ?dc characteristics: supply voltage? for specifications. 2: the power-up timer is decoupled from brown-out reset, allowing these features to be independently controlled. legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
? 2004 microchip technology inc. preliminary ds39646b-page 301 pic18f8722 family register 25-3: config2h: configuration register 2 high (byte address 300003h) u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? wdtps3 wdtps2 wdtps1 wdtps0 wdten bit 7 bit 0 bit 7-5 unimplemented: read as ? 0 ? bit 4-1 wdtps3:wdtps0: watchdog timer postscale select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 bit 0 wdten: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled (control is placed on the swdten bit) legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
pic18f8722 family ds39646b-page 302 preliminary ? 2004 microchip technology inc. register 25-4: config3l: configuration register 3 low (byte address 300004h) (1) r/p-1 r/p-1 r/p-1 r/p-1 u-0 u-0 r/p-1 r/p-1 wait bw abw1 abw0 ? ?pm1pm0 bit 7 bit 0 bit 7 wait: external bus data wait enable bit 1 = wait selections are unavailable for table reads and table writes 0 = wait selections for table reads and table writes are determined by the wait1:wait0 bits bit 6 bw: data bus width select bit 1 = 16-bit external bus mode 0 = 8-bit external bus mode bit 5-4 abw<1:0>: address bus width select bits 11 = 20-bit address bus 10 = 16-bit address bus 01 = 12-bit address bus 00 = 8-bit address bus bit 3-2 unimplemented: read as ? 0 ? bit 1-0 pm<1:0>: processor data memory mode select bits 11 = microcontroller mode 10 = microprocessor mode 01 = microprocessor with boot block mode 00 = extended microcontroller mode note 1: this register is unimplemented in pic18f6527/6622/6627/6722 devices. legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
? 2004 microchip technology inc. preliminary ds39646b-page 303 pic18f8722 family register 25-5: config3h: configuration register 3 high (byte address 300005h) r/p-1 u-0 u-0 u-0 u-0 r/p-0 r/p-1 r/p-1 mclre ? ? ? ? lpt1osc eccpmx (1) ccp2mx bit 7 bit 0 bit 7 mclre: mclr pin enable bit 1 = mclr pin enabled; rg5 input pin disabled 0 = rg5 input pin enabled; mclr disabled bit 6-3 unimplemented: read as ? 0 ? bit 2 lpt1osc: low-power timer1 oscillator enable bit 1 = timer1 configured for low-power operation 0 = timer1 configured for higher power operation bit 1 eccpmx: eccp mux bit (1) 1 = eccp1/3 (p1b/p1c/p3b/p3c) are multiplexed onto re6, re5, re4 and re3 respectively 0 = eccp1/3 (p1b/p1c/p3b/p3c) are multiplexed onto rh7, rh6, rh5 and rh4 respectively bit 0 ccp2mx: ccp2 mux bit 1 = eccp2 input/output is multiplexed with rc1 0 = eccp2 input/output is multiplexed with rb3 in extended microcontroller, microprocessor or microprocessor with boot block mode (1) . eccp2 is multiplexed with re7 in microcontroller mode. note 1: this feature is only available on pic18f8527/8622/8627/8722 devices. legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
pic18f8722 family ds39646b-page 304 preliminary ? 2004 microchip technology inc. register 25-6: config4l: configuration register 4 low (byte address 300006h) r/p-1 r/p-0 r/p-0 r/p-0 u-0 r/p-1 u-0 r/p-1 debug xinst bbsiz1 bbsiz0 ?lvp ?stvren bit 7 bit 0 bit 7 debug : background debugger enable bit 1 = background debugger disabled, rb6 and rb7 configured as general purpose i/o pins 0 = background debugger enabled, rb6 and rb7 are dedicated to in-circuit debug bit 6 xinst: extended instruction set enable bit 1 = instruction set extension and indexed addressing mode enabled 0 = instruction set extension and indexed addressing mode disabled (legacy mode) bit 5-4 bbsiz<1:0>: boot block size select bits 11 = 4k words (8 kbytes) boot block size 10 = 4k words (8 kbytes) boot block size 01 = 2k words (4 kbytes) boot block size 00 = 1k word (2 kbytes) boot block size bit 3 unimplemented: read as ? 0 ? bit 2 lvp: single-supply icsp? enable bit 1 = single-supply icsp enabled 0 = single-supply icsp disabled bit 1 unimplemented: read as ? 0 ? bit 0 stvren: stack full/underflow reset enable bit 1 = stack full/underflow will cause reset 0 = stack full/underflow will not cause reset legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
? 2004 microchip technology inc. preliminary ds39646b-page 305 pic18f8722 family register 25-7: config5l: configuration register 5 low (byte address 300008h) r/c-1 r/c-1 r/c-1 r/c-1 r/c-1 r/c-1 r/c-1 r/c-1 cp7 (1) cp6 (1) cp5 (2) cp5 (2) cp3 (3) cp2 cp1 cp0 bit 7 bit 0 bit 7 cp7: code protection bit (1) 1 = block 7 (01c000-01ffffh) not code-protected 0 = block 7 (01c000-01ffffh) code-protected bit 6 cp6: code protection bit (1) 1 = block 6 (01bfff-018000h) not code-protected 0 = block 6 (01bfff-018000h) code-protected bit 5 cp5: code protection bit (2) 1 = block 5 (014000-017fffh) not code-protected 0 = block 5 (014000-017fffh) code-protected bit 4 cp4: code protection bit (2) 1 = block 4 (010000-013fffh) not code-protected 0 = block 4 (010000-013fffh) code-protected bit 3 cp3: code protection bit (3) 1 = block 3 (00c000-00ffffh) not code-protected 0 = block 3 (00c000-00ffffh) code-protected bit 2 cp2: code protection bit 1 = block 2 (008000-00bfffh) not code-protected 0 = block 2 (008000-00bfffh) code-protected bit 1 cp1: code protection bit 1 = block 1 (004000-007fffh) not code-protected 0 = block 1 (004000-007fffh) code-protected bit 0 cp0: code protection bit 1 = block 0 (000800, 001000 or 002000 (4) -003fffh) not code-protected 0 = block 0 (000800, 001000 or 002000 (4) -003fffh) code-protected note 1: unimplemented in pic18f6527/6622/6627/8527/8622/8627 devices; maintain this bit set. 2: unimplemented in pic18f6527/6622/8527/8622 devices; maintain this bit set. 3: unimplemented in pic18f6527/8527 devices; maintain this bit set. 4: boot block size is determined by the bbsiz<1:0> bits in config4l. legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
pic18f8722 family ds39646b-page 306 preliminary ? 2004 microchip technology inc. register 25-8: config5h: configuration register 5 high (byte address 300009h) r/c-1 r/c-1 u-0 u-0 u-0 u-0 u-0 u-0 cpd cpb ? ? ? ? ? ? bit 7 bit 0 bit 7 cpd: data eeprom code protection bit 1 = data eeprom not code-protected 0 = data eeprom code-protected bit 6 cpb: boot block code protection bit 1 = boot block (000000-0007ffh) not code-protected 0 = boot block (000000-0007ffh) code-protected bit 5-0 unimplemented: read as ? 0 ? legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
? 2004 microchip technology inc. preliminary ds39646b-page 307 pic18f8722 family register 25-9: config6l: configuration register 6 low (byte address 30000ah) r/c-1 r/c-1 r/c-1 r/c-1 r/c-1 r/c-1 r/c-1 r/c-1 wrt7 wrt6 wrt5 (2) wrt4 (2) wrt3 (3) wrt2 wrt1 wrt0 bit 7 bit 0 bit 7 wrt7: write protection bit (1) 1 = block 7 (01c000-01ffffh) not write-protected 0 = block 7 (01c000-01ffffh) write-protected bit 6 wrt6: write protection bit (1) 1 = block 6 (01bfff-018000h) not write-protected 0 = block 6 (01bfff-018000h) write-protected bit 5 wrt5: write protection bit (2) 1 = block 5 (014000-017fffh) not write-protected 0 = block 5 (014000-017fffh) write-protected bit 4 wrt4: write protection bit (2) 1 = block 4 (010000-013fffh) not write-protected 0 = block 4 (010000-013fffh) write-protected bit 3 wrt3: write protection bit (3) 1 = block 3 (00c000-00ffffh) not write-protected 0 = block 3 (00c000-00ffffh) write-protected bit 2 wrt2: write protection bit 1 = block 2 (008000-00bfffh) not write-protected 0 = block 2 (008000-00bfffh) write-protected bit 1 wrt1: write protection bit 1 = block 1 (004000-007fffh) not write-protected 0 = block 1 (004000-007fffh) write-protected bit 0 wrt0: write protection bit 1 = block 0 (000800, 001000 or 002000 (4) -003fffh) not write-protected 0 = block 0 (000800, 001000 or 002000 (4) -003fffh) write-protected note 1: unimplemented in pic18f6527/6622/6627/8527/8622/8627 devices; maintain this bit set. 2: unimplemented in pic18f6527/6622/8527/8622 devices; maintain this bit set. 3: unimplemented in pic18f6527/8527 devices; maintain this bit set. 4: boot block size is determined by the bbsiz<1:0> bits in config4l. legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
pic18f8722 family ds39646b-page 308 preliminary ? 2004 microchip technology inc. register 25-10: config6h: configuration register 6 high (byte address 30000bh) r/c-1 r/c-1 r-1 u-0 u-0 u-0 u-0 u-0 wrtd wrtb wrtc (1) ? ? ? ? ? bit 7 bit 0 bit 7 wrtd: data eeprom write protection bit 1 = data eeprom not write-protected 0 = data eeprom write-protected bit 6 wrtb: boot block write protection bit 1 = boot block (000000-007fff, 000fff or 001fffh (1) ) not write-protected 0 = boot block (000000-007fff, 000fff or 001fffh (1) ) write-protected bit 5 wrtc: configuration register write protection bit (2) 1 = configuration registers (300000-3000ffh) not write-protected 0 = configuration registers (300000-3000ffh) write-protected bit 4-0 unimplemented: read as ? 0 ? note 1: boot block size is determined by the bbsiz<1:0> bits in config4l. 2: this bit is read-only in normal execution mode; it can be written only in program mode. legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
? 2004 microchip technology inc. preliminary ds39646b-page 309 pic18f8722 family register 25-11: config7l: configuration register 7 low (byte address 30000ch) r/c-1 r/c-1 r/c-1 r/c-1 r/c-1 r/c-1 r/c-1 r/c-1 ebtr7 (1) ebtr6 (1) ebtr5 (2) ebtr4 (2) ebtr3 (3) ebtr2 ebtr1 ebtr0 bit 7 bit 0 bit 7 ebtr7: table read protection bit (1) 1 = block 7 (01c000-01ffffh) not protected from table reads executed in other blocks 0 = block 7 (01c000-01ffffh) protected from table reads executed in other blocks bit 6 ebtr6: table read protection bit (1) 1 = block 6 (018000-01bfffh) not protected from table reads executed in other blocks 0 = block 6 (018000-01bfffh) protected from table reads executed in other blocks bit 5 ebtr5: table read protection bit (2) 1 = block 5 (014000-017fffh) not protected from table reads executed in other blocks 0 = block 5 (014000-017fffh) protected from table reads executed in other blocks bit 4 ebtr4: table read protection bit (2) 1 = block 4 (010000-013fffh) not protected from table reads executed in other blocks 0 = block 4 (010000-013fffh) protected from table reads executed in other blocks bit 3 ebtr3: table read protection bit (3) 1 = block 3 (00c000-00ffffh) not protected from table reads executed in other blocks 0 = block 3 (00c000-00ffffh) protected from table reads executed in other blocks bit 2 ebtr2 : table read protection bit 1 = block 2 (008000-00bfffh) not protected from table reads executed in other blocks 0 = block 2 (008000-00bfffh) protected from table reads executed in other blocks bit 1 ebtr1: table read protection bit 1 = block 1 (004000-007fffh) not protected from table reads executed in other blocks 0 = block 1 (004000-007fffh) protected from table reads executed in other blocks bit 0 ebtr0: table read protection bit 1 = block 0 (000800, 001000 or 002000 (4) -003fffh) not protected from table reads executed in other blocks 0 = block 0 (000800, 001000 or 002000 (4) -003fffh) protected from table reads executed in other blocks note 1: unimplemented in pic18f6527/6622/6627/8527/8622/8627 devices; maintain this bit set. 2: unimplemented in pic18f6527/6622/8527/8622 devices; maintain this bit set. 3: unimplemented in pic18f6527/8527 devices; maintain this bit set. 4: boot block size is determined by the bbsiz<1:0> bit in config4l. legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
pic18f8722 family ds39646b-page 310 preliminary ? 2004 microchip technology inc. register 25-12: config7h: configuration register 7 high (byte address 30000dh) u-0 r/c-1 u-0 u-0 u-0 u-0 u-0 u-0 ? ebtrb ? ? ? ? ? ? bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 ebtrb: boot block table read protection bit 1 = boot block (000000-007fff, 000fff or 001fffh (1) ) not protected from table reads executed in other blocks 0 = boot block (000000-007fff, 000fff or 001fffh (1) ) protected from table reads executed in other blocks bit 5-0 unimplemented: read as ? 0 ? note 1: boot block size is determined by the bbsiz<1:0> bits in config4l. legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
? 2004 microchip technology inc. preliminary ds39646b-page 311 pic18f8722 family register 25-13: devid1: device id register 1 for the pic18f8722 family register 25-14: devid2: device id register 2 for the pic18f8722 family rrrrrrrr dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 bit 7 bit 0 bit 7-5 dev2:dev0: device id bits 001 = pic18f8722 111 = pic18f8627 101 = pic18f8622 011 = pic18f8527 000 = pic18f6722 110 = pic18f6627 100 = pic18f6622 010 = pic18f6527 bit 4-0 rev4:rev0: revision id bits these bits are used to indicate the device revision. legend: r = read-only bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state rrrrrrrr dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 bit 7 bit 0 bit 7-0 dev10:dev3: device id bits these bits are used with the dev2:dev0 bits in the device id register 1 to identify the part number. 0001 0100 = pic18f6722/8722 devices 0001 0011 = pic18f6527/6622/6627/8527/8622/8627 devices note: these values for dev10:dev3 may be shared with other devices. the specific device is always identified by using the entire dev10:dev0 bit sequence. legend: r = read-only bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
pic18f8722 family ds39646b-page 312 preliminary ? 2004 microchip technology inc. 25.2 watchdog timer (wdt) for the pic18f8722 family of devices, the wdt is driven by the intrc source. when the wdt is enabled, the clock source is also enabled. the nominal wdt period is 4 ms and has the same stability as the intrc oscillator. the 4 ms period of the wdt is multiplied by a 16-bit postscaler. any output of the wdt postscaler is selected by a multiplexor, controlled by bits in configuration register 2h. available periods range from 4 ms to 131.072 seconds (2.18 minutes). the wdt and postscaler are cleared when any of the following events occur: a sleep or clrwdt instruction is executed, the ircf bits (osccon<6:4>) are changed or a clock failure has occurred. 25.2.1 control register register 25-15 shows the wdtcon register. this is a readable and writable register which contains a control bit that allows software to override the wdt enable configuration bit, but only if the configuration bit has disabled the wdt. figure 25-1: wdt block diagram note 1: the clrwdt and sleep instructions clear the wdt and postscaler counts when executed. 2: changing the setting of the ircf bits (osccon<6:4>) clears the wdt and postscaler counts. 3: when a clrwdt instruction is executed, the postscaler count will be cleared. intrc source wdt wake-up from reset wdt counter programmable postscaler 1:1 to 1:32,768 enable wdt wdtps<4:1> swdten wdten clrwdt 4 power-managed reset all device resets sleep 128 change on ircf bits modes
? 2004 microchip technology inc. preliminary ds39646b-page 313 pic18f8722 family register 25-15: wdtcon: watchdog timer control register table 25-2: summary of watchdog timer registers u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?swdten (1) bit 7 bit 0 bit 7-1 unimplemented : read as ? 0 ? bit 0 swdten: software controlled watchdog timer enable bit (1) 1 = watchdog timer is on 0 = watchdog timer is off note 1: this bit has no effect if the configuration bit, wdten, is enabled. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por name bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 reset values on page rcon ipen sboren ? ri to pd por bor 56 wdtcon ? ? ? ? ? ? ?swdten58 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the watchdog timer.
pic18f8722 family ds39646b-page 314 preliminary ? 2004 microchip technology inc. 25.3 two-speed start-up the two-speed start-up feature helps to minimize the latency period from oscillator start-up to code execution by allowing the microcontroller to use the intosc oscillator as a clock source until the primary clock source is available. it is enabled by setting the ieso configuration bit. two-speed start-up should be enabled only if the primary oscillator mode is lp, xt, hs or hspll (crystal-based modes). other sources do not require an ost start-up delay; for these, two-speed start-up should be disabled. when enabled, resets and wake-ups from sleep mode cause the device to configure itself to run from the internal oscillator block as the clock source, following the time-out of the power-up timer after a power-on reset is enabled. this allows almost immediate code execution while the primary oscillator starts and the ost is running. once the ost times out, the device automatically switches to pri_run mode. to use a higher clock speed on wake-up, the intosc or postscaler clock sources can be selected to provide a higher clock speed by setting bits ircf2:ircf0 immediately after reset. for wake-ups from sleep, the intosc or postscaler clock sources can be selected by setting the ircf2:ircf0 bits prior to entering sleep mode. in all other power-managed modes, two-speed start- up is not used. the device will be clocked by the currently selected clock source until the primary clock source becomes available. the setting of the ieso bit is ignored. 25.3.1 special considerations for using two-speed start-up while using the intosc oscillator in two-speed start- up, the device still obeys the normal command sequences for entering power-managed modes, including multiple sleep instructions (refer to section 3.1.4 ?multiple sleep commands? ). in practice, this means that user code can change the scs1:scs0 bit settings or issue sleep instructions before the ost times out. this would allow an application to briefly wake-up, perform routine ?housekeeping? tasks and return to sleep before the device starts to operate from the primary oscillator. user code can also check if the primary clock source is currently providing the device clocking by checking the status of the osts bit (osccon<3>). if the bit is set, the primary oscillator is providing the clock. otherwise, the internal oscillator block is providing the clock during wake-up from reset or sleep mode. figure 25-2: timing transition for two-speed start-up (intosc to hspll) q1 q3 q4 osc1 peripheral program pc pc + 2 intosc pll clock q1 pc + 6 q2 output q3 q4 q1 cpu clock pc + 4 clock counter q2 q2 q3 note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. 2: clock transition typically occurs within 2-4 t osc . wake from interrupt event t pll (1) 12 n-1n clock osts bit set transition (2) multiplexor t ost (1)
? 2004 microchip technology inc. preliminary ds39646b-page 315 pic18f8722 family 25.4 fail-safe clock monitor the fail-safe clock monitor (fscm) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. the fscm function is enabled by setting the fcmen configuration bit. when fscm is enabled, the intrc oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure. clock monitoring (shown in figure 25-3) is accomplished by creating a sample clock signal, which is the intrc out- put divided by 64. this allows ample time between fscm sample clocks for a peripheral clock edge to occur. the peripheral device clock and the sample clock are presented as inputs to the clock monitor latch (cm). the cm is set on the falling edge of the device clock source, but cleared on the rising edge of the sample clock. figure 25-3: fscm block diagram clock failure is tested for on the falling edge of the sample clock. if a sample clock falling edge occurs while cm is still set, a clock failure has been detected (figure 25-4). this causes the following: the fscm generates an oscillator fail interrupt by setting bit, oscfif (pir2<7>); the device clock source is switched to the internal oscillator block (osccon is not updated to show the current clock source ? this is the fail-safe condition) and the wdt is reset. during switchover, the postscaler frequency from the internal oscillator block may not be sufficiently stable for timing sensitive applications. in these cases, it may be desirable to select another clock configuration and enter an alternate power-managed mode. this can be done to attempt a partial recovery or execute a controlled shut- down. see section 3.1.4 ?multiple sleep commands? and section 25.3.1 ?special considerations for using two-speed start-up? for more details. to use a higher clock speed on wake-up, the intosc or postscaler clock sources can be selected to provide a higher clock speed by setting bits, ircf2:ircf0, immediately after reset. for wake-ups from sleep, the intosc or postscaler clock sources can be selected by setting the ircf2:ircf0 bits prior to entering sleep mode. the fscm will detect failures of the primary or second- ary clock sources only. if the internal oscillator block fails, no failure would be detected, nor would any action be possible. 25.4.1 fscm and the watchdog timer both the fscm and the wdt are clocked by the intrc oscillator. since the wdt operates with a separate divider and counter, disabling the wdt has no effect on the operation of the intrc oscillator when the fscm is enabled. as already noted, the clock source is switched to the intosc clock when a clock failure is detected. depending on the frequency selected by the ircf2:ircf0 bits, this may mean a substantial change in the speed of code execution. if the wdt is enabled with a small prescale value, a decrease in clock speed allows a wdt time-out to occur and a subsequent device reset. for this reason, fail-safe clock events also reset the wdt and postscaler, allowing it to start timing from when execution speed was changed and decreasing the likelihood of an erroneous time-out. 25.4.2 exiting fail-safe operation the fail-safe condition is terminated by either a device reset or by entering a power-managed mode. on reset, the controller starts the primary clock source specified in configuration register 1h (with any required start-up delays that are required for the oscillator mode, such as ost or pll timer). the intosc multiplexor provides the device clock until the primary clock source becomes ready (similar to a two- speed start-up). the clock source is then switched to the primary clock (indicated by the osts bit in the osccon register becoming set). the fail-safe clock monitor then resumes monitoring the peripheral clock. the primary clock source may never become ready during start-up. in this case, operation is clocked by the intosc multiplexor. the osccon register will remain in its reset state until a power-managed mode is entered. peripheral intrc 64 s c q (32 s) 488 hz (2.048 ms) clock monitor latch (cm) (edge-triggered) clock failure detected source clock q
pic18f8722 family ds39646b-page 316 preliminary ? 2004 microchip technology inc. figure 25-4: fscm timing diagram 25.4.3 fscm interrupts in power-managed modes by entering a power-managed mode, the clock multiplexor selects the clock source selected by the osccon register. fail-safe monitoring of the power- managed clock source resumes in the power-managed mode. if an oscillator failure occurs during power-managed operation, the subsequent events depend on whether or not the oscillator failure interrupt is enabled. if enabled (oscfif = 1 ), code execution will be clocked by the intosc multiplexer. an automatic transition back to the failed clock source will not occur. if the interrupt is disabled, subsequent interrupts while in idle mode will cause the cpu to begin executing instructions while being clocked by the intosc source. 25.4.4 por or wake from sleep the fscm is designed to detect oscillator failure at any point after the device has exited power-on reset (por) or low-power sleep mode. when the primary device clock is ec, rc or intrc modes, monitoring can begin immediately following these events. for oscillator modes involving a crystal or resonator (hs, hspll, lp or xt), the situation is somewhat different. since the oscillator may require a start-up time considerably longer than the fcsm sample clock time, a false clock failure may be detected. to prevent this, the internal oscillator block is automatically config- ured as the device clock and functions until the primary clock is stable (the ost and pll timers have timed out). this is identical to two-speed start-up mode. once the primary clock is stable, the intrc returns to its role as the fscm source. as noted in section 25.3.1 ?special considerations for using two-speed start-up? , it is also possible to select another clock configuration and enter an alternate power-managed mode while waiting for the primary clock to become stable. when the new power- managed mode is selected, the primary clock is disabled. oscfif cm output device clock output sample clock failure detected oscillator failure note: the device clock is normally at a mu ch higher frequency than the sample clock. the relative frequencies in this example have been chosen for clarity. (q ) cm test cm test cm test note: the same logic that prevents false oscilla- tor failure interrupts on por, or wake from sleep, will also prevent the detection of the oscillator?s failure to start at all follow- ing these events. this can be avoided by monitoring the osts bit and using a timing routine to determine if the oscillator is taking too long to start. even so, no oscillator failure interrupt will be flagged.
? 2004 microchip technology inc. preliminary ds39646b-page 317 pic18f8722 family 25.5 program verification and code protection the user program memory is divided into four blocks for pic18f6527/8527 devices, five blocks for pic18f6622/8622 devices, six blocks for pic18f6627/ 8627 devices and eight blocks for pic18f6722/8722 devices. one of these is a boot block of 2, 4 or 8 kbytes. the remainder of the memory is divided into blocks on binary boundaries. each of the blocks has three code protection bits associated with them. they are: code-protect bit (cpn) write-protect bit (wrtn) external block table read bit (ebtrn) figure 25-5 shows the program memory organization for 48, 64, 96 and 128-kbyte devices and the specific code protection bit associated with each block. the actual locations of the bits are summarized in table 25-3. figure 25-5: code-protected program memory for the pic18f8722 family 000000h 200000h 3fffffh 01ffffh note: sizes of memory areas are not to scale. * boot block size is determined by the bbsiz<1:0> bits in config4l. code memory unimplemented read as ? 0 ? configuration and id space memory size/device 128 kbytes (pic18fx722) 96 kbytes (pic18fx627) 64 kbytes (pic18fx622) 48 kbytes (pic18fx527) address range boot block boot block boot block boot block 000000h 0007ffh* or 000fffh* or 001fffh* block 0 block 0 block 0 block 0 000800h* or 001000h* or 002000h* 003fffh block 1 block 1 block 1 block 1 004000h 007fffh block 2 block 2 block 2 block 2 008000h 00bfffh block 3 block 3 block 3 unimplemented read ? 0 ?s 00c000h 00ffffh block 4 block 4 unimplemented read ? 0 ?s 010000h 013fffh block 5 block 5 014000h 017fffh block 6 unimplemented read ? 0 ?s 018000h 01bfffh block 7 01c000h 01ffffh
pic18f8722 family ds39646b-page 318 preliminary ? 2004 microchip technology inc. table 25-3: summary of code protection registers 25.5.1 program memory code protection the program memory may be read to or written from any location using the table read and table write instructions. the device id may be read with table reads. the configuration registers may be read and written with the table read and table write instructions. in normal execution mode, the cpn bits have no direct effect. cpn bits inhibit external reads and writes. a block of user memory may be protected from table writes if the wrtn configuration bit is ? 0 ?. the ebtrn bits control table reads. for a block of user memory with the ebtrn bit set to ? 0 ?, a table read instruction that executes from within that block is allowed to read. a table read instruc- tion that executes from a location outside of that block is not allowed to read and will result in reading ? 0 ?s. figures 25-6 through 25-8 illustrate table write and table read protection. figure 25-6: table write (wrtn) disallowed file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 300008h config5l cp7 (1) cp6 (1) cp5 (2) cp4 (2) cp3 (3) cp2 cp1 cp0 300009h config5h cpd cpb ? ? ? ? ? ? 30000ah config6l wrt7 (1) wrt6 (1) wrt5 (2) wrt4 (2) wrt3 (3) wrt2 wrt1 wrt0 30000bh config6h wrtd wrtb wrtc ? ? ? ? ? 30000ch config7l ebrt7 (1) ebrt6 (1) ebtr5 (2) ebtr4 (2) ebtr3 (3) ebtr2 ebtr1 ebtr0 30000dh config7h ? ebtrb ? ? ? ? ? ? legend: shaded cells are unimplemented. note 1: unimplemented in pic18f6527/6622/6627/8527/8622/8627 devices; maintain this bit set. 2: unimplemented in pic18f6527/6622/8527/8622 devices; maintain this bit set. 3: unimplemented in pic18f6527/8527 devices; maintain this bit set. note: code protection bits may only be written to a ? 0 ? from a ? 1 ? state. it is not possible to write a ? 1 ? to a bit in the ? 0 ? state. code protection bits are only set to ? 1 ? by a full chip erase or block erase function. the full chip erase and block erase functions can only be initiated via icsp or an external programmer. refer to the device programming specification for more information. 000000h 0007ffh 000800h 003fffh 004000h 007fffh 008000h 00bfffh 00c000h 00ffffh wrtb, ebtrb = 11 wrt0, ebtr0 = 01 wrt1, ebtr1 = 11 wrt2, ebtr2 = 11 wrt3, ebtr3 = 11 tblwt* tblptr = 0008ffh pc = 003ffeh tblwt* pc = 00bffeh register values program memory configuration bit settings results: all table writes disabled to blockn whenever wrtn = 0 .
? 2004 microchip technology inc. preliminary ds39646b-page 319 pic18f8722 family figure 25-7: external block table read (ebtrn) disallowed figure 25-8: external block table read (ebtrn) allowed wrtb, ebtrb = 11 wrt0, ebtr0 = 10 wrt1, ebtr1 = 11 wrt2, ebtr2 = 11 wrt3, ebtr3 = 11 tblrd* tblptr = 0008ffh pc = 007ffeh results: all table reads from external blocks to blockn are disabled whenever ebtrn = 0 . tablat register returns a value of ? 0 ?. register values program memory configuration bit settings 000000h 0007ffh 000800h 003fffh 004000h 007fffh 008000h 00bfffh 00c000h 00ffffh wrtb, ebtrb = 11 wrt0, ebtr0 = 10 wrt1, ebtr1 = 11 wrt2, ebtr2 = 11 wrt3, ebtr3 = 11 tblrd* tblptr = 0008ffh pc = 003ffeh register values program memory configuration bit settings results: table reads permitted within blockn, even when ebtrbn = 0 . tablat register returns the value of the data at the location tblptr. 000000h 0007ffh 000800h 003fffh 004000h 007fffh 008000h 00bfffh 00c000h 00ffffh
pic18f8722 family ds39646b-page 320 preliminary ? 2004 microchip technology inc. 25.5.2 data eeprom code protection the entire data eeprom is protected from external reads and writes by two bits: cpd and wrtd. cpd inhibits external reads and writes of data eeprom. wrtd inhibits internal and external writes to data eeprom. the cpu can always read data eeprom under normal operation, regardless of the protection bit settings. 25.5.3 configuration register protection the configuration registers can be write-protected. the wrtc bit controls protection of the configuration registers. in normal execution mode, the wrtc bit is readable only. wrtc can only be written via icsp or an external programmer. 25.6 id locations eight memory locations (200000h-200007h) are designated as id locations, where the user can store checksum or other code identification numbers. these locations are both readable and writable during normal execution through the tblrd and tblwt instructions or during program/verify. the id locations can be read when the device is code-protected. 25.7 in-circuit serial programming the pic18f8722 family of devices can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. this allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. 25.8 in-circuit debugger when the debug configuration bit is programmed to a ? 0 ?, the in-circuit debugger functionality is enabled. this function allows simple debugging functions when used with mplab ? ide. when the microcontroller has this feature enabled, some resources are not available for general use. table 25-4 shows which resources are required by the background debugger. table 25-4: debugger resources to use the in-circuit debugger function of the micro- controller, the design must implement in-circuit serial programming connections to rg5/mclr /v pp , v dd , v ss , rb7 and rb6. this will interface to the in-circuit debugger module available from microchip or one of the third party development tool companies. 25.9 single-supply icsp programming the lvp configuration bit enables single-supply icsp programming (formerly known as low-voltage icsp programming or lvp). when single-supply program- ming is enabled, the microcontroller can be programmed without requiring high voltage being applied to the rg5/mclr /v pp pin, but the rb5/kbi1/pgm pin is then dedicated to controlling program mode entry and is not available as a general purpose i/o pin. while programming, using single-supply programming mode, v dd is applied to the rg5/mclr /v pp pin as in normal execution mode. to enter programming mode, v dd is applied to the pgm pin. if single-supply icsp programming mode will not be used, the lvp bit can be cleared. rb5/kbi1/pgm then becomes available as the digital i/o pin, rb5. the lvp bit may be set or cleared only when using standard high-voltage programming (v ihh applied to the rg5/ mclr /v pp pin). once lvp has been disabled, only the standard high-voltage programming is available and must be used to program the device. memory that is not code-protected can be erased using a block erase, or erased row by row, then written at any specified v dd . if code-protected memory is to be erased, a block erase is required. if a block erase is to be performed when using low-voltage programming, the device must be supplied with v dd of 4.5v to 5.5v. i/o pins: rb6, rb7 stack: 2 levels program memory: 512 bytes data memory: 10 bytes note 1: high-voltage programming is always available, regardless of the state of the lvp bit or the pgm pin, by applying v ihh to the mclr pin. 2: by default, single-supply icsp is enabled in unprogrammed devices (as supplied from microchip) and erased devices. 3: when single-supply programming is enabled, the rb5 pin can no longer be used as a general purpose i/o pin. 4: when lvp is enabled, externally pull the pgm pin to v ss to allow normal program execution.
? 2004 microchip technology inc. ds39646b-page 321 pic18f8722 family 26.0 instruction set summary the pic18f8722 family of devices incorporates the standard set of 75 pic18 core instructions, as well as an extended set of 8 new instructions for the optimiza- tion of code that is recursive or that utilizes a software stack. the extended set is discussed later in this section. 26.1 standard instruction set the standard pic18 instruction set adds many enhancements to the previous picmicro ? instruction sets, while maintaining an easy migration from these picmicro instruction sets. most instructions are a single program memory word (16 bits), but there are four instructions that require two program memory locations. each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into four basic categories: byte-oriented operations bit-oriented operations literal operations control operations the pic18 instruction set summary in table 26-2 lists byte-oriented , bit-oriented , literal and control operations. table 26-1 shows the opcode field descriptions. most byte-oriented instructions have three operands: 1. the file register (specified by ?f?) 2. the destination of the result (specified by ?d?) 3. the accessed memory (specified by ?a?) the file register designator ?f? specifies which file regis- ter is to be used by the instruction. the destination designator ?d? specifies where the result of the operation is to be placed. if ?d? is zero, the result is placed in the wreg register. if ?d? is one, the result is placed in the file register specified in the instruction. all bit-oriented instructions have three operands: 1. the file register (specified by ?f?) 2. the bit in the file register (specified by ?b?) 3. the accessed memory (specified by ?a?) the bit field designator ?b? selects the number of the bit affected by the operation, while the file register designator ?f? represents the number of the file in which the bit is located. the literal instructions may use some of the following operands: a literal value to be loaded into a file register (specified by ?k?) the desired fsr register to load the literal value into (specified by ?f?) no operand required (specified by ???) the control instructions may use some of the following operands: a program memory address (specified by ?n?) the mode of the call or return instructions (specified by ?s?) the mode of the table read and table write instructions (specified by ?m?) no operand required (specified by ???) all instructions are a single word, except for four double-word instructions. these instructions were made double-word to contain the required information in 32 bits. in the second word, the 4 msbs are 1 ?s. if this second word is executed as an instruction (by itself), it will execute as a nop . all single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruc- tion. in these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a nop . the double word instructions execute in two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 s. if a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. two-word branch instructions (if true) would take 3 s. figure 26-1 shows the general formats that the instruc- tions can have. all examples use the convention ?nnh? to represent a hexadecimal number. the instruction set summary, shown in table 26-2, lists the standard instructions recognized by the microchip mpasm tm assembler. section 26.1.1 ?standard instruction set? provides a description of each instruction.
pic18f8722 family ds39646b-page 322 ? 2004 microchip technology inc. table 26-1: opcode field descriptions field description a ram access bit: a = 0 : ram location in access ram (bsr register is ignored) a = 1 : ram bank is specified by bsr register bbb bit address within an 8-bit file register (0 to 7). bsr bank select register. used to select the current ram bank. c, dc, z, ov, n alu status bits: c arry, d igit c arry, z ero, ov erflow, n egative. d destination select bit: d = 0 : store result in wreg d = 1 : store result in file register f dest destination: either the wreg register or the specified register file location. f 8-bit register file address (00h to ffh), or 2-bit fsr designator (0h to 3h). f s 12-bit register file address (000h to ff fh). this is the source address. f d 12-bit register file address (000h to fffh). this is the destination address. gie global interrupt enable bit. k literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label label name. mm the mode of the tblptr register for the table read and table write instructions. only used with table read and table write instructions: * no change to register (such as tblptr with table reads and writes) *+ post-increment register (such as tblptr with table reads and writes) *- post-decrement register (such as tblptr with table reads and writes) +* pre-increment register (such as tb lptr with table reads and writes) n the relative address (2?s complement number) for relative branch instructions or the direct address for call/branch and return instructions. pc program counter. pcl program counter low byte. pch program counter high byte. pclath program counter high byte latch. pclatu program counter upper byte latch. pd power-down bit. prodh product of multiply high byte. prodl product of multiply low byte. s fast call/return mode select bit: s = 0 : do not update into/from shadow registers s = 1 : certain registers loaded into/from shadow registers (fast mode) tblptr 21-bit table pointer (points to a program memory location). tablat 8-bit table latch. to time-out bit. tos top-of-stack. u unused or unchanged. wdt watchdog timer. wreg working register (accumulator). x don?t care (? 0 ? or ? 1 ?). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. z s 7-bit offset value for indirect addr essing of register files (source). z d 7-bit offset value for indirect addressing of register files (destination). { } optional argument. [text] indicates an indexed address. (text) the contents of text . [expr] specifies bit n of the register indicated by the pointer expr . assigned to. < > register bit field. in the set of. italics user-defined term (font is courier).
? 2004 microchip technology inc. ds39646b-page 323 pic18f8722 family figure 26-1: general format for instructions byte-oriented file register operations 15 10 9 8 7 0 d = 0 for result destination to be wreg register opcode d a f (file #) d = 1 for result destination to be file register (f) a = 0 to force access bank bit-oriented file register operations 15 12 11 9 8 7 0 opcode b (bit #) a f (file #) b = 3-bit position of bit in file register (f) literal operations 15 8 7 0 opcode k (literal) k = 8-bit immediate value byte to byte move operations (2-word) 15 12 11 0 opcode f (source file #) call, goto and branch operations 15 8 7 0 opcode n<7:0> (literal) n = 20-bit immediate value a = 1 for bsr to select bank f = 8-bit file register address a = 0 to force access bank a = 1 for bsr to select bank f = 8-bit file register address 15 12 11 0 1111 n<19:8> (literal) 15 12 11 0 1111 f (destination file #) f = 12-bit file register address control operations example instruction addwf myreg, w, b movff myreg1, myreg2 bsf myreg, bit, b movlw 7fh goto label 15 8 7 0 opcode n<7:0> (literal) 15 12 11 0 1111 n<19:8> (literal) call myfunc 15 11 10 0 opcode n<10:0> (literal) s = fast bit bra myfunc 15 8 7 0 opcode n<7:0> (literal) bc myfunc s
pic18f8722 family ds39646b-page 324 ? 2004 microchip technology inc. table 26-2: pic18fxxxx instruction set mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb byte-oriented operations addwf addwfc andwf clrf comf cpfseq cpfsgt cpfslt decf decfsz dcfsnz incf incfsz infsnz iorwf movf movff movwf mulwf negf rlcf rlncf rrcf rrncf setf subfwb subwf subwfb swapf tstfsz xorwf f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f s , f d f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a add wreg and f add wreg and carry bit to f and wreg with f clear f complement f compare f with wreg, skip = compare f with wreg, skip > compare f with wreg, skip < decrement f decrement f, skip if 0 decrement f, skip if not 0 increment f increment f, skip if 0 increment f, skip if not 0 inclusive or wreg with f move f move f s (source) to 1st word f d (destination) 2nd word move wreg to f multiply wreg with f negate f rotate left f through carry rotate left f (no carry) rotate right f through carry rotate right f (no carry) set f subtract f from wreg with borrow subtract wreg from f subtract wreg from f with borrow swap nibbles in f test f, skip if 0 exclusive or wreg with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 (2 or 3) 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 0101 0101 0011 0110 0001 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da 11da 10da 10da 011a 10da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff c, dc, z, ov, n c, dc, z, ov, n z, n z z, n none none none c, dc, z, ov, n none none c, dc, z, ov, n none none z, n z, n none none none c, dc, z, ov, n c, z, n z, n c, z, n z, n none c, dc, z, ov, n c, dc, z, ov, n c, dc, z, ov, n none none z, n 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1 1, 2 1, 2 1, 2 1, 2 4 1, 2 note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are two-word instructions. the second word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction.
? 2004 microchip technology inc. ds39646b-page 325 pic18f8722 family bit-oriented operations bcf bsf btfsc btfss btg f, b, a f, b, a f, b, a f, b, a f, b, a bit clear f bit set f bit test f, skip if clear bit test f, skip if set bit toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff none none none none none 1, 2 1, 2 3, 4 3, 4 1, 2 control operations bc bn bnc bnn bnov bnz bov bra bz call clrwdt daw goto nop nop pop push rcall reset retfie retlw return sleep n n n n n n n n n n, s ? ? n ? ? ? ? n s k s ? branch if carry branch if negative branch if not carry branch if not negative branch if not overflow branch if not zero branch if overflow branch unconditionally branch if zero call subroutine 1st word 2nd word clear watchdog timer decimal adjust wreg go to address 1st word 2nd word no operation no operation pop top of return stack (tos) push top of return stack (tos) relative call software device reset return from interrupt enable return with literal in wreg return from subroutine go into standby mode 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s kkkk 001s 0011 none none none none none none none none none none to , pd c none none none none none none all gie/gieh, peie/giel none none to , pd 4 table 26-2: pic18fxxxx instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are two-word instructions. the second word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction.
pic18f8722 family ds39646b-page 326 ? 2004 microchip technology inc. literal operations addlw andlw iorlw lfsr movlb movlw mullw retlw sublw xorlw k k k f, k k k k k k k add literal and wreg and literal with wreg inclusive or literal with wreg move literal (12-bit) 2nd word to fsr(f) 1st word move literal to bsr<3:0> move literal to wreg multiply literal with wreg return with literal in wreg subtract wreg from literal exclusive or literal with wreg 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk c, dc, z, ov, n z, n z, n none none none none none c, dc, z, ov, n z, n data memory ? program memory operations tblrd* tblrd*+ tblrd*- tblrd+* tblwt* tblwt*+ tblwt*- tblwt+* table read table read with post-increment table read with post-decrement table read with pre-increment table write table write with post-increment table write with post-decrement table write with pre-increment 2 2 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 none none none none none none none none 5 5 5 5 table 26-2: pic18fxxxx instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are two-word instructions. the second word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction.
? 2004 microchip technology inc. ds39646b-page 327 pic18f8722 family 26.1.1 standard instruction set addlw add literal to w syntax: addlw k operands: 0 k 255 operation: (w) + k w status affected: n, ov, c, dc, z encoding: 0000 1111 kkkk kkkk description: the contents of w are added to the 8-bit literal ?k? and the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: addlw 15h before instruction w = 10h after instruction w = 25h addwf add w to f syntax: addwf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (w) + (f) dest status affected: n, ov, c, dc, z encoding: 0010 01da ffff ffff description: add w to register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: addwf reg, 0, 0 before instruction w = 17h reg = 0c2h after instruction w = 0d9h reg = 0c2h note: all pic18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. if a label is used, the instruction format then becomes: {label} instruction argument(s).
pic18f8722 family ds39646b-page 328 ? 2004 microchip technology inc. addwfc add w and carry bit to f syntax: addwfc f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (w) + (f) + (c) dest status affected: n,ov, c, dc, z encoding: 0010 00da ffff ffff description: add w, the carry flag and data memory location ?f?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed in data memory location ?f?. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: addwfc reg, 0, 1 before instruction carry bit = 1 reg = 02h w=4dh after instruction carry bit = 0 reg = 02h w = 50h andlw and literal with w syntax: andlw k operands: 0 k 255 operation: (w) .and. k w status affected: n, z encoding: 0000 1011 kkkk kkkk description: the contents of w are anded with the 8-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: andlw 05fh before instruction w=a3h after instruction w = 03h
? 2004 microchip technology inc. ds39646b-page 329 pic18f8722 family andwf and w with f syntax: andwf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (w) .and. (f) dest status affected: n, z encoding: 0001 01da ffff ffff description: the contents of w are anded with register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: andwf reg, 0, 0 before instruction w = 17h reg = c2h after instruction w = 02h reg = c2h bc branch if carry syntax: bc n operands: -128 n 127 operation: if carry bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0010 nnnn nnnn description: if the carry bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bc 5 before instruction pc = address (here) after instruction if carry = 1; pc = address (here + 12) if carry = 0; pc = address (here + 2)
pic18f8722 family ds39646b-page 330 ? 2004 microchip technology inc. bcf bit clear f syntax: bcf f, b {,a} operands: 0 f 255 0 b 7 a [0,1] operation: 0 f status affected: none encoding: 1001 bbba ffff ffff description: bit ?b? in register ?f? is cleared. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: bcf flag_reg, 7, 0 before instruction flag_reg = c7h after instruction flag_reg = 47h bn branch if negative syntax: bn n operands: -128 n 127 operation: if negative bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0110 nnnn nnnn description: if the negative bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bn jump before instruction pc = address (here) after instruction if negative = 1; pc = address (jump) if negative = 0; pc = address (here + 2)
? 2004 microchip technology inc. ds39646b-page 331 pic18f8722 family bnc branch if not carry syntax: bnc n operands: -128 n 127 operation: if carry bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0011 nnnn nnnn description: if the carry bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnc jump before instruction pc = address (here) after instruction if carry = 0; pc = address (jump) if carry = 1; pc = address (here + 2) bnn branch if not negative syntax: bnn n operands: -128 n 127 operation: if negative bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0111 nnnn nnnn description: if the negative bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnn jump before instruction pc = address (here) after instruction if negative = 0; pc = address (jump) if negative = 1; pc = address (here + 2)
pic18f8722 family ds39646b-page 332 ? 2004 microchip technology inc. bnov branch if not overflow syntax: bnov n operands: -128 n 127 operation: if overflow bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0101 nnnn nnnn description: if the overflow bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnov jump before instruction pc = address (here) after instruction if overflow = 0; pc = address (jump) if overflow = 1; pc = address (here + 2) bnz branch if not zero syntax: bnz n operands: -128 n 127 operation: if zero bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0001 nnnn nnnn description: if the zero bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnz jump before instruction pc = address (here) after instruction if zero = 0; pc = address (jump) if zero = 1; pc = address (here + 2)
? 2004 microchip technology inc. ds39646b-page 333 pic18f8722 family bra unconditional branch syntax: bra n operands: -1024 n 1023 operation: (pc) + 2 + 2n pc status affected: none encoding: 1101 0nnn nnnn nnnn description: add the 2?s complement number ?2n? to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation example: here bra jump before instruction pc = address (here) after instruction pc = address (jump) bsf bit set f syntax: bsf f, b {,a} operands: 0 f 255 0 b 7 a [0,1] operation: 1 f status affected: none encoding: 1000 bbba ffff ffff description: bit ?b? in register ?f? is set. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: bsf flag_reg, 7, 1 before instruction flag_reg = 0ah after instruction flag_reg = 8ah
pic18f8722 family ds39646b-page 334 ? 2004 microchip technology inc. btfsc bit test file, skip if clear syntax: btfsc f, b {,a} operands: 0 f 255 0 b 7 a [0,1] operation: skip if (f) = 0 status affected: none encoding: 1011 bbba ffff ffff description: if bit ?b? in register ?f? is ? 0 ?, then the next instruction is skipped. if bit ?b? is ? 0 ?, then the next instruction fetched during the current instruction execution is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here false true btfsc : : flag, 1, 0 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (true) if flag<1> = 1; pc = address (false) btfss bit test file, skip if set syntax: btfss f, b {,a} operands: 0 f 255 0 b < 7 a [0,1] operation: skip if (f) = 1 status affected: none encoding: 1010 bbba ffff ffff description: if bit ?b? in register ?f? is ? 1 ?, then the next instruction is skipped. if bit ?b? is ? 1 ?, then the next instruction fetched during the current instruction execution is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here false true btfss : : flag, 1, 0 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (false) if flag<1> = 1; pc = address (true)
? 2004 microchip technology inc. ds39646b-page 335 pic18f8722 family btg bit toggle f syntax: btg f, b {,a} operands: 0 f 255 0 b < 7 a [0,1] operation: (f ) f status affected: none encoding: 0111 bbba ffff ffff description: bit ?b? in data memory location ?f? is inverted. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: btg portc, 4, 0 before instruction: portc = 0111 0101 [75h] after instruction: portc = 0110 0101 [65h] bov branch if overflow syntax: bov n operands: -128 n 127 operation: if overflow bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0100 nnnn nnnn description: if the overflow bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bov jump before instruction pc = address (here) after instruction if overflow = 1; pc = address (jump) if overflow = 0; pc = address (here + 2)
pic18f8722 family ds39646b-page 336 ? 2004 microchip technology inc. bz branch if zero syntax: bz n operands: -128 n 127 operation: if zero bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0000 nnnn nnnn description: if the zero bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bz jump before instruction pc = address (here) after instruction if zero = 1; pc = address (jump) if zero = 0; pc = address (here + 2) call subroutine call syntax: call k {,s} operands: 0 k 1048575 s [0,1] operation: (pc) + 4 tos, k pc<20:1>, if s = 1 (w) ws, (status) statuss, (bsr) bsrs status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 110s k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: subroutine call of entire 2-mbyte memory range. first, return address (pc + 4) is pushed onto the return stack. if ?s? = 1 , the w, status and bsr registers are also pushed into their respective shadow registers, ws, statuss and bsrs. if ?s? = 0 , no update occurs (default). then, the 20-bit value ?k? is loaded into pc<20:1>. call is a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k?<7:0>, push pc to stack read literal ?k?<19:8>, write to pc no operation no operation no operation no operation example: here call there,1 before instruction pc = address (here) after instruction pc = address (there) tos = address (here + 4) ws = w bsrs = bsr statuss = status
? 2004 microchip technology inc. ds39646b-page 337 pic18f8722 family clrf clear f syntax: clrf f {,a} operands: 0 f 255 a [0,1] operation: 000h f 1 z status affected: z encoding: 0110 101a ffff ffff description: clears the contents of the specified register. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: clrf flag_reg,1 before instruction flag_reg = 5ah after instruction flag_reg = 00h clrwdt clear watchdog timer syntax: clrwdt operands: none operation: 000h wdt, 000h wdt postscaler, 1 to, 1 pd status affected: to , pd encoding: 0000 0000 0000 0100 description: clrwdt instruction resets the watchdog timer. it also resets the postscaler of the wdt. status bits, to and pd , are set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data no operation example: clrwdt before instruction wdt counter = ? after instruction wdt counter = 00h wdt postscaler = 0 to =1 pd =1
pic18f8722 family ds39646b-page 338 ? 2004 microchip technology inc. comf complement f syntax: comf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: dest status affected: n, z encoding: 0001 11da ffff ffff description: the contents of register ?f? are complemented. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: comf reg, 0, 0 before instruction reg = 13h after instruction reg = 13h w=ech (f ) cpfseq compare f with w, skip if f = w syntax: cpfseq f {,a} operands: 0 f 255 a [0,1] operation: (f) ? (w), skip if (f) = (w) (unsigned comparison) status affected: none encoding: 0110 001a ffff ffff description: compares the contents of data memory location ?f? to the contents of w by performing an unsigned subtraction. if ?f? = w , then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here cpfseq reg, 0 nequal : equal : before instruction pc address = here w=? reg = ? after instruction if reg = w; pc = address (equal) if reg w; pc = address (nequal)
? 2004 microchip technology inc. ds39646b-page 339 pic18f8722 family cpfsgt compare f with w, skip if f > w syntax: cpfsgt f {,a} operands: 0 f 255 a [0,1] operation: (f) ? ( w), skip if (f) > (w) (unsigned comparison) status affected: none encoding: 0110 010a ffff ffff description: compares the contents of data memory location ?f? to the contents of the w by performing an unsigned subtraction. if the contents of ?f? are greater than the contents of wreg , then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here cpfsgt reg, 0 ngreater : greater : before instruction pc = address (here) w= ? after instruction if reg > w; pc = address (greater) if reg w; pc = address (ngreater) cpfslt compare f with w, skip if f < w syntax: cpfslt f {,a} operands: 0 f 255 a [0,1] operation: (f) ? ( w), skip if (f) < (w) (unsigned comparison) status affected: none encoding: 0110 000a ffff ffff description: compares the contents of data memory location ?f? to the contents of w by performing an unsigned subtraction. if the contents of ?f? are less than the contents of w, then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here cpfslt reg, 1 nless : less : before instruction pc = address (here) w= ? after instruction if reg < w; pc = address (less) if reg w; pc = address (nless)
pic18f8722 family ds39646b-page 340 ? 2004 microchip technology inc. daw decimal adjust w register syntax: daw operands: none operation: if [w<3:0> > 9] or [dc = 1 ] then (w<3:0>) + 6 w<3:0>; else (w<3:0>) w<3:0> if [w<7:4> > 9] or [c = 1 ] then (w<7:4>) + 6 w<7:4>; c = 1 ; else (w<7:4>) w<7:4> status affected: c encoding: 0000 0000 0000 0111 description: daw adjusts the eight-bit value in w, resulting from the earlier addition of two variables (each in packed bcd format) and produces a correct packed bcd result. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register w process data write w example 1: daw before instruction w=a5h c=0 dc = 0 after instruction w = 05h c=1 dc = 0 example 2: before instruction w=ceh c=0 dc = 0 after instruction w = 34h c=1 dc = 0 decf decrement f syntax: decf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest status affected: c, dc, n, ov, z encoding: 0000 01da ffff ffff description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: decf cnt, 1, 0 before instruction cnt = 01h z=0 after instruction cnt = 00h z=1
? 2004 microchip technology inc. ds39646b-page 341 pic18f8722 family decfsz decrement f, skip if 0 syntax: decfsz f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest, skip if result = 0 status affected: none encoding: 0010 11da ffff ffff description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is ? 0 ?, the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here decfsz cnt, 1, 1 goto loop continue before instruction pc = address (here) after instruction cnt = cnt ? 1 if cnt = 0; pc = address (continue) if cnt 0; pc = address (here + 2) dcfsnz decrement f, skip if not 0 syntax: dcfsnz f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest, skip if result 0 status affected: none encoding: 0100 11da ffff ffff description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is not ? 0 ?, the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here dcfsnz temp, 1, 0 zero : nzero : before instruction temp = ? after instruction temp = temp ? 1, if temp = 0; pc = address (zero) if temp 0; pc = address (nzero)
pic18f8722 family ds39646b-page 342 ? 2004 microchip technology inc. goto unconditional branch syntax: goto k operands: 0 k 1048575 operation: k pc<20:1> status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: goto allows an unconditional branch anywhere within entire 2-mbyte memory range. the 20-bit value ?k? is loaded into pc<20:1>. goto is always a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k?<7:0>, no operation read literal ?k?<19:8>, write to pc no operation no operation no operation no operation example: goto there after instruction pc = address (there) incf increment f syntax: incf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest status affected: c, dc, n, ov, z encoding: 0010 10da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: incf cnt, 1, 0 before instruction cnt = ffh z=0 c=? dc = ? after instruction cnt = 00h z=1 c=1 dc = 1
? 2004 microchip technology inc. ds39646b-page 343 pic18f8722 family incfsz increment f, skip if 0 syntax: incfsz f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest, skip if result = 0 status affected: none encoding: 0011 11da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f?. (default) if the result is ? 0 ?, the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here incfsz cnt, 1, 0 nzero : zero : before instruction pc = address (here) after instruction cnt = cnt + 1 if cnt = 0; pc = address (zero) if cnt 0; pc = address (nzero) infsnz increment f, skip if not 0 syntax: infsnz f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest, skip if result 0 status affected: none encoding: 0100 10da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is not ? 0 ?, the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here infsnz reg, 1, 0 zero nzero before instruction pc = address (here) after instruction reg = reg + 1 if reg 0; pc = address (nzero) if reg = 0; pc = address (zero)
pic18f8722 family ds39646b-page 344 ? 2004 microchip technology inc. iorlw inclusive or literal with w syntax: iorlw k operands: 0 k 255 operation: (w) .or. k w status affected: n, z encoding: 0000 1001 kkkk kkkk description: the contents of w are ored with the eight-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: iorlw 35h before instruction w=9ah after instruction w=bfh iorwf inclusive or w with f syntax: iorwf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (w) .or. (f) dest status affected: n, z encoding: 0001 00da ffff ffff description: inclusive or w with register ?f?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: iorwf result, 0, 1 before instruction result = 13h w = 91h after instruction result = 13h w = 93h
? 2004 microchip technology inc. ds39646b-page 345 pic18f8722 family lfsr load fsr syntax: lfsr f, k operands: 0 f 2 0 k 4095 operation: k fsrf status affected: none encoding: 1110 1111 1110 0000 00ff k 7 kkk k 11 kkk kkkk description: the 12-bit literal ?k? is loaded into the file select register pointed to by ?f?. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k? msb process data write literal ?k? msb to fsrfh decode read literal ?k? lsb process data write literal ?k? to fsrfl example: lfsr 2, 3abh after instruction fsr2h = 03h fsr2l = abh movf move f syntax: movf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: f dest status affected: n, z encoding: 0101 00da ffff ffff description: the contents of register ?f? are moved to a destination dependent upon the status of ?d?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). location ?f? can be anywhere in the 256-byte bank. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write w example: movf reg, 0, 0 before instruction reg = 22h w=ffh after instruction reg = 22h w = 22h
pic18f8722 family ds39646b-page 346 ? 2004 microchip technology inc. movff move f to f syntax: movff f s ,f d operands: 0 f s 4095 0 f d 4095 operation: (f s ) f d status affected: none encoding: 1st word (source) 2nd word (destin.) 1100 1111 ffff ffff ffff ffff ffff s ffff d description: the contents of source register ?f s ? are moved to destination register ?f d ?. location of source ?f s ? can be anywhere in the 4096-byte data space (000h to fffh) and location of destination ?f d ? can also be anywhere from 000h to fffh. either source or destination can be w (a useful special situation). movff is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an i/o port). the movff instruction cannot use the pcl, tosu, tosh or tosl as the destination register words: 2 cycles: 2 (3) q cycle activity: q1 q2 q3 q4 decode read register ?f? (src) process data no operation decode no operation no dummy read no operation write register ?f? (dest) example: movff reg1, reg2 before instruction reg1 = 33h reg2 = 11h after instruction reg1 = 33h reg2 = 33h movlb move literal to low nibble in bsr syntax: movlw k operands: 0 k 255 operation: k bsr status affected: none encoding: 0000 0001 kkkk kkkk description: the eight-bit literal ?k? is loaded into the bank select register (bsr). the value of bsr<7:4> always remains ? 0 ? regardless of the value of k 7 :k 4 . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write literal ?k? to bsr example: movlb 5 before instruction bsr register = 02h after instruction bsr register = 05h
? 2004 microchip technology inc. ds39646b-page 347 pic18f8722 family movlw move literal to w syntax: movlw k operands: 0 k 255 operation: k w status affected: none encoding: 0000 1110 kkkk kkkk description: the eight-bit literal ?k? is loaded into w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: movlw 5ah after instruction w=5ah movwf move w to f syntax: movwf f {,a} operands: 0 f 255 a [0,1] operation: (w) f status affected: none encoding: 0110 111a ffff ffff description: move data from w to register ?f?. location ?f? can be anywhere in the 256-byte bank. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: movwf reg, 0 before instruction w=4fh reg = ffh after instruction w=4fh reg = 4fh
pic18f8722 family ds39646b-page 348 ? 2004 microchip technology inc. mullw multiply literal with w syntax: mullw k operands: 0 k 255 operation: (w) x k prodh:prodl status affected: none encoding: 0000 1101 kkkk kkkk description: an unsigned multiplication is carried out between the contents of w and the 8-bit literal ?k?. the 16-bit result is placed in prodh:prodl register pair. prodh contains the high byte. w is unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this operation. a zero result is possible but not detected. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write registers prodh: prodl example: mullw 0c4h before instruction w=e2h prodh = ? prodl = ? after instruction w=e2h prodh = adh prodl = 08h mulwf multiply w with f syntax: mulwf f {,a} operands: 0 f 255 a [0,1] operation: (w) x (f) prodh:prodl status affected: none encoding: 0000 001a ffff ffff description: an unsigned multiplication is carried out between the contents of w and the register file location ?f?. the 16-bit result is stored in the prodh:prodl register pair. prodh contains the high byte. both w and ?f? are unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this operation. a zero result is possible but not detected. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write registers prodh: prodl example: mulwf reg, 1 before instruction w=c4h reg = b5h prodh = ? prodl = ? after instruction w=c4h reg = b5h prodh = 8ah prodl = 94h
? 2004 microchip technology inc. ds39646b-page 349 pic18f8722 family negf negate f syntax: negf f {,a} operands: 0 f 255 a [0,1] operation: ( f ) + 1 f status affected: n, ov, c, dc, z encoding: 0110 110a ffff ffff description: location ?f? is negated using two?s complement. the result is placed in the data memory location ?f?. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: negf reg, 1 before instruction reg = 0011 1010 [3ah] after instruction reg = 1100 0110 [c6h] nop no operation syntax: nop operands: none operation: no operation status affected: none encoding: 0000 1111 0000 xxxx 0000 xxxx 0000 xxxx description: no operation. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation example: none.
pic18f8722 family ds39646b-page 350 ? 2004 microchip technology inc. pop pop top of return stack syntax: pop operands: none operation: (tos) bit bucket status affected: none encoding: 0000 0000 0000 0110 description: the tos value is pulled off the return stack and is discarded. the tos value then becomes the previous value that was pushed onto the return stack. this instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation pop tos value no operation example: pop goto new before instruction tos = 0031a2h stack (1 level down) = 014332h after instruction tos = 014332h pc = new push push top of return stack syntax: push operands: none operation: (pc + 2) tos status affected: none encoding: 0000 0000 0000 0101 description: the pc + 2 is pushed onto the top of the return stack. the previous tos value is pushed down on the stack. this instruction allows implementing a software stack by modifying tos and then pushing it onto the return stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode push pc + 2 onto return stack no operation no operation example: push before instruction tos = 345ah pc = 0124h after instruction pc = 0126h tos = 0126h stack (1 level down) = 345ah
? 2004 microchip technology inc. ds39646b-page 351 pic18f8722 family rcall relative call syntax: rcall n operands: -1024 n 1023 operation: (pc) + 2 tos, (pc) + 2 + 2n pc status affected: none encoding: 1101 1nnn nnnn nnnn description: subroutine call with a jump up to 1k from the current location. first, return address (pc + 2) is pushed onto the stack. then, add the 2?s complement number ?2n? to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?n? push pc to stack process data write to pc no operation no operation no operation no operation example: here rcall jump before instruction pc = address (here) after instruction pc = address (jump) tos = address (here + 2) reset reset syntax: reset operands: none operation: reset all registers and flags that are affected by a mclr reset. status affected: all encoding: 0000 0000 1111 1111 description: this instruction provides a way to execute a mclr reset in software. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode start reset no operation no operation example: reset after instruction registers = reset value flags* = reset value
pic18f8722 family ds39646b-page 352 ? 2004 microchip technology inc. retfie return from interrupt syntax: retfie {s} operands: s [0,1] operation: (tos) pc, 1 gie/gieh or peie/giel, if s = 1 (ws) w, (statuss) status, (bsrs) bsr, pclatu, pclath are unchanged status affected: gie/gieh, peie/giel. encoding: 0000 0000 0001 000s description: return from interrupt. stack is popped and top-of-stack (tos) is loaded into the pc. interrupts are enabled by setting either the high or low priority global interrupt enable bit. if ?s? = 1 , the contents of the shadow registers ws, statuss and bsrs are loaded into their corresponding registers w, status and bsr. if ?s? = 0 , no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation pop pc from stack set gieh or giel no operation no operation no operation no operation example: retfie 1 after interrupt pc = tos w=ws bsr = bsrs status = statuss gie/gieh, peie/giel = 1 retlw return literal to w syntax: retlw k operands: 0 k 255 operation: k w, (tos) pc, pclatu, pclath are unchanged status affected: none encoding: 0000 1100 kkkk kkkk description: w is loaded with the eight-bit literal ?k?. the program counter is loaded from the top of the stack (the return address). the high address latch (pclath) remains unchanged. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data pop pc from stack, write to w no operation no operation no operation no operation example: call table ; w contains table ; offset value ; w now has ; table value : table addwf pcl ; w = offset retlw k0 ; begin table retlw k1 ; : : retlw kn ; end of table before instruction w = 07h after instruction w = value of kn
? 2004 microchip technology inc. ds39646b-page 353 pic18f8722 family return return from subroutine syntax: return {s} operands: s [0,1] operation: (tos) pc, if s = 1 (ws) w, (statuss) status, (bsrs) bsr, pclatu, pclath are unchanged status affected: none encoding: 0000 0000 0001 001s description: return from subroutine. the stack is popped and the top of the stack (tos) is loaded into the program counter. if ?s?= 1 , the contents of the shadow registers ws, statuss and bsrs are loaded into their corresponding registers w, status and bsr. if ?s? = 0 , no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation process data pop pc from stack no operation no operation no operation no operation example: return after instruction: pc = tos rlcf rotate left f through carry syntax: rlcf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest, (f<7>) c, (c) dest<0> status affected: c, n, z encoding: 0011 01da ffff ffff description: the contents of register ?f? are rotated one bit to the left through the carry flag. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: rlcf reg, 0, 0 before instruction reg = 1110 0110 c=0 after instruction reg = 1110 0110 w= 1100 1100 c=1 c register f
pic18f8722 family ds39646b-page 354 ? 2004 microchip technology inc. rlncf rotate left f (no carry) syntax: rlncf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest, (f<7>) dest<0> status affected: n, z encoding: 0100 01da ffff ffff description: the contents of register ?f? are rotated one bit to the left. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: rlncf reg, 1, 0 before instruction reg = 1010 1011 after instruction reg = 0101 0111 register f rrcf rotate right f through carry syntax: rrcf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest, (f<0>) c, (c) dest<7> status affected: c, n, z encoding: 0011 00da ffff ffff description: the contents of register ?f? are rotated one bit to the right through the carry flag. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: rrcf reg, 0, 0 before instruction reg = 1110 0110 c=0 after instruction reg = 1110 0110 w= 0111 0011 c=0 c register f
? 2004 microchip technology inc. ds39646b-page 355 pic18f8722 family rrncf rotate right f (no carry) syntax: rrncf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest, (f<0>) dest<7> status affected: n, z encoding: 0100 00da ffff ffff description: the contents of register ?f? are rotated one bit to the right. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1: rrncf reg, 1, 0 before instruction reg = 1101 0111 after instruction reg = 1110 1011 example 2: rrncf reg, 0, 0 before instruction w=? reg = 1101 0111 after instruction w= 1110 1011 reg = 1101 0111 register f setf set f syntax: setf f {,a} operands: 0 f 255 a [0,1] operation: ffh f status affected: none encoding: 0110 100a ffff ffff description: the contents of the specified register are set to ffh. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: setf reg,1 before instruction reg = 5ah after instruction reg = ffh
pic18f8722 family ds39646b-page 356 ? 2004 microchip technology inc. sleep enter sleep mode syntax: sleep operands: none operation: 00h wdt, 0 wdt postscaler, 1 to , 0 pd status affected: to , pd encoding: 0000 0000 0000 0011 description: the power-down status bit (pd ) is cleared. the time-out status bit (to ) is set. the watchdog timer and its postscaler are cleared. the processor is put into sleep mode with the oscillator stopped. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data go to sleep example: sleep before instruction to =? pd =? after instruction to =1 ? pd =0 ? if wdt causes wake-up, this bit is cleared. subfwb subtract f from w with borrow syntax: subfwb f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (w) ? (f) ? (c ) dest status affected: n, ov, c, dc, z encoding: 0101 01da ffff ffff description: subtract register ?f? and carry flag (borrow) from w (2?s complement method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1: subfwb reg, 1, 0 before instruction reg = 3 w=2 c=1 after instruction reg = ff w=2 c=0 z=0 n = 1 ; result is negative example 2: subfwb reg, 0, 0 before instruction reg = 2 w=5 c=1 after instruction reg = 2 w=3 c=1 z=0 n = 0 ; result is positive example 3: subfwb reg, 1, 0 before instruction reg = 1 w=2 c=0 after instruction reg = 0 w=2 c=1 z = 1 ; result is zero n=0
? 2004 microchip technology inc. ds39646b-page 357 pic18f8722 family sublw subtract w from literal syntax: sublw k operands: 0 k 255 operation: k ? (w) w status affected: n, ov, c, dc, z encoding: 0000 1000 kkkk kkkk description: w is subtracted from the eight-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example 1: sublw 02h before instruction w = 01h c=? after instruction w = 01h c = 1 ; result is positive z=0 n=0 example 2: sublw 02h before instruction w = 02h c=? after instruction w = 00h c = 1 ; result is zero z=1 n=0 example 3: sublw 02h before instruction w = 03h c=? after instruction w = ffh ; (2?s complement) c = 0 ; result is negative z=0 n=1 subwf subtract w from f syntax: subwf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? (w) dest status affected: n, ov, c, dc, z encoding: 0101 11da ffff ffff description: subtract w from register ?f? (2?s complement method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1: subwf reg, 1, 0 before instruction reg = 3 w=2 c=? after instruction reg = 1 w=2 c = 1 ; result is positive z=0 n=0 example 2: subwf reg, 0, 0 before instruction reg = 2 w=2 c=? after instruction reg = 2 w=0 c = 1 ; result is zero z=1 n=0 example 3: subwf reg, 1, 0 before instruction reg = 1 w=2 c=? after instruction reg = ffh ;(2?s complement) w=2 c = 0 ; result is negative z=0 n=1
pic18f8722 family ds39646b-page 358 ? 2004 microchip technology inc. subwfb subtract w from f with borrow syntax: subwfb f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? (w) ? (c ) dest status affected: n, ov, c, dc, z encoding: 0101 10da ffff ffff description: subtract w and the carry flag (borrow) from register ?f? (2?s complement method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1: subwfb reg, 1, 0 before instruction reg = 19h (0001 1001) w=0dh (0000 1101) c=1 after instruction reg = 0ch (0000 1011) w=0dh (0000 1101) c=1 z=0 n = 0 ; result is positive example 2: subwfb reg, 0, 0 before instruction reg = 1bh (0001 1011) w=1ah (0001 1010) c=0 after instruction reg = 1bh (0001 1011) w = 00h c=1 z = 1 ; result is zero n=0 example 3: subwfb reg, 1, 0 before instruction reg = 03h (0000 0011) w=0eh (0000 1101) c=1 after instruction reg = f5h (1111 0100) ; [2?s comp] w=0eh (0000 1101) c=0 z=0 n = 1 ; result is negative swapf swap f syntax: swapf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> status affected: none encoding: 0011 10da ffff ffff description: the upper and lower nibbles of register ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: swapf reg, 1, 0 before instruction reg = 53h after instruction reg = 35h
? 2004 microchip technology inc. ds39646b-page 359 pic18f8722 family tblrd table read syntax: tblrd ( *; *+; *-; +*) operands: none operation: if tblrd *, (prog mem (tblptr)) tablat; tblptr ? no change if tblrd *+, (prog mem (tblptr)) tablat; (tblptr) + 1 tblptr if tblrd *-, (prog mem (tblptr)) tablat; (tblptr) ? 1 tblptr if tblrd +*, (tblptr) + 1 tblptr; (prog mem (tblptr)) tablat status affected: none encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction is used to read the contents of program memory (p.m.). to address the program memory, a pointer called table pointer (tblptr) is used. the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2-mbyte address range. tblptr[0] = 0 : least significant byte of program memory word tblptr[0] = 1 : most significant byte of program memory word the tblrd instruction can modify the value of tblptr as follows: no change post-increment post-decrement pre-increment words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read program memory) no operation no operation (write tablat) tblrd table read (continued) example 1: tblrd *+ ; before instruction tablat = 55h tblptr = 00a356h memory(00a356h) = 34h after instruction tablat = 34h tblptr = 00a357h example 2: tblrd +* ; before instruction tablat = aah tblptr = 01a357h memory(01a357h) = 12h memory(01a358h) = 34h after instruction tablat = 34h tblptr = 01a358h
pic18f8722 family ds39646b-page 360 ? 2004 microchip technology inc. tblwt table write syntax: tblwt ( *; *+; *-; +*) operands: none operation: if tblwt*, (tablat) holding register; tblptr ? no change if tblwt*+, (tablat) holding register; (tblptr) + 1 tblptr if tblwt*-, (tablat) holding register; (tblptr) ? 1 tblptr if tblwt+*, (tblptr) + 1 tblptr; (tablat) holding register status affected: none encoding: 0000 0000 0000 11nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction uses the 3 lsbs of tblptr to determine which of the 8 holding registers the tablat is written to. the holding registers are used to program the contents of program memory (p.m.). (refer to section 5.0 ?memory organization? for additional details on programming flash memory.) the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2-mbyte address range. the lsb of the tblptr selects which byte of the program memory location to access. tblptr[0] = 0 : least significant byte of program memory word tblptr[0] = 1 : most significant byte of program memory word the tblwt instruction can modify the value of tblptr as follows: no change post-increment post-decrement pre-increment words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read tablat) no operation no operation (write to holding register) tblwt table write (continued) example 1: tblwt *+; before instruction tablat = 55h tblptr = 00a356h holding register (00a356h) = ffh after instructions (table write completion) tablat = 55h tblptr = 00a357h holding register (00a356h) = 55h example 2: tblwt +*; before instruction tablat = 34h tblptr = 01389ah holding register (01389ah) = ffh holding register (01389bh) = ffh after instruction (table write completion) tablat = 34h tblptr = 01389bh holding register (01389ah) = ffh holding register (01389bh) = 34h
? 2004 microchip technology inc. ds39646b-page 361 pic18f8722 family tstfsz test f, skip if 0 syntax: tstfsz f {,a} operands: 0 f 255 a [0,1] operation: skip if f = 0 status affected: none encoding: 0110 011a ffff ffff description: if ?f? = 0 , the next instruction fetched during the current instruction execution is discarded and a nop is executed, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here tstfsz cnt, 1 nzero : zero : before instruction pc = address (here) after instruction if cnt = 00h, pc = address (zero) if cnt 00h, pc = address (nzero) xorlw exclusive or literal with w syntax: xorlw k operands: 0 k 255 operation: (w) .xor. k w status affected: n, z encoding: 0000 1010 kkkk kkkk description: the contents of w are xored with the 8-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: xorlw 0afh before instruction w=b5h after instruction w=1ah
pic18f8722 family ds39646b-page 362 ? 2004 microchip technology inc. xorwf exclusive or w with f syntax: xorwf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (w) .xor. (f) dest status affected: n, z encoding: 0001 10da ffff ffff description: exclusive or the contents of w with register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in the register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 26.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: xorwf reg, 1, 0 before instruction reg = afh w=b5h after instruction reg = 1ah w=b5h
? 2004 microchip technology inc. ds39646b-page 363 pic18f8722 family 26.2 extended instruction set in addition to the standard 75 instructions of the pic18 instruction set, the pic18f8722 family of devices also provide an optional extension to the core cpu function- ality. the added features include eight additional instructions that augment indirect and indexed addressing operations and the implementation of indexed literal offset addressing for many of the standard pic18 instructions. the additional features of the extended instruction set are enabled by default. to enable them, users must set the xinst configuration bit. the instructions in the extended set can all be classified as literal operations, which either manipulate the file select registers, or use them for indexed addressing. two of the instructions, addfsr and subfsr , each have an additional special instantiation for using fsr2. these versions ( addulnk and subulnk ) allow for automatic return after execution. the extended instructions are specifically implemented to optimize re-entrant program code (that is, code that is recursive or that uses a software stack) written in high-level languages, particularly c. among other things, they allow users working in high-level languages to perform certain operations on data structures more efficiently. these include: dynamic allocation and deallocation of software stack space when entering and leaving subroutines function pointer invocation software stack pointer manipulation manipulation of variables located in a software stack a summary of the instructions in the extended instruc- tion set is provided in table 26-3. detailed descriptions are provided in section 26.2.2 ?extended instruction set? . the opcode field descriptions in table 26-1 (page 322) apply to both the standard and extended pic18 instruction sets. 26.2.1 extended instruction syntax most of the extended instructions use indexed argu- ments, using one of the file select registers and some offset to specify a source or destination register. when an argument for an instruction serves as part of indexed addressing, it is enclosed in square brackets (?[ ]?). this is done to indicate that the argument is used as an index or offset. the mpasm? assembler will flag an error if it determines that an index or offset value is not bracketed. when the extended instruction set is enabled, brackets are also used to indicate index arguments in byte-oriented and bit-oriented instructions. this is in addition to other changes in their syntax. for more details, see section 26.2.3.1 ?extended instruction syntax with standard pic18 commands? . table 26-3: extensions to the pic18 instruction set note: the instruction set extension and the indexed literal offset addressing mode were designed for optimizing applications written in c; the user may likely never use these instructions directly in assembler. the syntax for these commands is provided as a reference for users who may be reviewing code that has been generated by a compiler. note: in the past, square brackets have been used to denote optional arguments in the pic18 and earlier instruction sets. in this text and going forward, optional arguments are denoted by braces (?{ }?). mnemonic, operands description cycles 16-bit instruction word status affected msb lsb addfsr addulnk callw movsf movss pushl subfsr subulnk f, k k z s , f d z s , z d k f, k k add literal to fsr add literal to fsr2 and return call subroutine using wreg move z s (source) to 1st word f d (destination) 2nd word move z s (source) to 1st word z d (destination) 2nd word store literal at fsr2, decrement fsr2 subtract literal from fsr subtract literal from fsr2 and return 1 2 2 2 2 1 1 2 1110 1110 0000 1110 1111 1110 1111 1110 1110 1110 1000 1000 0000 1011 ffff 1011 xxxx 1010 1001 1001 ffkk 11kk 0001 0zzz ffff 1zzz xzzz kkkk ffkk 11kk kkkk kkkk 0100 zzzz ffff zzzz zzzz kkkk kkkk kkkk none none none none none none none none
pic18f8722 family ds39646b-page 364 ? 2004 microchip technology inc. 26.2.2 extended instruction set addfsr add literal to fsr syntax: addfsr f, k operands: 0 k 63 f [ 0, 1, 2 ] operation: fsr(f) + k fsr(f) status affected: none encoding: 1110 1000 ffkk kkkk description: the 6-bit literal ?k? is added to the contents of the fsr specified by ?f?. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to fsr example: addfsr 2, 23h before instruction fsr2 = 03ffh after instruction fsr2 = 0422h addulnk add literal to fsr2 and return syntax: addulnk k operands: 0 k 63 operation: fsr2 + k fsr2, (tos) pc status affected: none encoding: 1110 1000 11kk kkkk description: the 6-bit literal ?k? is added to the contents of fsr2. a return is then executed by loading the pc with the tos. the instruction takes two cycles to execute; a nop is performed during the second cycle. this may be thought of as a special case of the addfsr instruction, where f = 3 (binary ? 11 ?); it operates only on fsr2. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to fsr no operation no operation no operation no operation example: addulnk 23h before instruction fsr2 = 03ffh pc = 0100h after instruction fsr2 = 0422h pc = (tos) note: all pic18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. if a label is used, the instruction format then becomes: {label} instruction argument(s).
? 2004 microchip technology inc. ds39646b-page 365 pic18f8722 family callw subroutine call using wreg syntax: callw operands: none operation: (pc + 2) tos, (w) pcl, (pclath) pch, (pclatu) pcu status affected: none encoding: 0000 0000 0001 0100 description first, the return address (pc + 2) is pushed onto the return stack. next, the contents of w are written to pcl; the existing value is discarded. then, the contents of pclath and pclatu are latched into pch and pcu, respectively. the second cycle is executed as a nop instruction while the new next instruction is fetched. unlike call , there is no option to update w, status or bsr. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read wreg push pc to stack no operation no operation no operation no operation no operation example: here callw before instruction pc = address (here) pclath = 10h pclatu = 00h w = 06h after instruction pc = 001006h tos = address (here + 2) pclath = 10h pclatu = 00h w = 06h movsf move indexed to f syntax: movsf [z s ], f d operands: 0 z s 127 0 f d 4095 operation: ((fsr2) + z s ) f d status affected: none encoding: 1st word (source) 2nd word (destin.) 1110 1111 1011 ffff 0zzz ffff zzzz s ffff d description: the contents of the source register are moved to destination register ?f d ?. the actual address of the source register is determined by adding the 7-bit literal offset ?z s ?, in the first word, to the value of fsr2. the address of the destination register is specified by the 12-bit literal ?f d ? in the second word. both addresses can be anywhere in the 4096-byte data space (000h to fffh). the movsf instruction cannot use the pcl, tosu, tosh or tosl as the destination register. if the resultant source address points to an indirect addressing register, the value returned will be 00h. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode determine source addr determine source addr read source reg decode no operation no dummy read no operation write register ?f? (dest) example: movsf [05h], reg2 before instruction fsr2 = 80h contents of 85h = 33h reg2 = 11h after instruction fsr2 = 80h contents of 85h = 33h reg2 = 33h
pic18f8722 family ds39646b-page 366 ? 2004 microchip technology inc. movss move indexed to indexed syntax: movss [z s ], [z d ] operands: 0 z s 127 0 z d 127 operation: ((fsr2) + z s ) ((fsr2) + z d ) status affected: none encoding: 1st word (source) 2nd word (dest.) 1110 1111 1011 xxxx 1zzz xzzz zzzz s zzzz d description the contents of the source register are moved to the destination register. the addresses of the source and destination registers are determined by adding the 7-bit literal offsets ?z s ? or ?z d ?, respectively, to the value of fsr2. both registers can be located anywhere in the 4096-byte data memory space (000h to fffh). the movss instruction cannot use the pcl, tosu, tosh or tosl as the destination register. if the resultant source address points to an indirect addressing register, the value returned will be 00h. if the resultant destination address points to an indirect addressing register, the instruction will execute as a nop . words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode determine source addr determine source addr read source reg decode determine dest addr determine dest addr write to dest reg example: movss [05h], [06h] before instruction fsr2 = 80h contents of 85h = 33h contents of 86h = 11h after instruction fsr2 = 80h contents of 85h = 33h contents of 86h = 33h pushl store literal at fsr2, decrement fsr2 syntax: pushl k operands: 0 k 255 operation: k (fsr2), fsr2 ? 1 fsr2 status affected: none encoding: 1111 1010 kkkk kkkk description: the 8-bit literal ?k? is written to the data memory address specified by fsr2. fsr2 is decremented by 1 after the operation. this instruction allows users to push values onto a software stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read ?k? process data write to destination example: pushl 08h before instruction fsr2h:fsr2l = 01ech memory (01ech) = 00h after instruction fsr2h:fsr2l = 01ebh memory (01ech) = 08h
? 2004 microchip technology inc. ds39646b-page 367 pic18f8722 family subfsr subtract literal from fsr syntax: subfsr f, k operands: 0 k 63 f [ 0, 1, 2 ] operation: fsrf ? k fsrf status affected: none encoding: 1110 1001 ffkk kkkk description: the 6-bit literal ?k? is subtracted from the contents of the fsr specified by ?f?. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: subfsr 2, 23h before instruction fsr2 = 03ffh after instruction fsr2 = 03dch subulnk subtract literal from fsr2 and return syntax: subulnk k operands: 0 k 63 operation: fsr2 ? k fsr2 (tos) pc status affected: none encoding: 1110 1001 11kk kkkk description: the 6-bit literal ?k? is subtracted from the contents of the fsr2. a return is then executed by loading the pc with the tos. the instruction takes two cycles to execute; a nop is performed during the second cycle. this may be thought of as a special case of the subfsr instruction, where f = 3 (binary ? 11 ?); it operates only on fsr2. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination no operation no operation no operation no operation example: subulnk 23h before instruction fsr2 = 03ffh pc = 0100h after instruction fsr2 = 03dch pc = (tos)
pic18f8722 family ds39646b-page 368 ? 2004 microchip technology inc. 26.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode in addition to eight new commands in the extended set, enabling the extended instruction set also enables indexed literal offset addressing ( section 5.5.1 ?indexed addressing with literal offset? ). this has a significant impact on the way that many commands of the standard pic18 instruction set are interpreted. when the extended set is disabled, addresses embed- ded in opcodes are treated as literal memory locations: either as a location in the access bank (a = 0 ) or in a gpr bank designated by the bsr (a = 1 ). when the extended instruction set is enabled and a = 0 , however, a file register argument of 5fh or less is interpreted as an offset from the pointer value in fsr2 and not as a literal address. for practical purposes, this means that all instructions that use the access ram bit as an argument ? that is, all byte-oriented and bit-oriented instructions, or almost half of the core pic18 instruc- tions ? may behave differently when the extended instruction set is enabled. when the content of fsr2 is 00h, the boundaries of the access ram are essentially remapped to their original values. this may be useful in creating backward-compatible code. if this technique is used, it may be necessary to save the value of fsr2 and restore it when moving back and forth between c and assembly routines in order to preserve the stack pointer. users must also keep in mind the syntax requirements of the extended instruction set (see section 26.2.3.1 ?extended instruction syntax with standard pic18 commands? ). although the indexed literal offset addressing mode can be very useful for dynamic stack and pointer manipulation, it can also be very annoying if a simple arithmetic operation is carried out on the wrong register. users who are accustomed to the pic18 pro- gramming must keep in mind that, when the extended instruction set is enabled, register addresses of 5fh or less are used for indexed literal offset addressing. representative examples of typical byte-oriented and bit-oriented instructions in the indexed literal offset addressing mode are provided on the following page to show how execution is affected. the operand condi- tions shown in the examples are applicable to all instructions of these types. 26.2.3.1 extended instruction syntax with standard pic18 commands when the extended instruction set is enabled, the file register argument ?f? in the standard byte-oriented and bit-oriented commands is replaced with the literal offset value ?k?. as already noted, this occurs only when ?f? is less than or equal to 5fh. when an offset value is used, it must be indicated by square brackets (?[ ]?). as with the extended instructions, the use of brackets indicates to the compiler that the value is to be interpreted as an index or an offset. omitting the brackets, or using a value greater than 5fh within the brackets, will generate an error in the mpasm assembler. if the index argument is properly bracketed for indexed literal offset addressing, the access ram argument is never specified; it will automatically be assumed to be ? 0 ?. this is in contrast to standard operation (extended instruction set disabled), when ?a? is set on the basis of the target address. declaring the access ram bit in this mode will also generate an error in the mpasm assembler. the destination argument ?d? functions as before. in the latest versions of the mpasm assembler, language support for the extended instruction set must be explicitly invoked. this is done with either the command line option, /y , or the pe directive in the source listing. 26.2.4 considerations when enabling the extended instruction set it is important to note that the extensions to the instruc- tion set may not be beneficial to all users. in particular, users who are not writing code that uses a software stack may not benefit from using the extensions to the instruction set. additionally, the indexed literal offset addressing mode may create issues with legacy applications written to the pic18 assembler. this is because instructions in the legacy code may attempt to address registers in the access bank below 5fh. since these addresses are interpreted as literal offsets to fsr2 when the instruction set extension is enabled, the application may read or write to the wrong data addresses. when porting an application to the pic18f8722 family, it is very important to consider the type of code. a large, re-entrant application that is written in c and would benefit from efficient compilation will do well when using the instruction set extensions. legacy applica- tions that heavily use the access bank will most likely not benefit from using the extended instruction set. note: enabling the pic18 instruction set exten- sion may cause legacy applications to behave erratically or fail entirely.
? 2004 microchip technology inc. ds39646b-page 369 pic18f8722 family addwf add w to indexed (indexed literal offset mode) syntax: addwf [k] {,d} operands: 0 k 95 d [0,1] operation: (w) + ((fsr2) + k) dest status affected: n, ov, c, dc, z encoding: 0010 01d0 kkkk kkkk description: the contents of w are added to the contents of the register indicated by fsr2, offset by the value ?k?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read ?k? process data write to destination example: addwf [ofst] ,0 before instruction w = 17h ofst = 2ch fsr2 = 0a00h contents of 0a2ch = 20h after instruction w = 37h contents of 0a2ch = 20h bsf bit set indexed (indexed literal offset mode) syntax: bsf [k], b operands: 0 f 95 0 b 7 operation: 1 ((fsr2) + k) status affected: none encoding: 1000 bbb0 kkkk kkkk description: bit ?b? of the register indicated by fsr2, offset by the value ?k?, is set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: bsf [flag_ofst], 7 before instruction flag_ofst = 0ah fsr2 = 0a00h contents of 0a0ah = 55h after instruction contents of 0a0ah = d5h setf set indexed (indexed literal offset mode) syntax: setf [k] operands: 0 k 95 operation: ffh ((fsr2) + k) status affected: none encoding: 0110 1000 kkkk kkkk description: the contents of the register indicated by fsr2, offset by ?k?, are set to ffh. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read ?k? process data write register example: setf [ofst] before instruction ofst = 2ch fsr2 = 0a00h contents of 0a2ch = 00h after instruction contents of 0a2ch = ffh
pic18f8722 family ds39646b-page 370 ? 2004 microchip technology inc. 26.2.5 special considerations with microchip mplab ? ide tools the latest versions of microchip?s software tools have been designed to fully support the extended instruction set for the pic18f8722 family. this includes the mplab c18 c compiler, mpasm assembly language and mplab integrated development environment (ide). when selecting a target device for software development, mplab ide will automatically set default configuration bits for that device. the default setting for the xinst configuration is ? 0 ?, disabling the extended instruction set and indexed literal offset addressing mode. for proper execution of applications developed to take advantage of the extended instruction set, xinst must be set during programming. to develop software for the extended instruction set, the user must enable support for the instructions and the indexed addressing mode in their language tool(s). depending on the environment being used, this may be done in several ways: a menu option or dialog box within the environment that allows the user to configure the language tool and its settings for the project a command line option a directive in the source code these options vary between different compilers, assemblers and development environments. users are encouraged to review the documentation accompany- ing their development systems for the appropriate information.
? 2004 microchip technology inc. preliminary ds39646b-page 371 pic18f8722 family 27.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: integrated development environment - mplab ? ide software assemblers/compilers/linkers - mpasm tm assembler - mplab c17 and mplab c18 c compilers -mplink tm object linker/ mplib tm object librarian - mplab c30 c compiler - mplab asm30 assembler/linker/library simulators - mplab sim software simulator - mplab dspic30 software simulator emulators - mplab ice 2000 in-circuit emulator - mplab ice 4000 in-circuit emulator in-circuit debugger - mplab icd 2 device programmers -pro mate ? ii universal device programmer - picstart ? plus development programmer - mplab pm3 device programmer low-cost demonstration boards - picdem tm 1 demonstration board - picdem.net tm demonstration board - picdem 2 plus demonstration board - picdem 3 demonstration board - picdem 4 demonstration board - picdem 17 demonstration board - picdem 18r demonstration board - picdem lin demonstration board - picdem usb demonstration board evaluation kits -k ee l oq ? evaluation and programming tools - picdem msc -microid ? developer kits -can - powersmart ? developer kits -analog 27.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. the mplab ide is a windows ? based application that contains: an interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) a full-featured editor with color coded context a multiple project manager customizable data windows with direct edit of contents high-level source code debugging mouse over variable inspection extensive on-line help the mplab ide allows you to: edit your source files (either assembly or c) one touch assemble (or compile) and download to picmicro emulator and simulator tools (automatically updates all project information) debug using: - source files (assembly or c) - mixed assembly and c - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increasing flexibility and power. 27.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all picmicro mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol ref- erence, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: integration into mplab ide projects user defined macros to streamline assembly code conditional assembly for multi-purpose source files directives that allow complete control over the assembly process
pic18f8722 family ds39646b-page 372 preliminary ? 2004 microchip technology inc. 27.3 mplab c17 and mplab c18 c compilers the mplab c17 and mplab c18 code development systems are complete ansi c compilers for microchip?s pic17cxxx and pic18cxxx family of microcontrollers. these compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 27.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: efficient linking of single libraries instead of many smaller files enhanced code maintainability by grouping related modules together flexible creation of libraries with easy module listing, replacement, deletion and extraction 27.5 mplab c30 c compiler the mplab c30 c compiler is a full-featured, ansi compliant, optimizing compiler that translates standard ansi c programs into dspic30f assembly language source. the compiler also supports many command line options and language extensions to take full advantage of the dspic30f device hardware capabili- ties and afford fine control of the compiler code generator. mplab c30 is distributed with a complete ansi c standard library. all library functions have been vali- dated and conform to the ansi c library standard. the library includes functions for string manipulation, dynamic memory allocation, data conversion, time- keeping and math functions (trigonometric, exponential and hyperbolic). the compiler provides symbolic information for high-level source debugging with the mplab ide. 27.6 mplab asm30 assembler, linker and librarian mplab asm30 assembler produces relocatable machine code from symbolic assembly language for dspic30f devices. mplab c30 compiler uses the assembler to produce it?s object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: support for the entire dspic30f instruction set support for fixed-point and floating-point data command line interface rich directive set flexible macro language mplab ide compatibility 27.7 mplab sim software simulator the mplab sim software simulator allows code devel- opment in a pc hosted environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any pin. the execu- tion can be performed in single-step, execute until break or trace mode. the mplab sim simulator fully supports symbolic debugging using the mplab c17 and mplab c18 c compilers, as well as the mpasm assembler. the software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool. 27.8 mplab sim30 software simulator the mplab sim30 software simulator allows code development in a pc hosted environment by simulating the dspic30f series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any of the pins. the mplab sim30 simulator fully supports symbolic debugging using the mplab c30 c compiler and mplab asm30 assembler. the simulator runs in either a command line mode for automated tasks, or from mplab ide. this high-speed simulator is designed to debug, analyze and optimize time intensive dsp routines.
? 2004 microchip technology inc. preliminary ds39646b-page 373 pic18f8722 family 27.9 mplab ice 2000 high-performance universal in-circuit emulator the mplab ice 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator sys- tem with enhanced trace, trigger and data monitoring features. interchangeable processor modules allow the system to be easily reconfigured for emulation of differ- ent processors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new picmicro microcontrollers. the mplab ice 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft ? windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 27.10 mplab ice 4000 high-performance universal in-circuit emulator the mplab ice 4000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for high- end picmicro microcontrollers. software control of the mplab ice in-circuit emulator is provided by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab icd 4000 is a premium emulator system, providing the features of mplab ice 2000, but with increased emulation memory and high-speed perfor- mance for dspic30f and pic18xxxx devices. its advanced emulator features include complex triggering and timing, up to 2 mb of emulation memory and the ability to view variables in real-time. the mplab ice 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 27.11 mplab icd 2 in-circuit debugger microchip?s in-circuit debugger, mplab icd 2, is a powerful, low-cost, run-time development tool, connecting to the host pc via an rs-232 or high-speed usb interface. this tool is based on the flash picmicro mcus and can be used to develop for these and other picmicro microcontrollers. the mplab icd 2 utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip?s in-circuit serial programming tm (icsp tm ) protocol, offers cost effective in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by setting breakpoints, single-stepping and watching variables, cpu status and peripheral registers. running at full speed enables testing hardware and applications in real-time. mplab icd 2 also serves as a development programmer for selected picmicro devices. 27.12 pro mate ii universal device programmer the pro mate ii is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features an lcd display for instructions and error messages and a modular detachable socket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify and program picmicro devices without a pc connection. it can also set code protection in this mode. 27.13 mplab pm3 device programmer the mplab pm3 is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modular detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand- alone mode, the mplab pm3 device programmer can read, verify and program picmicro devices without a pc connection. it can also set code protection in this mode. mplab pm3 connects to the host pc via an rs- 232 or usb cable. mplab pm3 has high-speed com- munications and optimized algorithms for quick pro- gramming of large memory devices and incorporates an sd/mmc card for file storage and secure data appli- cations.
pic18f8722 family ds39646b-page 374 preliminary ? 2004 microchip technology inc. 27.14 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low-cost, prototype programmer. it con- nects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer supports most picmicro devices up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 27.15 picdem 1 picmicro demonstration board the picdem 1 demonstration board demonstrates the capabilities of the pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the sample microcontrollers provided with the picdem 1 demonstration board can be programmed with a pro mate ii device program- mer or a picstart plus development programmer. the picdem 1 demonstration board can be connected to the mplab ice in-circuit emulator for testing. a prototype area extends the circuitry for additional appli- cation components. features include an rs-232 interface, a potentiometer for simulated analog input, push button switches and eight leds. 27.16 picdem.net internet/ethernet demonstration board the picdem.net demonstration board is an internet/ ethernet demonstration board using the pic18f452 microcontroller and tcp/ip firmware. the board supports any 40-pin dip device that conforms to the standard pinout used by the pic16f877 or pic18c452. this kit features a user friendly tcp/ip stack, web server with html, a 24l256 serial eeprom for xmodem download to web pages into serial eeprom, icsp/mplab icd 2 interface con- nector, an ethernet interface, rs-232 interface and a 16 x 2 lcd display. also included is the book and cd-rom ?tcp/ip lean, web servers for embedded systems,? by jeremy bentham 27.17 picdem 2 plus demonstration board the picdem 2 plus demonstration board supports many 18, 28 and 40-pin microcontrollers, including pic16f87x and pic18fxx2 devices. all the neces- sary hardware and software is included to run the dem- onstration programs. the sample microcontrollers provided with the picdem 2 demonstration board can be programmed with a pro mate ii device program- mer, picstart plus development programmer, or mplab icd 2 with a universal programmer adapter. the mplab icd 2 and mplab ice in-circuit emulators may also be used with the picdem 2 demonstration board to test firmware. a prototype area extends the circuitry for additional application components. some of the features include an rs-232 interface, a 2 x 16 lcd display, a piezo speaker, an on-board temperature sensor, four leds and sample pic18f452 and pic16f877 flash microcontrollers. 27.18 picdem 3 pic16c92x demonstration board the picdem 3 demonstration board supports the pic16c923 and pic16c924 in the plcc package. all the necessary hardware and software is included to run the demonstration programs. 27.19 picdem 4 8/14/18-pin demonstration board the picdem 4 can be used to demonstrate the capa- bilities of the 8, 14 and 18-pin pic16xxxx and pic18xxxx mcus, including the pic16f818/819, pic16f87/88, pic16f62xa and the pic18f1320 family of microcontrollers. picdem 4 is intended to showcase the many features of these low pin count parts, including lin and motor control using eccp. special provisions are made for low-power operation with the supercapacitor circuit and jumpers allow on- board hardware to be disabled to eliminate current draw in this mode. included on the demo board are pro- visions for crystal, rc or canned oscillator modes, a five volt regulator for use with a nine volt wall adapter or battery, db-9 rs-232 interface, icd connector for programming via icsp and development with mplab icd 2, 2 x 16 liquid crystal display, pcb footprints for h-bridge motor driver, lin transceiver and eeprom. also included are: header for expansion, eight leds, four potentiometers, three push buttons and a proto- typing area. included with the kit is a pic16f627a and a pic18f1320. tutorial firmware is included along with the user?s guide.
? 2004 microchip technology inc. preliminary ds39646b-page 375 pic18f8722 family 27.20 picdem 17 demonstration board the picdem 17 demonstration board is an evaluation board that demonstrates the capabilities of several microchip microcontrollers, including pic17c752, pic17c756a, pic17c762 and pic17c766. a pro- grammed sample is included. the pro mate ii device programmer, or the picstart plus development pro- grammer, can be used to reprogram the device for user tailored application development. the picdem 17 demonstration board supports program download and execution from external on-board flash memory. a generous prototype area is available for user hardware expansion. 27.21 picdem 18r pic18c601/801 demonstration board the picdem 18r demonstration board serves to assist development of the pic18c601/801 family of microchip microcontrollers. it provides hardware implementation of both 8-bit multiplexed/demultiplexed and 16-bit memory modes. the board includes 2 mb external flash memory and 128 kb sram memory, as well as serial eeprom, allowing access to the wide range of memory types supported by the pic18c601/801. 27.22 picdem lin pic16c43x demonstration board the powerful lin hardware and software kit includes a series of boards and three picmicro microcontrollers. the small footprint pic16c432 and pic16c433 are used as slaves in the lin communication and feature on-board lin transceivers. a pic16f874 flash microcontroller serves as the master. all three micro- controllers are programmed with firmware to provide lin bus communication. 27.23 pickit tm 1 flash starter kit a complete ?development system in a box?, the pickit? flash starter kit includes a convenient multi-section board for programming, evaluation and development of 8/14-pin flash pic ? microcontrollers. powered via usb, the board operates under a simple windows gui. the pickit 1 starter kit includes the user?s guide (on cd rom), pickit 1 tutorial software and code for various applications. also included are mplab ? ide (integrated development environment) software, software and hardware ?tips 'n tricks for 8-pin flash pic ? microcontrollers? handbook and a usb interface cable. supports all current 8/14-pin flash pic microcontrollers, as well as many future planned devices. 27.24 picdem usb pic16c7x5 demonstration board the picdem usb demonstration board shows off the capabilities of the pic16c745 and pic16c765 usb microcontrollers. this board provides the basis for future usb products. 27.25 evaluation and programming tools in addition to the picdem series of circuits, microchip has a line of evaluation kits and demonstration software for these products. k ee l oq evaluation and programming tools for microchip?s hcs secure data products can developers kit for automotive network applications analog design boards and filter design software powersmart battery charging evaluation/ calibration kits irda ? development kit microid development and rflab tm development software seeval ? designer kit for memory evaluation and endurance calculations picdem msc demo boards for switching mode power supply, high-power ir driver, delta sigma adc and flow rate sensor check the microchip web page and the latest product selector guide for the complete list of demonstration and evaluation kits.
pic18f8722 family ds39646b-page 376 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39646b-page 377 pic18f8722 family 28.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............-40c to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss (except v dd and mclr ) ................................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +7.5v voltage on mclr with respect to v ss (note 2) ......................................................................................... 0v to +13.25v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) .............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by all ports ...................................................................................................................... .200 ma maximum current sourced by all ports ........................................................................................... .......................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd ? i oh } + {(v dd ? v oh ) x i oh } + (v ol x i ol ) 2: voltage spikes below v ss at the rg5/mclr /v pp pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 ? should be used when applying a ?low? level to the rg5/mclr / v pp pin, rather than pulling this pin directly to v ss . ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic18f8722 family ds39646b-page 378 preliminary ? 2004 microchip technology inc. figure 28-1: pic18f8722 device family voltage-frequency graph (industrial) figure 28-2: pic18f8722 device family voltage-frequency graph (extended) frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v f max 5.0v 3.5v 3.0v 2.5v pic18f6627/6622/6627/6722 4.2v f max = 20 mhz in 8-bit external memory mode. f max = 40 mhz in all other modes. pic18f8527/8622/8627/8722 frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v f max 5.0v 3.5v 3.0v 2.5v 4.2v f max = 20 mhz in 8-bit external memory mode. f max = 25 mhz in all other modes. pic18f6627/6622/6627/6722 pic18f8527/8622/8627/8722
? 2004 microchip technology inc. preliminary ds39646b-page 379 pic18f8722 family figure 28-3: pic18lf8722 device family voltage-frequency graph (industrial) frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v f max 5.0v 3.5v 3.0v 2.5v in 8-bit external memory mode: note: v ddappmin is the minimum voltage of the picmicro ? device in the application. 4 mhz 4.2v f max = (9.55 mhz/v) (v ddappmin ? 2.0v) + 4 mhz, if v ddappmin 4.2v; f max = 25 mhz, if v ddappmin > 4.2v. in all other modes: f max = (16.36 mhz/v) (v ddappmin ? 2.0v) + 4 mhz; f max = 40 mhz, if v ddappmin > 4.2v. pic18lf6627/6622/6627/6722 pic18lf8527/8622/8627/8722
pic18f8722 family ds39646b-page 380 preliminary ? 2004 microchip technology inc. 28.1 dc characteristics: supply voltage pic18f6x27/6x22/8x27/8x22 (industrial, extended) pic18lf6x27/6x22/8x27/8x22 (industrial) pic18lf6x27/6x22/8x27/8x22 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6x27/6x22/8x27/8x22 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ max units conditions d001 v dd supply voltage pic18lf6x27/6x22/8x27/8x22 2.0 ? 5.5 v pic18f6x27/6x22/8x27/8x22 4.2 ? 5.5 v d002 v dr ram data retention voltage (1) 1.5 ? ? v d003 v por v dd start voltage to ensure internal power-on reset signal ??0.7vsee section 4.3 ?power-on reset (por)? for details d004 s vdd v dd rise rate to ensure internal power-on reset signal 0.05 ? ? v/ms see section 4.3 ?power-on reset (por)? for details d005 v bor brown-out reset voltage borv1:borv0 = 11 2.00 2.05 2.16 v pic18lf6627/6722/8627/8722 borv1:borv0 = 11 2.00 2.11 2.22 v pic18lf6527/6622/8527/8622 borv1:borv0 = 10 2.65 2.79 2.93 v pic18lf6x27/6x22/8x27/8x22 borv1:borv0 = 01 4.11 4.33 4.55 v all devices borv1:borv0 = 00 4.36 4.59 4.82 v all devices legend: shading of rows is to assist in readability of the table. note 1: this is the limit to which v dd can be lowered in sleep mode, or duri ng a device reset, without losing ram data.
? 2004 microchip technology inc. preliminary ds39646b-page 381 pic18f8722 family 28.2 dc characteristics: power-down and supply current pic18f6x27/6x22/8x27/8x22 (industrial, extended) pic18lf6x27/6x22/8x27/8x22 (industrial) pic18lf6x27/6x22/8x27/8x22 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6x27/6x22/8x27/8x22 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions power-down current (i pd ) (1) pic18lf6x27/6x22/8x27/8x22 0.12 1.2 a -40c v dd = 2.0v, ( sleep mode) 0.12 1.2 a +25c 0.24 6.0 a +85c pic18lf6x27/6x22/8x27/8x22 0.12 1.7 a -40c v dd = 3.0v, ( sleep mode) 0.12 2.4 a +25c 0.36 9.6 a +85c all devices 0.12 2.4 a -40c v dd = 5.0v, ( sleep mode) 0.12 2.5 a +25c 0.48 18.0 a +85c extended devices only 12 150 a +125c legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd or v ss ; mclr = v dd ; wdt enabled/disabled as specified. 3: low-power timer1 oscillator selected. 4: bor and hlvd enable internal band gap reference. with both modules enabled, current consumption will be less than the sum of both specifications.
pic18f8722 family ds39646b-page 382 preliminary ? 2004 microchip technology inc. supply current (i dd ) (2) pic18lf6x27/6x22/8x27/8x22 18 39 a-40c f osc = 31 khz ( rc_run mode, internal oscillator source) 18 36 a +25c v dd = 2.0v 18 42 a +85c pic18lf6x27/6x22/8x27/8x22 48 75 a-40c 42 72 a +25c v dd = 3.0v 36 69 a +85c all devices 126 202 a-40c v dd = 5.0v 108 192 a +25c 96 182 a +85c extended devices only 96 300 a +125c pic18lf6x27/6x22/8x27/8x22 0.38 1.2 ma -40c f osc = 1 mhz ( rc_run mode, internal oscillator source) 0.38 1.2 ma +25c v dd = 2.0v 0.38 1.2 ma +85c pic18lf6x27/6x22/8x27/8x22 0.72 1.6 ma -40c 0.7 1.5 ma +25c v dd = 3.0v 0.72 1.4 ma +85c all devices 1.3 2.8 ma -40c v dd = 5.0v 1.3 2.8 ma +25c 1.2 2.7 ma +85c extended devices only 1.2 4.0 ma +125c 28.2 dc characteristics: power-down and supply current pic18f6x27/6x22/8x27/8x22 (industrial, extended) pic18lf6x27/6x22/8x27/8x22 (industrial) (continued) pic18lf6x27/6x22/8x27/8x22 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6x27/6x22/8x27/8x22 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd or v ss ; mclr = v dd ; wdt enabled/disabled as specified. 3: low-power timer1 oscillator selected. 4: bor and hlvd enable internal band gap reference. with both modules enabled, current consumption will be less than the sum of both specifications.
? 2004 microchip technology inc. preliminary ds39646b-page 383 pic18f8722 family supply current (i dd ) (2) pic18lf6x27/6x22/8x27/8x22 1.0 2.5 ma -40c f osc = 4 mhz ( rc_run mode, internal oscillator source) 1.0 2.4 ma +25c v dd = 2.0v 1.0 2.3 ma +85c pic18lf6x27/6x22/8x27/8x22 1.6 3.6 ma -40c 1.6 3.6 ma +25c v dd = 3.0v 1.6 3.6 ma +85c all devices 3.0 6.3 ma -40c v dd = 5.0v 3.0 6.0 ma +25c 3.0 5.8 ma +85c extended devices only 3.0 12 ma +125c pic18lf6x27/6x22/8x27/8x22 3.5 9.6 a-40c f osc = 31 khz ( rc_idle mode, internal oscillator source) 3.7 9.6 a +25c v dd = 2.0v 4.3 32 a +85c pic18lf6x27/6x22/8x27/8x22 5.4 13 a-40c 5.7 13 a +25c v dd = 3.0v 7.0 38 a +85c all devices 11 19 a-40c v dd = 5.0v 11.8 19 a +25c 13.5 43 a +85c extended devices only 25 216 a +125c 28.2 dc characteristics: power-down and supply current pic18f6x27/6x22/8x27/8x22 (industrial, extended) pic18lf6x27/6x22/8x27/8x22 (industrial) (continued) pic18lf6x27/6x22/8x27/8x22 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6x27/6x22/8x27/8x22 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd or v ss ; mclr = v dd ; wdt enabled/disabled as specified. 3: low-power timer1 oscillator selected. 4: bor and hlvd enable internal band gap reference. with both modules enabled, current consumption will be less than the sum of both specifications.
pic18f8722 family ds39646b-page 384 preliminary ? 2004 microchip technology inc. supply current (i dd ) (2) pic18lf6x27/6x22/8x27/8x22 200 420 a-40c f osc = 1 mhz ( rc_idle mode, internal oscillator source) 210 420 a +25c v dd = 2.0v 228 420 a +85c pic18lf6x27/6x22/8x27/8x22 300 600 a-40c 324 600 a +25c v dd = 3.0v 350 600 a +85c all devices 0.6 1.2 ma -40c v dd = 5.0v 0.62 1.2 ma +25c 0.67 1.2 ma +85c extended devices only 0.72 3.5 ma +125c pic18lf6x27/6x22/8x27/8x22 410 600 a-40c f osc = 4 mhz ( rc_idle mode, internal oscillator source) 420 600 a +25c v dd = 2.0v 430 600 a +85c pic18lf6x27/6x22/8x27/8x22 0.63 1.1 ma -40c 0.65 1.1 ma +25c v dd = 3.0v 0.69 1.1 ma +85c all devices 1.2 1.9 ma -40c v dd = 5.0v 1.3 1.8 ma +25c 1.2 1.7 ma +85c extended devices only 1.2 6.0 ma +125c 28.2 dc characteristics: power-down and supply current pic18f6x27/6x22/8x27/8x22 (industrial, extended) pic18lf6x27/6x22/8x27/8x22 (industrial) (continued) pic18lf6x27/6x22/8x27/8x22 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6x27/6x22/8x27/8x22 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd or v ss ; mclr = v dd ; wdt enabled/disabled as specified. 3: low-power timer1 oscillator selected. 4: bor and hlvd enable internal band gap reference. with both modules enabled, current consumption will be less than the sum of both specifications.
? 2004 microchip technology inc. preliminary ds39646b-page 385 pic18f8722 family supply current (i dd ) (2) pic18lf6x27/6x22/8x27/8x22 300 600 a-40c f osc = 1 mh z ( pri_run mode, ec oscillator) 310 600 a +25c v dd = 2.0v 300 600 a +85c pic18lf6x27/6x22/8x27/8x22 660 855 a-40c 580 780 a +25c v dd = 3.0v 550 780 a +85c all devices 1.5 1.9 ma -40c v dd = 5.0v 1.4 1.8 ma +25c 1.3 1.7 ma +85c extended devices only 1.3 4.2 ma +125c pic18lf6x27/6x22/8x27/8x22 0.86 2.4 ma -40c f osc = 4 mhz ( pri_run mode, ec oscillator) 0.88 2.4 ma +25c v dd = 2.0v 0.88 2.4 ma +85c pic18lf6x27/6x22/8x27/8x22 1.6 3.6 ma -40c 1.6 3.6 ma +25c v dd = 3.0v 1.6 3.6 ma +85c all devices 3.2 7.2 ma -40c v dd = 5.0v 3.1 7.2 ma +25c 3.0 7.2 ma +85c extended devices only 3.1 8.4 ma +125c 28.2 dc characteristics: power-down and supply current pic18f6x27/6x22/8x27/8x22 (industrial, extended) pic18lf6x27/6x22/8x27/8x22 (industrial) (continued) pic18lf6x27/6x22/8x27/8x22 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6x27/6x22/8x27/8x22 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd or v ss ; mclr = v dd ; wdt enabled/disabled as specified. 3: low-power timer1 oscillator selected. 4: bor and hlvd enable internal band gap reference. with both modules enabled, current consumption will be less than the sum of both specifications.
pic18f8722 family ds39646b-page 386 preliminary ? 2004 microchip technology inc. supply current (i dd ) (2) extended devices only 10 25 ma +125c v dd = 4.2v f osc = 25 mhz ( pri_run mode, ec oscillator) 13 33 ma +125c v dd = 5.0v all devices 18 42 ma -40c f osc = 40 mh z ( pri_run mode, ec oscillator) 19 42 ma +25c v dd = 4.2v 19 42 ma +85c all devices 25 48 ma -40c 25 48 ma +25c v dd = 5.0v 25 48 ma +85c 28.2 dc characteristics: power-down and supply current pic18f6x27/6x22/8x27/8x22 (industrial, extended) pic18lf6x27/6x22/8x27/8x22 (industrial) (continued) pic18lf6x27/6x22/8x27/8x22 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6x27/6x22/8x27/8x22 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd or v ss ; mclr = v dd ; wdt enabled/disabled as specified. 3: low-power timer1 oscillator selected. 4: bor and hlvd enable internal band gap reference. with both modules enabled, current consumption will be less than the sum of both specifications.
? 2004 microchip technology inc. preliminary ds39646b-page 387 pic18f8722 family supply current (i dd ) (2) all devices 9.0 19 ma -40c v dd = 4.2v f osc = 4 mh z . 16 mhz internal ( pri_run hs+pll ) 9.0 18 ma +25c 9.0 17 ma +85c extended devices only 9.6 30 ma +125c all devices 12 25 ma -40c v dd = 5.0v f osc = 4 mh z , 16 mhz internal ( pri_run hs+pll ) 12 24 ma +25c 12 23 ma +85c extended devices only 12 42 ma +125c all devices 20 42 ma -40c v dd = 4.2v f osc = 10 mh z , 40 mhz internal ( pri_run hs+pll ) 20 42 ma +25c 20 42 ma +85c all devices 28 48 ma -40c v dd = 5.0v f osc = 10 mh z , 40 mhz internal ( pri_run hs+pll ) 28 48 ma +25c 28 48 ma +85c 28.2 dc characteristics: power-down and supply current pic18f6x27/6x22/8x27/8x22 (industrial, extended) pic18lf6x27/6x22/8x27/8x22 (industrial) (continued) pic18lf6x27/6x22/8x27/8x22 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6x27/6x22/8x27/8x22 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd or v ss ; mclr = v dd ; wdt enabled/disabled as specified. 3: low-power timer1 oscillator selected. 4: bor and hlvd enable internal band gap reference. with both modules enabled, current consumption will be less than the sum of both specifications.
pic18f8722 family ds39646b-page 388 preliminary ? 2004 microchip technology inc. supply current (i dd ) (2) pic18lf6x27/6x22/8x27/8x22 78 215 a-40c f osc = 1 mhz ( pri_idle mode, ec oscillator) 78 210 a +25c v dd = 2.0v 84 205 a +85c pic18lf6x27/6x22/8x27/8x22 144 325 a-40c 144 300 a +25c v dd = 3.0v 144 288 a +85c all devices 360 575 a-40c v dd = 5.0v 290 540 a +25c 360 515 a +85c extended devices only 0.38 1.1 ma +125c pic18lf6x27/6x22/8x27/8x22 312 570 a-40c f osc = 4 mhz ( pri_idle mode, ec oscillator) 305 540 a +25c v dd = 2.0v 324 515 a +85c pic18lf6x27/6x22/8x27/8x22 0.5 1.1 ma -40c 0.6 1.0 ma +25c v dd = 3.0v 0.6 0.9 ma +85c all devices 1.1 1.8 ma -40c v dd = 5.0v 1.1 1.7 ma +25c 1.1 1.6 ma +85c extended devices only 1.2 3.1 ma +125c 28.2 dc characteristics: power-down and supply current pic18f6x27/6x22/8x27/8x22 (industrial, extended) pic18lf6x27/6x22/8x27/8x22 (industrial) (continued) pic18lf6x27/6x22/8x27/8x22 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6x27/6x22/8x27/8x22 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd or v ss ; mclr = v dd ; wdt enabled/disabled as specified. 3: low-power timer1 oscillator selected. 4: bor and hlvd enable internal band gap reference. with both modules enabled, current consumption will be less than the sum of both specifications.
? 2004 microchip technology inc. preliminary ds39646b-page 389 pic18f8722 family supply current (i dd ) (2) extended devices only 3.4 8.4 ma +125c v dd = 4.2v f osc = 25 mhz ( pri_idle mode, ec oscillator) 5.2 13 ma +125c v dd = 5.0v all devices 7.2 19 ma -40c f osc = 40 mhz ( pri_idle mode, ec oscillator) 7.4 19 ma +25c v dd = 4.2 v 7.8 19 ma +85c all devices 9.7 21 ma -40c 11 21 ma +25c v dd = 5.0v 10 21 ma +85c 28.2 dc characteristics: power-down and supply current pic18f6x27/6x22/8x27/8x22 (industrial, extended) pic18lf6x27/6x22/8x27/8x22 (industrial) (continued) pic18lf6x27/6x22/8x27/8x22 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6x27/6x22/8x27/8x22 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd or v ss ; mclr = v dd ; wdt enabled/disabled as specified. 3: low-power timer1 oscillator selected. 4: bor and hlvd enable internal band gap reference. with both modules enabled, current consumption will be less than the sum of both specifications.
pic18f8722 family ds39646b-page 390 preliminary ? 2004 microchip technology inc. supply current (i dd ) (2) pic18lf6x27/6x22/8x27/8x22 17 48 a-40c f osc = 32 khz (3) ( sec_run mode, timer1 as clock) 18 48 a +25c v dd = 2.0v 19 48 a +70c pic18lf6x27/6x22/8x27/8x22 48 89 a-40c 42 84 a +25c v dd = 3.0v 37 80 a +70c all devices 120 180 a-40c 97 180 a +25c v dd = 5.0v 90 180 a +70c pic18lf6x27/6x22/8x27/8x22 3.0 14 a-40c f osc = 32 khz (3) ( sec_idle mode, timer1 as clock) 4.4 14 a +25c v dd = 2.0v 5.4 14 a +70c pic18lf6x27/6x22/8x27/8x22 6.0 18 a-40c 6.5 18 a +25c v dd = 3.0v 7.6 18 a +70c all devices 10.0 30 a-40c 10.5 30 a +25c v dd = 5.0v 11.0 43 a +70c 28.2 dc characteristics: power-down and supply current pic18f6x27/6x22/8x27/8x22 (industrial, extended) pic18lf6x27/6x22/8x27/8x22 (industrial) (continued) pic18lf6x27/6x22/8x27/8x22 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6x27/6x22/8x27/8x22 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd or v ss ; mclr = v dd ; wdt enabled/disabled as specified. 3: low-power timer1 oscillator selected. 4: bor and hlvd enable internal band gap reference. with both modules enabled, current consumption will be less than the sum of both specifications.
? 2004 microchip technology inc. preliminary ds39646b-page 391 pic18f8722 family module differential currents ( ? i wdt , ? i bor , ? i lvd , ? i oscb , ? i ad ) d022 ( ? i wdt ) watchdog timer 1.5 5.7 a-40c v dd = 2.0v 1.6 6.3 a +25c 2.4 6.3 a +85c 2.3 6.6 a-40c v dd = 3.0v 2.4 7.2 a +25c 3.4 7.2 a +85c 4.8 12 a-40c v dd = 5.0v 6.0 12 a +25c 6.1 12 a +85c 10 16 a +125c d022a ( ? i bor ) brown-out reset (4) 4.2 48 a -40c to +85c v dd = 3.0v 48 54 a -40c to +85c v dd = 5.0v 66 54 a -40c to +125c 02.4 a -40c to +85c sleep mode, boren1:boren0 = 10 06.0 a -40c to +125c d022b ( ? i lvd ) high/low-voltage detect (4) 2.7 47 a -40c to +85c v dd = 2.0v 30 48 a -40c to +85c v dd = 3.0v 35 54 a -40c to +85c v dd = 5.0v 36 54 a -40c to +125c d025 ( ? i oscb ) timer1 oscillator 2.5 8.1 a-40c v dd = 2.0v 32 khz on timer1 (3) 2.2 8.7 a +25c 2.5 8.7 a +85c 2.6 9.1 a-40c v dd = 3.0v 32 khz on timer1 (3) 3.1 9.7 a +25c 3.5 9.7 a +85c 3.6 9.6 a-40c v dd = 5.0v 32 khz on timer1 (3) 3.8 9.6 a +25c 4.0 9.6 a +85c 28.2 dc characteristics: power-down and supply current pic18f6x27/6x22/8x27/8x22 (industrial, extended) pic18lf6x27/6x22/8x27/8x22 (industrial) (continued) pic18lf6x27/6x22/8x27/8x22 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6x27/6x22/8x27/8x22 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd or v ss ; mclr = v dd ; wdt enabled/disabled as specified. 3: low-power timer1 oscillator selected. 4: bor and hlvd enable internal band gap reference. with both modules enabled, current consumption will be less than the sum of both specifications.
pic18f8722 family ds39646b-page 392 preliminary ? 2004 microchip technology inc. d026 ( ? i ad ) a/d converter 1.2 2.4 a -40c to +85c v dd = 2.0v a/d on, not converting, sleep mode 1.2 2.4 a -40c to +85c v dd = 3.0v 1.2 2.4 a -40c to +85c v dd = 5.0v 2.4 9.6 a -40c to +125c 28.2 dc characteristics: power-down and supply current pic18f6x27/6x22/8x27/8x22 (industrial, extended) pic18lf6x27/6x22/8x27/8x22 (industrial) (continued) pic18lf6x27/6x22/8x27/8x22 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6x27/6x22/8x27/8x22 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd or v ss ; mclr = v dd ; wdt enabled/disabled as specified. 3: low-power timer1 oscillator selected. 4: bor and hlvd enable internal band gap reference. with both modules enabled, current consumption will be less than the sum of both specifications.
? 2004 microchip technology inc. preliminary ds39646b-page 393 pic18f8722 family 28.3 dc characteristics: pic18f8722 (industrial, extended) pic18lf6x27/6x22/8x27/8x22 (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. symbol characteristic min max units conditions v il input low voltage i/o ports: d030 with ttl buffer v ss 0.15 v dd vv dd < 4.5v d030a ? 0.8 v 4.5v v dd 5.5v d031 with schmitt trigger buffer v ss 0.2 v dd v d032 mclr v ss 0.2 v dd v d033 osc1 v ss 0.3 v dd v hs, hspll modes d033a d033b d034 osc1 osc1 t13cki v ss v ss v ss 0.2 v dd 0.3 0.3 v v v rc, ec modes (1) xt, lp modes v ih input high voltage i/o ports: d040 with ttl buffer 0.25 v dd + 0.8v v dd vv dd < 4.5v d040a 2.0 v dd v4.5v v dd 5.5v d041 with schmitt trigger buffer 0.8 v dd v dd v d042 mclr 0.8 v dd v dd v d043 osc1 0.7 v dd v dd v hs, hspll modes d043a d043b d043c d044 osc1 osc1 osc1 t13cki 0.8 v dd 0.9 v dd 1.6 1.6 v dd v dd v dd v dd v v v v ec mode rc mode (1) xt, lp modes i il input leakage current (2,3) d060 i/o ports ? 1 av ss v pin v dd , pin at high-impedance d061 mclr ? 5 avss v pin v dd d063 osc1 ? 5 avss v pin v dd i pu weak pull-up current d070 i purb portb weak pull-up current 50 400 av dd = 5v, v pin = v ss note 1: in rc oscillator configuration, the osc1/clki pin is a schmitt trigger input. it is not recommended that the picmicro ? device be driven with an external clock while in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
pic18f8722 family ds39646b-page 394 preliminary ? 2004 microchip technology inc. v ol output low voltage d080 i/o ports ? 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d083 osc2/clko (rc, rcio, ec, ecio modes) ?0.6vi ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c v oh output high voltage (3) d090 i/o ports v dd ? 0.7 ? v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d092 osc2/clko (rc, rcio, ec, ecio modes) v dd ? 0.7 ? v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c capacitive loading specs on output pins d100 cosc2 osc2 pin ? 15 pf in xt, hs and lp modes when external clock is used to drive osc1 d101 c io all i/o pins and osc2 (in rc mode) ? 50 pf to meet the ac timing specifications d102 c b sclx, sdax ? 400 pf i 2 c? specification 28.3 dc characteristics: pic18f8722 (industrial, extended) pic18lf6x27/6x22/8x27/8x22 (industrial) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. symbol characteristic min max units conditions note 1: in rc oscillator configuration, the osc1/clki pin is a schmitt trigger input. it is not recommended that the picmicro ? device be driven with an external clock while in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
? 2004 microchip technology inc. preliminary ds39646b-page 395 pic18f8722 family table 28-1: memory programming requirements dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. sym characteristic min typ? max units conditions data eeprom memory d120 e d byte endurance 100k 1m ? e/w -40 c to +85 c d121 v drw v dd for read/write v min ? 5.5 v using eecon to read/write v min = minimum operating voltage d122 t dew erase/write cycle time ? 4 ? ms d123 t retd characteristic retention 40 ? ? year provided no other specifications are violated d124 t ref number of total erase/write cycles before refresh (1) 1m 10m ? e/w -40c to +85c d125 i ddp supply current during programming ?10?ma program flash memory d130 e p cell endurance 10k 100k ? e/w -40 c to +85 c d131 v pr v dd for read v min ?5.5vv min = minimum operating voltage d132b v pew v dd for self-timed write and row erase v min ?5.5vv min = minimum operating voltage d133a t iw self-timed write cycle time ? 2 ? ms d134 t retd characteristic retention 40 100 ? year provided no other specifications are violated d135 i ddp supply current during programming ?10?ma ? data in ?typ? column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: refer to section 8.8 ?using the data eeprom? for a more detailed discussion on data eeprom endurance.
pic18f8722 family ds39646b-page 396 preliminary ? 2004 microchip technology inc. table 28-2: comparator specifications table 28-3: comparator voltage reference specifications operating conditions: 3.0v < v dd < 5.5v, -40c < t a < +85c (unless otherwise stated) param no. sym characteristics min typ max units comments d300 v ioff input offset voltage ? 5.0 10 mv d301 v icm input common mode voltage 0 ? v dd ? 1.5 v d302 cmrr common mode rejection ratio 55 ? ? db 300 t resp response time (1) ? 150 400 ns pic18 f xxxx 300a ? 150 600 ns pic18 lf xxxx, v dd = 2.0v 301 t mc 2 ov comparator mode change to output valid ?? 10 s note 1: response time measured with one comparator input at (v dd ? 1.5)/2, while the other input transitions from v ss to v dd . operating conditions: 3.0v < v dd < 5.5v, -40c < t a < +85c (unless otherwise stated) param no. sym characteristics min typ max units comments d310 v res resolution v dd /24 ? v dd /32 lsb d311 vr aa absolute accuracy ? ? 1/2 lsb d312 vr ur unit resistor value (r) ? 2k ? ? 310 t set settling time (1) ? ? 10 s note 1: settling time measured while cvrr = 1 and cvr3:cvr0 transitions from ? 0000 ? to ? 1111 ?.
? 2004 microchip technology inc. preliminary ds39646b-page 397 pic18f8722 family figure 28-4: high/low-voltage detect characteristics table 28-4: high/low-voltage detect characteristics v hlvd hlvdif v dd (hlvdif set by hardware) (hlvdif can be cleared in software) v hlvd for vdirmag = 1 : for vdirmag = 0 : v dd standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. symbol characteristic min typ max units conditions d420 hlvd voltage on v dd transition high-to-low hlvdl = 0000 2.06 2.17 2.28 v hlvdl = 0001 2.12 2.23 2.34 v hlvdl = 0010 2.24 2.36 2.48 v hlvdl = 0011 2.32 2.44 2.56 v hlvdl = 0100 2.47 2.60 2.73 v hlvdl = 0101 2.65 2.79 2.93 v hlvdl = 0110 2.74 2.89 3.04 v hlvdl = 0111 2.96 3.12 3.28 v hlvdl = 1000 3.22 3.39 3.56 v hlvdl = 1001 3.37 3.55 3.73 v hlvdl = 1010 3.52 3.71 3.90 v hlvdl = 1011 3.70 3.90 4.10 v hlvdl = 1100 3.90 4.11 4.32 v hlvdl = 1101 4.11 4.33 4.55 v hlvdl = 1110 4.36 4.59 4.82 v
pic18f8722 family ds39646b-page 398 preliminary ? 2004 microchip technology inc. 28.4 ac (timing) characteristics 28.4.1 timing parameter symbology the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 3. t cc : st (i 2 c? specifications only) 2. tpps 4. ts (i 2 c specifications only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clko rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t13cki mc mclr wr wr uppercase letters and their meanings: s f fall p period hhigh rrise i invalid (high-impedance) v valid l low z high-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition
? 2004 microchip technology inc. preliminary ds39646b-page 399 pic18f8722 family 28.4.2 timing conditions the temperature and voltages specified in table 28-5 apply to all timing specifications unless otherwise noted. figure 28-5 specifies the load conditions for the timing specifications. table 28-5: temperature and voltage specifications ? ac figure 28-5: load conditions for devi ce timing specifications note: because of space limitations, the generic terms ?pic18fxxxx? and ?pic18lfxxxx? are used throughout this section to refer to the pic18f6x27/6x22/8x27/8x22 and pic18lf6x27/6x22/8x27/ 8x22 families of devices specifically and only those devices. ac characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in the dc specifications in section 28.1 and section 28.3 . lf parts operate for industrial temperatures only. v dd /2 c l r l pin pin v ss v ss c l r l =464 ? c l = 50 pf for all pins except osc2/clko and including d and e outputs as ports load condition 1 load condition 2
pic18f8722 family ds39646b-page 400 preliminary ? 2004 microchip technology inc. 28.4.3 timing diagrams and specifications figure 28-6: external clock timing (all modes except pll) table 28-6: external clock timing requirements osc1 clko q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 param. no. symbol characteristic min max units conditions 1a f osc external clki frequency (1) dc 1 mhz xt, rc oscillator mode dc 25 mhz hs oscillator mode dc 31.25 khz lp oscillator mode dc 40 mhz ec oscillator mode oscillator frequency (1) dc 4 mhz rc oscillator mode 0.1 4 mhz xt oscillator mode 4 25 mhz hs oscillator mode 4 10 mhz hs + pll oscillator mode 5 200 khz lp oscillator mode 1t osc external clki period (1) 1000 ? ns xt, rc oscillator mode 40 ? ns hs oscillator mode 32 ? s lp oscillator mode 25 ? ns ec oscillator mode oscillator period (1) 250 ? ns rc oscillator mode 250 1 s xt oscillator mode 40 250 ns hs oscillator mode 100 250 ns hs + pll oscillator mode 5? s lp oscillator mode 2t cy instruction cycle time (1) 100 ? ns t cy = 4/f osc , industrial 160 ? ns t cy = 4/f osc , extended 3t os l, t os h external clock in (osc1) high or low time 30 ? ns xt oscillator mode 2.5 ? s lp oscillator mode 10 ? ns hs oscillator mode 4t os r, t os f external clock in (osc1) rise or fall time ? 20 ns xt oscillator mode ? 50 ns lp oscillator mode ? 7.5 ns hs oscillator mode note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period for all configurations except pll. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osc1/clki pin. when an external clock input is used, the ?max.? cycle time limit is ?dc? (no clock) for all devices.
? 2004 microchip technology inc. preliminary ds39646b-page 401 pic18f8722 family table 28-7: pll clock timing specifications (v dd = 4.2v to 5.5v) table 28-8: ac characteristics:internal rc accuracy pic18f6x27/6x22/8x27/8x22 (industrial, extended) pic18lf6x27/6x22/8x27/8x22 (industrial) param no. sym characteristic min typ? max units conditions f10 f osc oscillator frequency range 4 ? 10 mhz hs mode only f11 f sys on-chip vco system frequency 16 ? 40 mhz hs mode only f12 t rc pll start-up time (lock time) ? ? 2 ms f13 ? clk clko stability (jitter) -2 ? +2 % ? data in ?typ? column is at 5v, 25 c, unless otherwise stated. these parameters are for design guidance only and are not tested. pic18lf6x27/6x22/8x27/8x22 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6x27/6x22/8x27/8x22 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device min typ max units conditions intosc accuracy @ freq = 8 mhz, 4 mhz, 2 mhz, 1 mhz, 500 khz, 250 khz, 125 khz (1) pic18lf6x27/6x22/8x27/8x22 -2 +/-1 2 % +25c v dd = 2.7-3.3v -5 ? 5 % -10c to +85c v dd = 2.7-3.3v -10 +/-1 10 % -40c to +85c v dd = 2.7-3.3v pic18f6x27/6x22/8x27/8x22 -2 +/-1 2 % +25c v dd = 4.5-5.5v -5 ? 5 % -10c to +85c v dd = 4.5-5.5v -10 +/-1 10 % -40c to +85c v dd = 4.5-5.5v intrc accuracy @ freq = 31 khz (2) pic18lf6x27/6x22/8x27/8x22 -15 ? 15 % -40c to +85c v dd = 2.7-3.3v pic18f6x27/6x22/8x27/8x22 -15 +/-8 15 % -40c to +85c v dd = 4.5-5.5v legend: shading of rows is to assist in readability of the table. note 1: frequency calibrated at 25c. osctune register can be used to compensate for temperature drift. 2: intrc frequency after calibration.
pic18f8722 family ds39646b-page 402 preliminary ? 2004 microchip technology inc. figure 28-7: clko and i/o timing table 28-9: clko and i/o timing requirements note: refer to figure 28-5 for load conditions. osc1 clko i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value param no. symbol characteristic min typ max units conditions 10 t os h2 ck losc1 to clko ? 75 200 ns (note 1) 11 t os h2 ck hosc1 to clko ? 75 200 ns (note 1) 12 t ck r clko rise time ? 35 100 ns (note 1) 13 t ck f clko fall time ? 35 100 ns (note 1) 14 t ck l2 io vclko to port out valid ? ? 0.5 t cy + 20 ns (note 1) 15 t io v2 ck h port in valid before clko 0.25 t cy + 25 ? ? ns (note 1) 16 t ck h2 io i port in hold after clko 0??ns (note 1) 17 t os h2 io vosc1 (q1 cycle) to port out valid ? 50 150 ns 18 t os h2 io iosc1 (q2 cycle) to port input invalid (i/o in hold time) pic18 f xxxx 100 ? ? ns 18a pic18 lf xxxx 200 ? ? ns v dd = 2.0v 19 t io v2 os h port input valid to osc1 (i/o in setup time) 0??ns 20 t io r port output rise time pic18 f xxxx ? 10 25 ns 20a pic18 lf xxxx ? ? 60 ns v dd = 2.0v 21 t io f port output fall time pic18 f xxxx ? 10 25 ns 21a pic18 lf xxxx ? ? 60 ns v dd = 2.0v 22? t inp int pin high or low time t cy ??ns 23? t rbp rb7:rb4 change int high or low time t cy ??ns ? these parameters are asynchronous events not related to any internal clock edges. note 1: measurements are taken in rc mode, where clko output is 4 x t osc .
? 2004 microchip technology inc. preliminary ds39646b-page 403 pic18f8722 family figure 28-8: program memo ry read timing diagram table 28-10: clko and i/o timing requirements param. no symbol characteristics min typ max units 150 tadv2all address out valid to ale (address setup time) 0.25 t cy ? 10 ? ? ns 151 tall2adl ale to address out invalid (address hold time) 5??ns 155 tall2oel ale to oe 10 0.125 t cy ?ns 160 tadz2oel ad high-z to oe (bus release to oe )0??ns 161 toeh2add oe to ad driven 0.125 t cy ? 5 ? ? ns 162 tadv2oeh ls data valid before oe (data setup time) 20 ? ? ns 163 toeh2adl oe to data in invalid (data hold time) 0 ? ? ns 164 talh2all ale pulse width ? t cy ?ns 165 toel2oeh oe pulse width 0.5 t cy ? 5 0.5 t cy ?ns 166 talh2alh ale to ale (cycle time) ? 0.25 t cy ?ns 167 tacc address valid to data valid 0.75 t cy ? 25 ? ? ns 168 toe oe to data valid ? 0.5 t cy ? 25 ns 169 tall2oeh ale to oe 0.625 t cy ? 10 ? 0.625 t cy + 10 ns 171 talh2csl chip enable active to ale 0.25 t cy ? 20 ? ? ns 171a tubl2oeh ad valid to chip enable active ? ? 10 ns q1 q2 q3 q4 q1 q2 osc1 ale oe address data from external 164 166 160 165 161 151 162 163 ad<15:0> 167 168 155 address address 150 a<19:16> address 169 ba0 ce 171 171a operating conditions: 2.0v < v cc < 5.5v, -40c < t a < +125c unless otherwise stated.
pic18f8722 family ds39646b-page 404 preliminary ? 2004 microchip technology inc. figure 28-9: program memory write timing diagram table 28-11: program memory write timing requirements param. no symbol characteristics min typ max units 150 tadv2all address out valid to ale (address setup time) 0.25 t cy ? 10 ? ? ns 151 tall2adl ale to address out invalid (address hold time) 5 ? ? ns 153 twrh2adl wrn to data out invalid (data hold time) 5 ? ? ns 154 twrl wrn pulse width 0.5 t cy ? 5 0.5 t cy ?ns 156 tadv2wrh data valid before wrn (data setup time) 0.5 t cy ? 10 ? ? ns 157 tbsv2wrl byte select valid before wrn (byte select setup time) 0.25 t cy ??ns 157a twrh2bsi wrn to byte select invalid (byte select hold time) 0.125 t cy ? 5 ? ? ns 166 talh2alh ale to ale (cycle time) ? 0.25 t cy ?ns 171 talh2csl chip enable active to ale 0.25 t cy ? 20 ? ? ns 171a tubl2oeh ad valid to chip enable active ? ? 10 ns q1 q2 q3 q4 q1 q2 osc1 ale address data 156 150 151 153 ad<15:0> address wrh or wrl ub or lb 157 154 157a address a<19:16> address ba0 166 ce 171 171a operating conditions: 2.0v < v cc < 5.5v, -40c < t a < +125c unless otherwise stated.
? 2004 microchip technology inc. preliminary ds39646b-page 405 pic18f8722 family figure 28-10: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 28-11: brown-out reset timing table 28-12: reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements param. no. symbol characteristic min typ max units conditions 30 tmcl mclr pulse width (low) 2 ? ? s 31 t wdt watchdog timer time-out period (no postscaler) 3.4 4.0 4.6 ms 32 t ost oscillation start-up timer period 1024 t osc ? 1024 t osc ?t osc = osc1 period 33 t pwrt power-up timer period 55.6 64 75 ms 34 t ioz i/o high-impedance from mclr low or watchdog timer reset ?2? s 35 t bor brown-out reset pulse width 200 ? ? sv dd b vdd (see d005) 36 t irvst time for internal reference voltage to become stable ?2050 s 37 t lvd high/low-voltage detect pulse width 200 ? ? sv dd v hlvd 38 t csd cpu start-up time ? 10 ? s 39 t iobst time for intosc to stabilize ? 1 ? s v dd mclr internal por pwrt time-out oscillator time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 28-5 for load conditions. v dd bv dd 35 v bgap = 1.2v v irvst enable internal internal reference 36 reference voltage voltage stable
pic18f8722 family ds39646b-page 406 preliminary ? 2004 microchip technology inc. figure 28-12: timer0 and timer1 external clock timings table 28-13: timer0 and timer1 external clock requirements note: refer to figure 28-5 for load conditions. 46 47 45 48 41 42 40 t0cki t1oso/t13cki tmr0 or tmr1 param no. symbol characteristic min max units conditions 40 t t 0h t0cki high pulse width no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns 41 t t 0l t0cki low pulse width no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns 42 t t 0p t0cki period no prescaler t cy + 10 ? ns with prescaler greater of: 20 ns or (t cy + 40)/n ?nsn = prescale value (1, 2, 4,..., 256) 45 t t 1h t13cki high time synchronous, no prescaler 0.5 t cy + 20 ? ns synchronous, with prescaler pic18 f xxxx 10 ? ns pic18 lf xxxx 25 ? ns v dd = 2.0v asynchronous pic18 f xxxx 30 ? ns pic18 lf xxxx 50 ? ns v dd = 2.0v 46 t t 1l t13cki low time synchronous, no prescaler 0.5 t cy + 5 ? ns synchronous, with prescaler pic18 f xxxx 10 ? ns pic18 lf xxxx 25 ? ns v dd = 2.0v asynchronous pic18 f xxxx 30 ? ns pic18 lf xxxx 50 ? ns v dd = 2.0v 47 t t 1p t13cki input period synchronous greater of: 20 ns or (t cy + 40)/n ?nsn = prescale value (1, 2, 4, 8) asynchronous 60 ? ns f t 1 t13cki oscillator input frequency range dc 50 khz 48 t cke 2 tmr i delay from external t13cki clock edge to timer increment 2 t osc 7 t osc ?
? 2004 microchip technology inc. preliminary ds39646b-page 407 pic18f8722 family figure 28-13: capture/compare/pwm timings (all eccp/ccp modules) table 28-14: capture/compare/pwm requirements (all eccp/ccp modules) note: refer to figure 28-5 for load conditions. ccpx (capture mode) 50 51 52 ccpx 53 54 (compare or pwm mode) param no. symbol characteristic min max units conditions 50 t cc l ccpx input low time no prescaler 0.5 t cy + 20 ? ns with prescaler pic18 f xxxx 10 ? ns pic18 lf xxxx 20 ? ns v dd = 2.0v 51 t cc h ccpx input high time no prescaler 0.5 t cy + 20 ? ns with prescaler pic18 f xxxx 10 ? ns pic18 lf xxxx 20 ? ns v dd = 2.0v 52 t cc p ccpx input period 3 t cy + 40 n ? ns n = prescale value (1, 4 or 16) 53 t cc r ccpx output fall time pic18 f xxxx ? 25 ns pic18 lf xxxx ? 45 ns v dd = 2.0v 54 t cc f ccpx output fall time pic18 f xxxx ? 25 ns pic18 lf xxxx ? 45 ns v dd = 2.0v
pic18f8722 family ds39646b-page 408 preliminary ? 2004 microchip technology inc. figure 28-14: parallel slave port timing (pic18f8527/8622/8627/8722) table 28-15: parallel slave port requirements (pic18f8527/8622/8627/8722) note: refer to figure 28-5 for load conditions. re2/cs re0/rd re1/wr rd7:rd0 62 63 64 65 param. no. symbol characteristic min max units conditions 62 tdtv2wrh data in valid before wr or cs (setup time) 20 ? ns 63 twrh2dti wr or cs to data?in invalid (hold time) pic18 f xxxx 20 ? ns pic18 lf xxxx 35 ? ns v dd = 2.0v 64 trdl2dtv rd and cs to data?out valid ? 80 ns 65 trdh2dti rd or cs to data?out invalid 10 30 ns 66 tibfinh inhibit of the ibf flag bit being cleared from wr or cs ?3 t cy
? 2004 microchip technology inc. preliminary ds39646b-page 409 pic18f8722 family figure 28-15: example spi? master mode timing (cke = 0 ) table 28-16: example spi? mode requirements (master mode, cke = 0 ) ss x sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit 6 - - - - - - 1 msb in lsb in bit 6 - - - - 1 note: refer to figure 28-5 for load conditions. param no. symbol characteristic min max units conditions 70 t ss l2 sc h, t ss l2 sc l ssx to sckx or sckx input t cy ?ns 71 t sc h sckx input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 t sc l sckx input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 100 ? ns 73a t b 2 b last clock edge of byte 1 to the 1st clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 100 ? ns 75 t do r sdox data output rise time pic18 f xxxx ? 25 ns pic18 lf xxxx ? 45 ns v dd = 2.0v 76 t do f sdox data output fall time ? 25 ns 78 t sc r sckx output rise time (master mode) pic18 f xxxx ? 25 ns pic18 lf xxxx ? 45 ns v dd = 2.0v 79 t sc f sckx output fall time (master mode) ? 25 ns 80 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge pic18 f xxxx ? 50 ns pic18 lf xxxx ? 100 ns v dd = 2.0v note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used.
pic18f8722 family ds39646b-page 410 preliminary ? 2004 microchip technology inc. figure 28-16: example spi? master mode timing (cke = 1 ) table 28-17: example spi? mode requirements (master mode, cke = 1 ) ss x sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit 6 - - - - - - 1 lsb in bit 6 - - - - 1 lsb note: refer to figure 28-5 for load conditions. param. no. symbol characteristic min max units conditions 71 t sc h sckx input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 t sc l sckx input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 100 ? ns 73a t b 2 b last clock edge of byte 1 to the 1st clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 100 ? ns 75 t do r sdox data output rise time pic18 f xxxx ? 25 ns pic18 lf xxxx ? 45 ns v dd = 2.0v 76 t do f sdox data output fall time ? 25 ns 78 t sc r sckx output rise time (master mode) pic18 f xxxx ? 25 ns pic18 lf xxxx ? 45 ns v dd = 2.0v 79 t sc f sckx output fall time (master mode) ? 25 ns 80 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge pic18 f xxxx ? 50 ns pic18 lf xxxx ? 100 ns v dd = 2.0v 81 t do v2 sc h, t do v2 sc l sdox data output setup to sckx edge t cy ?ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used.
? 2004 microchip technology inc. preliminary ds39646b-page 411 pic18f8722 family figure 28-17: example spi? slave mode timing (cke = 0 ) table 28-18: example spi? mode requirements (slave mode timing, cke = 0 ) param no. symbol characteristic min max units conditions 70 t ss l2 sc h, t ss l2 sc l ssx to sckx or sckx input t cy ?ns 71 t sc h sckx input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 t sc l sckx input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 100 ? ns 73a t b 2 b last clock edge of byte 1 to the first clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 100 ? ns 75 t do r sdox data output rise time pic18 f xxxx ? 25 ns pic18 lf xxxx ? 45 ns v dd = 2.0v 76 t do f sdox data output fall time ? 25 ns 77 t ss h2 do z ssx to sdox output high-impedance 10 50 ns 78 t sc r sckx output rise time (master mode) pic18 f xxxx ? 25 ns pic18 lf xxxx ? 45 ns v dd = 2.0v 79 t sc f sckx output fall time (master mode) ? 25 ns 80 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge pic18 f xxxx ? 50 ns pic18 lf xxxx ? 100 ns v dd = 2.0v 83 t sc h2 ss h, t sc l2 ss h ssx after sckx edge 1.5 t cy + 40 ? ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used. ss x sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 sdix msb lsb bit 6 - - - - - - 1 msb in bit 6 - - - - 1 lsb in 83 note: refer to figure 28-5 for load conditions.
pic18f8722 family ds39646b-page 412 preliminary ? 2004 microchip technology inc. figure 28-18: example spi? slave mode timing (cke = 1 ) table 28-19: example spi? slave mode requirements (cke = 1 ) param no. symbol characteristic min max units conditions 70 t ss l2 sc h, t ss l2 sc l ssx to sckx or sckx input t cy ?ns 71 t sc h sckx input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 t sc l sckx input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73a t b 2 b last clock edge of byte 1 to the first clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 100 ? ns 75 t do r sdox data output rise time pic18 f xxxx ? 25 ns pic18 lf xxxx ? 45 ns v dd = 2.0v 76 t do f sdox data output fall time ? 25 ns 77 t ss h2 do z ssx to sdox output high-impedance 10 50 ns 78 t sc r sckx output rise time (master mode) pic18 f xxxx ? 25 ns pic18 lf xxxx ? 45 ns v dd = 2.0v 79 t sc f sckx output fall time (master mode) ? 25 ns 80 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge pic18 f xxxx ? 50 ns pic18 lf xxxx ? 100 ns v dd = 2.0v 82 t ss l2 do v sdox data output valid after ssx edge pic18 f xxxx ? 50 ns pic18 lf xxxx ? 100 ns v dd = 2.0v 83 t sc h2 ss h, t sc l2 ss h ssx after sckx edge 1.5 t cy + 40 ? ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used. ss x sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdi 70 71 72 82 sdix 74 75, 76 msb bit 6 - - - - - - 1 lsb 77 msb in bit 6 - - - - 1 lsb in 80 83 note: refer to figure 28-5 for load conditions.
? 2004 microchip technology inc. preliminary ds39646b-page 413 pic18f8722 family figure 28-19: i 2 c? bus start/stop bits timing table 28-20: i 2 c? bus start/stop bits requirements (slave mode) figure 28-20: i 2 c? bus data timing note: refer to figure 28-5 for load conditions. 91 92 93 sclx sdax start condition stop condition 90 param. no. symbol characteristic min max units conditions 90 t su : sta start condition 100 khz mode 4700 ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? 91 t hd : sta start condition 100 khz mode 4000 ? ns after this period, the first clock pulse is generated hold time 400 khz mode 600 ? 92 t su : sto stop condition 100 khz mode 4700 ? ns setup time 400 khz mode 600 ? 93 t hd : sto stop condition 100 khz mode 4000 ? ns hold time 400 khz mode 600 ? note: refer to figure 28-5 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 sclx sdax in sdax out
pic18f8722 family ds39646b-page 414 preliminary ? 2004 microchip technology inc. table 28-21: i 2 c? bus data requirements (slave mode) param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 ? s pic18fxxxx must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? s pic18fxxxx must operate at a minimum of 10 mhz ssp module 1.5 t cy ? 101 t low clock low time 100 khz mode 4.7 ? s pic18fxxxx must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? s pic18fxxxx must operate at a minimum of 10 mhz ssp module 1.5 t cy ? 102 t r sdax and sclx rise time 100 khz mode ? 1000 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 to 400 pf 103 t f sdax and sclx fall time 100 khz mode ? 300 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 to 400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition 400 khz mode 0.6 ? s 91 t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period, the first clock pulse is generated 400 khz mode 0.6 ? s 106 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 s 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 92 t su : sto stop condition setup time 100 khz mode 4.7 ? s 400 khz mode 0.6 ? s 109 t aa output valid from clock 100 khz mode ? 3500 ns (note 1) 400 khz mode ? ? ns 110 t buf bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s d102 c b bus capacitive loading ? 400 pf note 1: as a transmitter, the device must provi de this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of sclx to avoid unint ended generation of start or stop conditions. 2: a fast mode i 2 c? bus device can be us ed in a standard mode i 2 c bus system, but the requirement, t su : dat 250 ns, must then be met. this will automatically be the case if the device does not stretch the low period of the sclx signal. if such a device does stretch the low period of the sclx si gnal, it must output the next data bit to the sdax line, t r max. + t su : dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification), before the sclx line is released.
? 2004 microchip technology inc. preliminary ds39646b-page 415 pic18f8722 family figure 28-21: master ssp i 2 c? bus start/stop bits timing waveforms table 28-22: master ssp i 2 c? bus start/stop bits requirements figure 28-22: master ssp i 2 c? bus data timing note: refer to figure 28-5 for load conditions. 91 93 sclx sdax start condition stop condition 90 92 param. no. symbol characteristic min max units conditions 90 t su : sta start condition 100 khz mode 2(t osc )(brg + 1) ? ns only relevant for repeated start condition setup time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 91 t hd : sta start condition 100 khz mode 2(t osc )(brg + 1) ? ns after this period, the first clock pulse is generated hold time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 92 t su : sto stop condition 100 khz mode 2(t osc )(brg + 1) ? ns setup time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 93 t hd : sto stop condition 100 khz mode 2(t osc )(brg + 1) ? ns hold time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? note 1: maximum pin capacitance = 10 pf for all i 2 c? pins. note: refer to figure 28-5 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 sclx sdax in sdax out
pic18f8722 family ds39646b-page 416 preliminary ? 2004 microchip technology inc. table 28-23: master ssp i 2 c? bus data requirements param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 101 t low clock low time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 102 t r sdax and sclx rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ? 300 ns 103 t f sdax and sclx fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ? 100 ns 90 t su : sta start condition setup time 100 khz mode 2(t osc )(brg + 1) ? ms only relevant for repeated start condition 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 91 t hd : sta start condition hold time 100 khz mode 2(t osc )(brg + 1) ? ms after this period, the first clock pulse is generated 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 106 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 ms 1 mhz mode (1) tbd ? ns 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 1 mhz mode (1) tbd ? ns 92 t su : sto stop condition setup time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 109 t aa output valid from clock 100 khz mode ? 3500 ns 400 khz mode ? 1000 ns 1 mhz mode (1) ??ns 110 t buf bus free time 100 khz mode 4.7 ? ms time the bus must be free before a new transmission can start 400 khz mode 1.3 ? ms 1 mhz mode (1) tbd ? ms d102 c b bus capacitive loading ? 400 pf legend: tbd = to be determined note 1: maximum pin capacitance = 10 pf for all i 2 c? pins. 2: a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system, but parameter #107 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the sclx signal. if such a device does stretch the low period of the sclx signal, it must output the next data bit to the sdax line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 khz mode,) before the sclx line is released.
? 2004 microchip technology inc. preliminary ds39646b-page 417 pic18f8722 family figure 28-23: eusart synchronous transmissi on (master/slave) timing table 28-24: eusart synchronous transmission requirements figure 28-24: eusart synchronous receive (master/slave) timing table 28-25: eusart synchronous receive requirements 121 121 120 122 ckx/txx dtx/rxx pin pin note: refer to figure 28-5 for load conditions. param no. symbol characteristic min max units conditions 120 t ck h2 dt v sync xmit (master and slave) clock high to data out valid pic18 f xxxx ? 40 ns pic18 lf xxxx ? 100 ns v dd = 2.0v 121 t ckrf clock out rise time and fall time (master mode) pic18 f xxxx ? 20 ns pic18 lf xxxx ? 50 ns v dd = 2.0v 122 t dtrf data out rise time and fall time pic18 f xxxx ? 20 ns pic18 lf xxxx ? 50 ns v dd = 2.0v 125 126 ckx/txx dtx/rxx pin pin note: refer to figure 28-5 for load conditions. param. no. symbol characteristic min max units conditions 125 t dt v2 ckl sync rcv (master and slave) data hold before ckx (dtx hold time) 10 ? ns 126 t ck l2 dtl data hold after ckx (dtx hold time) 15 ? ns
pic18f8722 family ds39646b-page 418 preliminary ? 2004 microchip technology inc. table 28-26: a/d converter characteristics: pic18f6x27/6x22/8x27/8x22 (industrial) pic18lf6x27/6x22/8x27/8x22 (industrial) figure 28-25: a/d conversion timing param no. symbol characteristic min typ max units conditions a01 n r resolution ? ? 10 bit ? v ref 3.0v a03 e il integral linearity error ? ? <1 lsb ? v ref 3.0v a04 e dl differential linearity error ? ? <1 lsb ? v ref 3.0v a06 e off offset error ? ? <1.5 lsb ? v ref 3.0v a07 e gn gain error ? ? <1 lsb ? v ref 3.0v a10 ? monotonicity guaranteed (1) ?v ss v ain v ref a20 ? v ref reference voltage range (v refh ? v refl ) 1.8 3 ? ? ? ? v v v dd < 3.0v v dd 3.0v a21 v refh reference voltage high v ss ?v refh v a22 v refl reference voltage low v ss ? 0.3v ? v dd ? 3.0v v a25 v ain analog input voltage v refl ?v refh v a30 z ain recommended impedance of analog voltage source ??2.5k ? a40 i ad a/d current from v dd pic18 f xxxx ? 180 ? a average current during conversion pic18 lf xxxx ? 90 ? a a50 i ref v ref input current (2) ? ? ? ? 5 150 a a during v ain acquisition. during a/d conversion cycle. note 1: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes. 2: v refh current is from ra3/an3/v ref + pin or v dd , whichever is selected as the v refh source. v refl current is from ra2/an2/v ref - pin or v ss , whichever is selected as the v refl source. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (note 1, 2) 987 21 0 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 2: this is a minimal rc delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. . . . . . . t cy
? 2004 microchip technology inc. preliminary ds39646b-page 419 pic18f8722 family table 28-27: a/d conversion requirements param no. symbol characteristic min max units conditions 130 t ad a/d clock period pic18 f xxxx 0.7 25.0 (1) st osc based, v ref 3.0v pic18 lf xxxx 1.4 25.0 (1) sv dd = 2.0v; t osc based, v ref full range pic18 f xxxx tbd 1 s a/d rc mode pic18 lf xxxx tbd 3 sv dd = 2.0v; a/d rc mode 131 t cnv conversion time (not including acquisition time) (note 2) 11 12 t ad 132 t acq acquisition time (note 3) 1.4 tbd ? ? s s -40 c to +85 c 0 c to +85 c 135 t swc switching time from convert sample ? (note 4) 137 t dis discharge time 0.2 ? s legend: tbd = to be determined note 1: the time of the a/d clock period is dependent on the device frequency and the t ad clock divider. 2: adres register may be read on the following t cy cycle. 3: the time for the holding capacitor to acquire the ?new? input voltage when the voltage changes full scale after the conversion (v dd to v ss or v ss to v dd ). the source impedance ( r s ) on the input channels is 50 ? . 4: on the following cycle of the device clock.
pic18f8722 family ds39646b-page 420 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39646b-page 421 pic18f8722 family 29.0 dc and ac characteristics graphs and tables graphs and tables are not available at this time.
pic18f8722 family ds39646b-page 422 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39646b-page 423 pic18f8722 family 30.0 packaging information 30.1 package marking information 64-lead tqfp xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example pic18f6722 -i/pt 0410017 80-lead tqfp xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example pic18f8722-e /pt 0410017 legend: xx...x customer specific information* y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard picmicro device marking consists of microchip part number, year code, week code, and traceability code. for picmicro device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price.
pic18f8722 family ds39646b-page 424 preliminary ? 2004 microchip technology inc. 30.2 package details the following sections give the technical details of the packages. 64-lead plastic thin quad flatpack (pt) 10x10x1 mm body, 1.0/0.10 mm lead form (tqfp) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 0.27 0.22 0.17 .011 .009 .007 b lead width 0.23 0.18 0.13 .009 .007 .005 c lead thickness 16 16 n1 pins per side 10.10 10.00 9.90 .398 .394 .390 d1 molded package length 10.10 10.00 9.90 .398 .394 .390 e1 molded package width 12.25 12.00 11.75 .482 .472 .463 d overall length 12.25 12.00 11.75 .482 .472 .463 e overall width 7 3.5 0 7 3.5 0 foot angle 0.75 0.60 0.45 .030 .024 .018 l foot length 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.05 1.00 0.95 .041 .039 .037 a2 molded package thickness 1.20 1.10 1.00 .047 .043 .039 a overall height 0.50 .020 p pitch 64 64 n number of pins max nom min max nom min dimension limits millimeters* inches units c 2 1 n d d1 b p #leads=n1 e1 e a2 a1 a l ch x 45 (f) footprint (reference) (f) .039 1.00 pin 1 corner chamfer ch .025 .035 .045 0.64 0.89 1.14 shall not exceed .010" (0.254mm) per side. dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions notes: jedec equivalent: ms-026 drawing no. c04-085 *controlling parameter
? 2004 microchip technology inc. preliminary ds39646b-page 425 pic18f8722 family 80-lead plastic thin quad flatpack (pt) 12x12x1 mm body, 1.0/0.10 mm lead form (tqfp) 1.10 1.00 .043 .039 1.14 0.89 0.64 .045 .035 .025 ch pin 1 corner chamfer 1.00 .039 (f) footprint (reference) (f) e e1 #leads=n1 p b d1 d n 1 2 c l a a1 a2 units inches millimeters* dimension limits min nom max min nom max number of pins n 80 80 pitch p .020 0.50 overall height a .047 1.20 molded package thickness a2 .037 .039 .041 0.95 1.00 1.05 standoff a1 .002 .004 .006 0.05 0.10 0.15 foot length l .018 .024 .030 0.45 0.60 0.75 foot angle 03.5 7 03.5 7 overall width e .541 .551 .561 13.75 14.00 14.25 overall length d .541 .551 .561 13.75 14.00 14.25 molded package width e1 .463 .472 .482 11.75 12.00 12.25 molded package length d1 .463 .472 .482 11.75 12.00 12.25 pins per side n1 20 20 lead thickness c .004 .006 .008 0.09 0.15 0.20 lead width b .007 .009 .011 0.17 0.22 0.27 mold draft angle top 5 10 15 5 10 15 mold draft angle bottom 5 10 15 5 10 15 ch x 45 shall not exceed .010" (0.254mm) per side. dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions notes: jedec equivalent: ms-026 drawing no. c04-092 *controlling parameter
pic18f8722 family ds39646b-page 426 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39646b-page 427 pic18f8722 family appendix a: revision history revision a (september 2004) original data sheet for the pic18f8722 family of devices. revision b (december 2004) this revision includes updates to the electrical specifica- tions in section 28.0 ?electrical characteristics? , minor corrections to the data sheet text and information to support the following devices has been added: appendix b: device differences the differences between the devices listed in this data sheet are shown in table b-1. table b-1: device differences (pic18f6527/6622/6627/6722) table b-2: device differences (pic18f8527/8622/8627/8722) pic18f6527 pic18lf6527 pic18f6622 pic18lf6622 pic18f8527 pic18lf8527 pic18f8622 pic18lf8622 features pic18f6527 pic18f6622 pic18f6627 pic18f6722 program memory (bytes) 48k 64k 96k 128k program memory (instructions) 24576 32768 49152 65536 interrupt sources 28 28 28 28 i/o ports ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g capture/compare/pwm modules2222 enhanced capture/compare/pwm modules 3333 parallel communications (psp) yes yes yes yes external memory bus no no no no 10-bit analog-to-digital module 12 input channels 12 input channels 12 input channels 12 input channels packages 64-pin tqfp 64-pin tqfp 64-pin tqfp 64-pin tqfp features pic18f8527 pic18f8622 pic18f8627 pic18f8722 program memory (bytes) 48k 64k 96k 128k program memory (instructions) 24576 32768 49152 65536 interrupt sources 29292929 i/o ports ports a, b, c, d, e, f, g, h , j ports a, b, c, d, e, f, g, h , j ports a, b, c, d, e, f, g, h , j ports a, b, c, d, e, f, g, h , j capture/compare/pwm modules 2 2 2 2 enhanced capture/compare/pwm modules 3333 parallel communications (psp) yes yes yes yes external memory bus yes yes yes yes 10-bit analog-to-digital module 16 input channels 16 input channels 16 input channels 16 input channels packages 80-pin tqfp 80-pin tqfp 80-pin tqfp 80-pin tqfp
pic18f8722 family ds39646b-page 428 preliminary ? 2004 microchip technology inc. appendix c: conversion considerations this appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. typically, these changes are due to the differences in the process technology used. an example of this type of conversion is from a pic16c74a to a pic16c74b. not applicable appendix d: migration from baseline to enhanced devices this section discusses how to migrate from a baseline device (i.e., pic16c5x) to an enhanced mcu device (i.e., pic18fxxx). the following are the list of modifications over the pic16c5x microcontroller family: not currently available
? 2004 microchip technology inc. preliminary ds39646b-page 429 pic18f8722 family appendix e: migration from mid-range to enhanced devices a detailed discussion of the differences between the mid-range mcu devices (i.e., pic16cxxx) and the enhanced devices (i.e., pic18fxxx) is provided in an716, ?migrating designs from pic16c74a/74b to pic18c442 ?. the changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations. this application note is available on our web site, www.microchip.com, as literature number ds00716. appendix f: migration from high-end to enhanced devices a detailed discussion of the migration pathway and differences between the high-end mcu devices (i.e., pic17cxxx) and the enhanced devices (i.e., pic18fxxx) is provided in an726, ?pic17cxxx to pic18cxxx migration ?. this application note is available on our web site, www.microchip.com, as literature number ds00726.
pic18f8722 family ds39646b-page 430 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39646b-page 431 pic18f8722 family index a a/d ................................................................................... 271 a/d converter interrupt, configuring ....................... 275 acquisition requirements ........................................ 276 adcon0 register .................................................... 271 adcon1 register .................................................... 271 adcon2 register .................................................... 271 adresh register ............................................ 271, 274 adresl register .................................................... 271 analog port pins ...................................................... 158 analog port pins, configuring .................................. 278 associated registers ............................................... 280 configuring the module ............................................ 275 conversion clock (t ad ) ........................................... 277 conversion status (go/done bit) .......................... 274 conversions ............................................................. 279 converter characteristics ........................................ 418 discharge ................................................................. 279 operation in power-managed modes ...................... 278 selecting and configuring acquisition time .............................................. 277 special event trigger (eccp) ................................. 192 special event trigger (eccp2) ............................... 280 use of the eccp2 trigger ....................................... 280 absolute maximum ratings ............................................. 377 ac (timing) characteristics ............................................. 398 load conditions for device timing specifications ....................................... 399 parameter symbology ............................................. 398 temperature and voltage specific ations ................. 399 timing conditions .................................................... 399 access bank mapping in indexed literal offset mode .................... 85 ackstat ........................................................................ 236 ackstat status flag ..................................................... 236 adcon0 register ............................................................ 271 go/done bit ........................................................... 274 adcon1 register ............................................................ 271 adcon2 register ............................................................ 271 addfsr .......................................................................... 364 addlw ............................................................................ 327 addulnk ........................................................................ 364 addwf ............................................................................ 327 addwfc ......................................................................... 328 adresh register ............................................................ 271 adresl register .................................................... 271, 274 analog-to-digital converter. see a/d. andlw ............................................................................ 328 andwf ............................................................................ 329 assembler mpasm assembler .................................................. 371 auto-wake-up on sync break character ......................... 262 b bank select register (bsr) ............................................... 72 baud rate generator ....................................................... 232 bc .................................................................................... 329 bcf .................................................................................. 330 bf .................................................................................... 236 bf status flag ................................................................. 236 block diagrams 16-bit byte select mode .......................................... 103 16-bit byte write mode ............................................ 101 16-bit word write mode .......................................... 102 a/d ........................................................................... 274 analog input model .................................................. 275 baud rate generator .............................................. 232 capture mode operation ......................................... 181 comparator analog input model .............................. 285 comparator i/o operating modes ........................... 282 comparator output .................................................. 284 comparator voltage reference ............................... 288 comparator voltage reference output buffer example .................................... 289 compare mode operation ....................................... 182 device clock .............................................................. 37 enhanced pwm ....................................................... 193 eusart receive .................................................... 260 eusart transmit ................................................... 258 external power-on reset circuit (slow v dd power-up) ........................................ 51 fail-safe clock monitor (fscm) .............................. 315 generic i/o port operation ...................................... 135 high/low-voltage detect with external input .................................................. 292 hspll ....................................................................... 33 interrupt logic .......................................................... 120 intosc and pll ....................................................... 34 mssp (i 2 c master mode) ........................................ 230 mssp (i 2 c mode) .................................................... 215 mssp (spi mode) ................................................... 205 on-chip reset circuit ................................................ 49 pic18f6527/6622/6627/6722 ................................... 11 pic18f8527/8622/8627/8722 ................................... 12 portd and porte (parallel slave port) ............... 158 pwm operation (simplified) .................................... 184 reads from flash program memory ......................... 91 single comparator ................................................... 283 table read operation ............................................... 87 table write operation ............................................... 88 table writes to flash program memory .................... 93 timer0 in 16-bit mode ............................................. 162 timer0 in 8-bit mode ............................................... 162 timer1 ..................................................................... 166 timer1 (16-bit read/write mode) ............................ 166 timer2 ..................................................................... 172 timer3 ..................................................................... 174 timer3 (16-bit read/write mode) ............................ 174 timer4 ..................................................................... 178 watchdog timer ...................................................... 312 bn .................................................................................... 330 bnc ................................................................................. 331 bnn ................................................................................. 331 bnov .............................................................................. 332 bnz ................................................................................. 332 bor. see brown-out reset. bov ................................................................................. 335 bra ................................................................................. 333 break character (12-bit) transmit and receive .............. 263 brg. see baud rate generator.
pic18f8722 family ds39646b-page 432 preliminary ? 2004 microchip technology inc. brown-out reset (bor) ..................................................... 52 detecting .................................................................... 52 disabling in sleep mode ............................................ 52 software enabled ....................................................... 52 bsf .................................................................................. 333 btfsc ............................................................................. 334 btfss .............................................................................. 334 btg .................................................................................. 335 bz ..................................................................................... 336 c c compilers mplab c17 ............................................................. 372 mplab c18 ............................................................. 372 mplab c30 ............................................................. 372 call ................................................................................ 336 callw ............................................................................. 365 capture (ccp module) ..................................................... 181 associated registers ............................................... 183 ccprxh:ccprxl registers ................................... 181 ccpx pin configuration ........................................... 181 prescaler .................................................................. 181 software interrupt .................................................... 181 timer1/timer3 mode selection ................................ 181 capture (eccp module) .................................................. 192 capture/compare/pwm (ccp) ........................................ 179 capture mode. see capture. ccp mode and timer resources ............................ 180 ccprxh register .................................................... 180 ccprxl register ..................................................... 180 compare mode. see compare. interconnect configurations ..................................... 180 module configuration ............................................... 180 clock sources .................................................................... 37 selecting the 31 khz source ...................................... 38 selection using osccon register ........................... 38 clrf ................................................................................ 337 clrwdt .......................................................................... 337 code examples 16 x 16 signed multiply routine .............................. 118 16 x 16 unsigned multiply routine .......................... 118 8 x 8 signed multiply routine .................................. 117 8 x 8 unsigned multiply routine .............................. 117 changing between capture prescalers ................... 181 computed goto using an offset value ................... 68 data eeprom read ............................................... 113 data eeprom refresh routine .............................. 114 data eeprom write ............................................... 113 erasing a flash program memory row ..................... 92 fast register stack .................................................... 68 how to clear ram (bank 1) using indirect addressing .................................. 81 implementing a real-time clock using a timer1 interrupt service ..................... 169 initializing porta .................................................... 135 initializing portb .................................................... 137 initializing portc .................................................... 140 initializing portd .................................................... 143 initializing porte .................................................... 146 initializing portf .................................................... 149 initializing portg ................................................... 151 initializing porth .................................................... 154 initializing portj .................................................... 156 loading the ssp1buf (ssp1sr) register .......................................... 208 reading a flash program memory word .................. 91 saving status, wreg and bsr registers in ram .................................... 134 writing to flash program memory ....................... 94?95 code protection ............................................................... 297 comf .............................................................................. 338 comparator ...................................................................... 281 analog input connection considerations ................ 285 associated registers ............................................... 285 configuration ........................................................... 282 effects of a reset .................................................... 284 interrupts ................................................................. 284 operation ................................................................. 283 operation during sleep ........................................... 284 outputs .................................................................... 283 reference ................................................................ 283 external signal ................................................ 283 internal signal .................................................. 283 response time ........................................................ 283 comparator specifications ............................................... 396 comparator voltage reference ....................................... 287 accuracy and error .................................................. 288 associated registers ............................................... 289 configuring .............................................................. 287 connection considerations ...................................... 288 effects of a reset .................................................... 288 operation during sleep ........................................... 288 comparator voltage reference specifications ......................................... 396 compare (ccp module) .................................................. 182 associated registers ............................................... 183 ccprx registers ..................................................... 182 pin configuration ..................................................... 182 software interrupt .................................................... 182 special event trigger .............................................. 182 timer1/timer3 mode selection ................................ 182 compare (ccp modules) special event trigger .............................................. 175 compare (eccp module) ................................................ 192 special event trigger .............................................. 192 compare (eccp2 module) special event trigger .............................................. 280 computed goto ............................................................... 68 configuration bits ............................................................ 297 configuration register protection .................................... 320 context saving during interrupts ..................................... 134 conversion considerations .............................................. 428 cpfseq .......................................................................... 338 cpfsgt .......................................................................... 339 cpfslt ........................................................................... 339 crystal oscillator/cerami c resonator ................................ 31 d data addressing modes .................................................... 81 comparing addressing modes with the extended instruction set enabled ............... 84 direct ......................................................................... 81 indexed literal offset ................................................ 83 instructions affected .......................................... 83 indirect ....................................................................... 81 inherent and literal .................................................... 81 data eeprom code protection ....................................................... 320
? 2004 microchip technology inc. preliminary ds39646b-page 433 pic18f8722 family data eeprom memory ................................................... 111 associated registers ............................................... 115 eeadr and eeadrh registers ............................. 111 eecon1 and eecon2 registers ........................... 111 operation during code-protect ............................... 114 protection against spurious write ........................... 114 reading .................................................................... 113 using ........................................................................ 114 write verify .............................................................. 113 writing ...................................................................... 113 data memory ..................................................................... 72 access bank .............................................................. 74 and the extended instruction set ............................... 83 bank select register (bsr) ....................................... 72 general purpose registers ........................................ 74 map for pic18f8722 family ...................................... 73 special function registers ........................................ 75 daw ................................................................................. 340 dc and ac characteristics graphs and tables .................................................. 421 dc characteristics ........................................................... 393 power-down and supply current ............................ 381 supply voltage ......................................................... 380 dcfsnz .......................................................................... 341 decf ............................................................................... 340 decfsz ........................................................................... 341 demonstration boards picdem 1 ................................................................ 374 picdem 17 .............................................................. 375 picdem 18r ........................................................... 375 picdem 2 plus ........................................................ 374 picdem 3 ................................................................ 374 picdem 4 ................................................................ 374 picdem lin ............................................................ 375 picdem usb ........................................................... 375 picdem.net internet/ethernet ................................. 374 development support ...................................................... 371 device differences ........................................................... 427 device overview .................................................................. 7 details on individual family members ......................... 9 features (table) ...................................................... 9, 10 new core features ...................................................... 7 device reset timers .......................................................... 53 oscillator start-up timer (ost) ................................. 53 pll lock time-out ..................................................... 53 power-up timer (pwrt) ........................................... 53 time-out sequence .................................................... 53 direct addressing ............................................................... 82 e eccp capture and compare modes .................................. 192 standard pwm mode ............................................... 192 effect on standard pic instructions ................................. 368 effects of power-managed modes on various clock sources ............................................... 40 electrical characteristics .................................................. 377 enhanced capture/compare/pwm (eccp) .................... 187 and program memory modes .................................. 188 capture mode. see capture (eccp module). outputs and configuration ....................................... 188 pin configurations for eccp1 ................................. 189 pin configurations for eccp2 ................................. 190 pin configurations for eccp3 ................................. 191 pwm mode. see pwm (eccp module). timer resources ...................................................... 192 enhanced pwm mode. see pwm (eccp module). ....... 192 enhanced universal synchronous asynchronous receiver transmitter (eusart). see eusart. equations a/d acquisition time ............................................... 276 a/d minimum charging time .................................. 276 a/d, calculating the minimum required acquisition time ............................... 276 errata ................................................................................... 5 eusart asynchronous mode ................................................ 257 12-bit break transmit and receive ................. 263 associated registers, receive ........................ 261 associated registers, transmit ....................... 259 auto-wake-up on sync break ......................... 262 receiver .......................................................... 260 setting up 9-bit mode with address detect ........................................ 260 transmitter ...................................................... 257 baud rate generator operation in power-managed modes ...................................................... 251 baud rate generator (brg) ................................... 251 associated registers ....................................... 252 auto-baud rate detect .................................... 255 baud rate error, calculating ........................... 252 baud rates, asynchronous modes ................. 253 high baud rate select (brgh bit) ................. 251 sampling ......................................................... 251 synchronous master mode ...................................... 264 associated registers, receive ........................ 267 associated registers, transmit ....................... 265 reception ........................................................ 266 transmission ................................................... 264 synchronous slave mode ........................................ 268 associated registers, receive ........................ 269 associated registers, transmit ....................... 268 reception ........................................................ 269 transmission ................................................... 268 evaluation and programming tools ................................. 375 extended instruction set addfsr .................................................................. 364 addulnk ............................................................... 364 callw .................................................................... 365 movsf .................................................................... 365 movss .................................................................... 366 pushl ..................................................................... 366 subfsr .................................................................. 367 subulnk ................................................................ 367 extended microcontroller mode ....................................... 100 external clock input ........................................................... 32 external memory bus ........................................................ 97 16-bit byte select mode .......................................... 103 16-bit byte write mode ............................................ 101 16-bit data width modes ......................................... 100 16-bit mode timing ................................................. 104 16-bit word write mode .......................................... 102 8-bit data width modes ........................................... 106 8-bit mode timing ................................................... 107 i/o port functions ...................................................... 97 operation in power-managed modes .............................................................. 109
pic18f8722 family ds39646b-page 434 preliminary ? 2004 microchip technology inc. f fail-safe clock monitor ............................................ 297, 315 exiting operation ..................................................... 315 interrupts in power-managed modes ....................... 316 por or wake from sleep ........................................ 316 wdt during oscillator failure ................................. 315 fast register stack ............................................................ 68 firmware instructions ....................................................... 321 flash program memory ...................................................... 87 associated registers ................................................. 95 control registers ....................................................... 88 eecon1 and eecon2 ..................................... 88 tablat (table latch) register ......................... 90 tblptr (table pointer) register ...................... 90 erase sequence ........................................................ 92 erasing ....................................................................... 92 operation during code-protect ................................. 95 reading ...................................................................... 91 table pointer boundaries based on operation ........................ 90 table pointer boundaries .......................................... 90 table reads and table writes .................................. 87 write sequence ......................................................... 93 writing to ................................................................... 93 protection against spurious writes ................... 95 unexpected termination .................................... 95 write verify ........................................................ 95 fscm. see fail-safe clock monitor. g general call address support ......................................... 229 goto ............................................................................... 342 h hardware multiplier .......................................................... 117 introduction .............................................................. 117 operation ................................................................. 117 performance comparison ........................................ 117 high/low-voltage detect ................................................. 291 applications .............................................................. 294 associated registers ............................................... 295 characteristics ......................................................... 397 current consumption ............................................... 293 effects of a reset ..................................................... 295 operation ................................................................. 292 during sleep .................................................... 295 setup ........................................................................ 293 start-up time ........................................................... 293 typical application ................................................... 294 hlvd. see high/low-voltage detect. i i/o ports ........................................................................... 135 i 2 c mode (mssp) acknowledge sequence timing ............................... 239 associated registers ............................................... 245 baud rate generator ............................................... 232 bus collision during a repeated start condition .................. 243 during a stop condition ................................... 244 clock arbitration ....................................................... 233 clock stretching ....................................................... 225 10-bit slave receive mode (sen = 1) ............ 225 10-bit slave transmit mode ............................ 225 7-bit slave receive mode (sen = 1) .............. 225 7-bit slave transmit mode .............................. 225 clock synchronization and the ckp bit ................... 226 effects of a reset .................................................... 240 general call address support ................................. 229 i 2 c clock rate w/brg ............................................. 232 master mode ............................................................ 230 operation ......................................................... 231 reception ........................................................ 236 repeated start condition timing .................... 235 start condition timing ..................................... 234 transmission ................................................... 236 multi-master communication, bus collision and arbitration ................................................. 240 multi-master mode ................................................... 240 operation ................................................................. 219 read/write bit information (r/w bit) ............... 219, 220 registers ................................................................. 215 serial clock (rc3/sckx/sclx) ............................... 220 slave mode .............................................................. 219 addressing ....................................................... 219 reception ........................................................ 220 transmission ................................................... 220 sleep operation ....................................................... 240 stop condition timing ............................................. 239 id locations ............................................................. 297, 320 incf ................................................................................ 342 incfsz ............................................................................ 343 in-circuit debugger .......................................................... 320 in-circuit serial programming (icsp) ...................... 297, 320 indexed literal offset addressing and standard pic18 instructions ............................. 368 indexed literal offset mode ............................................. 368 indirect addressing ............................................................ 82 infsnz ............................................................................ 343 initialization conditions for all registers ...................... 57?61 instruction cycle ................................................................ 69 clocking scheme ....................................................... 69 instruction flow/pipelining ................................................. 69 instruction set .................................................................. 321 addlw .................................................................... 327 addwf .................................................................... 327 addwf (indexed literal offset mode) .................... 369 addwfc ................................................................. 328 andlw .................................................................... 328 andwf .................................................................... 329 bc ............................................................................ 329 bcf ......................................................................... 330 bn ............................................................................ 330 bnc ......................................................................... 331 bnn ......................................................................... 331 bnov ...................................................................... 332 bnz ......................................................................... 332 bov ......................................................................... 335 bra ......................................................................... 333 bsf .......................................................................... 333 bsf (indexed literal offset mode) .......................... 369 btfsc ..................................................................... 334
? 2004 microchip technology inc. preliminary ds39646b-page 435 pic18f8722 family btfss ..................................................................... 334 btg .......................................................................... 335 bz ............................................................................ 336 call ........................................................................ 336 clrf ........................................................................ 337 clrwdt .................................................................. 337 comf ...................................................................... 338 cpfseq .................................................................. 338 cpfsgt .................................................................. 339 cpfslt ................................................................... 339 daw ......................................................................... 340 dcfsnz .................................................................. 341 decf ....................................................................... 340 decfsz ................................................................... 341 extended instructions .............................................. 363 considerations when enabling ........................ 368 syntax .............................................................. 363 use with mplab ide tools ............................. 370 general format ........................................................ 323 goto ...................................................................... 342 incf ......................................................................... 342 incfsz .................................................................... 343 infsnz .................................................................... 343 iorlw ..................................................................... 344 iorwf ..................................................................... 344 lfsr ........................................................................ 345 movf ....................................................................... 345 movff .................................................................... 346 movlb .................................................................... 346 movlw ................................................................... 347 movwf ................................................................... 347 mullw .................................................................... 348 mulwf .................................................................... 348 negf ....................................................................... 349 nop ......................................................................... 349 pop ......................................................................... 350 push ....................................................................... 350 rcall ..................................................................... 351 reset ..................................................................... 351 retfie .................................................................... 352 retlw .................................................................... 352 return .................................................................. 353 rlcf ........................................................................ 353 rlncf ..................................................................... 354 rrcf ....................................................................... 354 rrncf ................................ .................................... 355 setf ........................................................................ 355 setf (indexed literal offset mode) ........................ 369 sleep ..................................................................... 356 standard instructions ............................................... 321 subfwb .................................................................. 356 sublw .................................................................... 357 subwf .................................................................... 357 subwfb .................................................................. 358 swapf .................................................................... 358 tblrd ..................................................................... 359 tblwt ..................................................................... 360 tstfsz ................................................................... 361 xorlw .................................................................... 361 xorwf .................................................................... 362 intcon register rbif bit .................................................................... 137 intcon registers ........................................................... 121 inter-integrated circuit. see i 2 c. internal oscillator block ..................................................... 34 adjustment ................................................................. 34 intio modes ............................................................. 34 intosc frequency drift ........................................... 35 intosc output frequency ....................................... 34 osctune register ................................................... 34 pll in intosc modes .............................................. 35 internal rc oscillator use with wdt .......................................................... 312 interrupt sources ............................................................. 297 a/d conversion complete ....................................... 275 capture complete (ccp) ........................................ 181 compare complete (ccp) ...................................... 182 interrupt-on-change (rb7:rb4) .............................. 137 intn pin ................................................................... 134 portb, interrupt-on-change .................................. 134 tmr0 ....................................................................... 134 tmr0 overflow ........................................................ 163 tmr1 overflow ........................................................ 165 tmr2 to pr2 match (pwm) ............................ 184, 192 tmr3 overflow ................................................ 173, 175 tmr4 to pr4 match ................................................ 178 tmr4 to pr4 match (pwm) .................................... 177 interrupts ......................................................................... 119 interrupts, flag bits interrupt-on-change (rb7:rb4) flag (rbif bit) ................................................. 137 intosc, intrc. see internal oscillator block. iorlw ............................................................................. 344 iorwf ............................................................................. 344 ipr registers ................................................................... 130 k key features easy migration ............................................................. 8 expanded memory ...................................................... 7 external memory interface .......................................... 8 l lfsr ............................................................................... 345 low-voltage icsp programming. see single-supply icsp programming. m master clear (mclr ) ......................................................... 51 master synchronous serial port (mssp). see mssp. memory mode memory access ............................................... 64 memory maps for pic18f8722 family program memory modes ........................................... 65 memory organization ........................................................ 63 data memory ............................................................. 72 program memory ....................................................... 63 modes ................................................................ 63 memory programming requirements .............................. 395 microcontroller mode ....................................................... 100 microprocessor mode ...................................................... 100 microprocessor with boot block mode ............................. 100 migration from baseline to enhanced devices ................................................... 428 migration from high-end to enhanced devices ................................................... 429 migration from mid-range to enhanced devices ................................................... 429
pic18f8722 family ds39646b-page 436 preliminary ? 2004 microchip technology inc. movf ............................................................................... 345 movff ............................................................................. 346 movlb ............................................................................. 346 movlw ............................................................................ 347 movsf ............................................................................ 365 movss ............................................................................ 366 movwf ........................................................................... 347 mplab asm30 assembler, linker, librarian .................. 372 mplab icd 2 in-circuit debugger ................................... 373 mplab ice 2000 high-performance universal in-circuit emulator ................................... 373 mplab ice 4000 high-performance universal in-circuit emulator ................................... 373 mplab integrated development environment software .............................................. 371 mplab pm3 device programmer .................................... 373 mplink object linker/mplib object librarian ............... 372 mssp ack pulse ........................................................ 219, 220 control registers (general) ...................................... 205 i 2 c mode. see i 2 c mode. module overview ..................................................... 205 spi master/slave connection .................................. 209 tmr4 output for clock shift .................................... 178 mullw ............................................................................ 348 mulwf ............................................................................ 348 n negf ............................................................................... 349 nop ................................................................................. 349 o opcode field descriptions ............................................... 322 oscillator configuration ...................................................... 31 ec .............................................................................. 31 ecio .......................................................................... 31 hs .............................................................................. 31 hspll ........................................................................ 31 internal oscillator block ............................................. 34 intio1 ....................................................................... 31 intio2 ....................................................................... 31 lp ............................................................................... 31 rc .............................................................................. 31 rcio .......................................................................... 31 xt .............................................................................. 31 oscillator selection .......................................................... 297 oscillator start-up timer (ost) ................................... 40, 53 oscillator switching ............................................................ 37 oscillator transitions .......................................................... 38 oscillator, timer1 ..................................................... 165, 175 oscillator, timer3 ............................................................. 173 p packaging ........................................................................ 423 details ...................................................................... 424 marking .................................................................... 423 parallel slave port (psp) ................................................. 158 associated registers ............................................... 160 re0/rd pin .............................................................. 158 re1/wr pin ............................................................. 158 re2/cs pin .............................................................. 158 select (pspmode bit) ............................................ 158 pickit 1 flash starter kit .................................................. 375 picstart plus development programmer .................... 374 pie registers ................................................................... 127 pin functions av dd .......................................................................... 30 av dd .......................................................................... 20 av ss .......................................................................... 30 av ss .......................................................................... 20 osc1/clki/ra7 .................................................. 13, 21 osc2/clko/ra6 ................................................ 13, 21 ra0/an0 .............................................................. 14, 22 ra1/an1 .............................................................. 14, 22 ra2/an2/v ref - ................................................... 14, 22 ra3/an3/v ref + .................................................. 14, 22 ra4/t0cki .......................................................... 14, 22 ra5/an4/hlvdin ................................................ 14, 22 rb0/int0/flt0 .................................................... 15, 23 rb1/int1 ............................................................. 15, 23 rb2/int2 ............................................................. 15, 23 rb3/int3 ................................................................... 15 rb3/int3/eccp2/p2a .............................................. 23 rb4/kbi0 ............................................................. 15, 23 rb5/kbi1/pgm .................................................... 15, 23 rb6/kbi2/pgc .................................................... 15, 23 rb7/kbi3/pgd .................................................... 15, 23 rc0/t1oso/t13cki ........................................... 16, 24 rc1/t1osi/eccp2/p2a ..................................... 16, 24 rc2/eccp1/p1a ................................................. 16, 24 rc3/sck1/scl1 ................................................. 16, 24 rc4/sdi1/sda1 .................................................. 16, 24 rc5/sdo1 ........................................................... 16, 24 rc6/tx1/ck1 ...................................................... 16, 24 rc7/rx1/dt1 ...................................................... 16, 24 rd0/ad0/psp0 ......................................................... 25 rd0/psp0 ................................................................. 17 rd1/ad1/psp1 ......................................................... 25 rd1/psp1 ................................................................. 17 rd2/ad2/psp2 ......................................................... 25 rd2/psp2 ................................................................. 17 rd3/ad3/psp3 ......................................................... 25 rd3/psp3 ................................................................. 17 rd4/ad4/psp4/sdo2 ............................................... 25 rd4/psp4/sdo2 ....................................................... 17 rd5/ad5/psp5/sdi2/sda2 ...................................... 25 rd5/psp5/sdi2/sda2 .............................................. 17 rd6/ad6/psp6/sck2/scl2 ..................................... 25 rd6/psp6/sck2/scl2 ............................................. 17 rd7/ad7/psp7/ss2 .................................................. 25 rd7/psp7/ss2 ......................................................... 17 re0/ad8/rd /p2d ...................................................... 26 re0/rd /p2d .............................................................. 18 re1/ad9/wr /p2c ..................................................... 26 re1/wr /p2c ............................................................. 18 re2/ad10/cs /p2b .................................................... 26 re2/cs /p2d .............................................................. 18 re3/ad11/p3c .......................................................... 26 re3/p3c .................................................................... 18 re4/ad12/p3b .......................................................... 26 re4/p3b .................................................................... 18 re5/ad13/p1c .......................................................... 26 re5/p1c .................................................................... 18 re6/ad14/p1b .......................................................... 26 re6/p1b .................................................................... 18 re7/ad15/eccp2/p2a ............................................. 26 re7/eccp2/p2a ....................................................... 18 rf0/an5 .............................................................. 19, 27 rf1/an6/c2out ................................................. 19, 27 rf2/an7/c1out ................................................. 19, 27
? 2004 microchip technology inc. preliminary ds39646b-page 437 pic18f8722 family rf3/an8 .............................................................. 19, 27 rf4/an9 .............................................................. 19, 27 rf5/an10/cv ref ................................................ 19, 27 rf6/an11 ............................................................ 19, 27 rf7/ss1 .............................................................. 19, 27 rg0/eccp3/p3a ................................................. 20, 28 rg1/tx2/ck2 ...................................................... 20, 28 rg2/rx2/dt2 ...................................................... 20, 28 rg3/ccp4/p3d ................................................... 20, 28 rg4/ccp5/p1d ................................................... 20, 28 rg5 ...................................................................... 20, 28 rg5/mclr /v pp ................................................... 13, 21 rh0/a16 .................................................................... 29 rh1/a17 .................................................................... 29 rh2/a18 .................................................................... 29 rh3/a19 .................................................................... 29 rh4/an12/p3c .......................................................... 29 rh5/an13/p3b .......................................................... 29 rh6/an14/p1c .......................................................... 29 rh7/an15/p1b .......................................................... 29 rj0/ale ..................................................................... 30 rj1/oe ...................................................................... 30 rj2/wrl .................................................................... 30 rj3/wrh ................................................................... 30 rj4/ba0 ..................................................................... 30 rj5/ce ....................................................................... 30 rj6/lb ....................................................................... 30 rj7/ub ....................................................................... 30 v dd ............................................................................ 30 v dd ............................................................................ 20 v ss ............................................................................. 30 v ss ............................................................................. 20 pinout i/o descriptions pic18f6527/6622/6627/6722 .................................... 13 pic18f8527/8622/8627/8722 .................................... 21 pir registers ................................................................... 124 pll frequency multiplier ................................................... 33 hspll oscillator mode .............................................. 33 use with intosc ....................................................... 33 pop ................................................................................. 350 por. see power-on reset. porta associated registers ............................................... 136 functions ................................................................. 136 lata register .......................................................... 135 porta register ...................................................... 135 trisa register ........................................................ 135 portb associated registers ............................................... 139 functions ................................................................. 138 latb register .......................................................... 137 portb register ...................................................... 137 rb7:rb4 interrupt-on-change flag (rbif bit) ................................................. 137 trisb register ........................................................ 137 portc associated registers ............................................... 142 functions ................................................................. 141 latc register ......................................................... 140 portc register ...................................................... 140 rc3/sckx/sclx pin ................................................ 220 trisc register ........................................................ 140 portd ............................................................................ 158 associated registers ............................................... 145 functions ................................................................. 144 latd register ......................................................... 143 portd register ...................................................... 143 trisd register ....................................................... 143 porte analog port pins ...................................................... 158 associated registers ............................................... 148 functions ................................................................. 147 late register ......................................................... 146 porte register ...................................................... 146 psp mode select (pspmode bit) .......................... 158 re0/rd pin ............................................................. 158 re1/wr pin ............................................................ 158 re2/cs pin ............................................................. 158 trise register ........................................................ 146 portf associated registers ............................................... 150 functions ................................................................. 150 latf register ......................................................... 149 portf register ...................................................... 149 trisf register ........................................................ 149 portg associated registers ............................................... 153 functions ................................................................. 152 latg register ......................................................... 151 portg register ..................................................... 151 trisg register ....................................................... 151 porth associated registers ............................................... 155 functions ................................................................. 155 lath register ......................................................... 154 porth register ...................................................... 154 trish register ....................................................... 154 portj associated registers ............................................... 157 functions ................................................................. 157 latj register .......................................................... 156 portj register ...................................................... 156 trisj register ........................................................ 156 power-managed modes ..................................................... 41 and a/d operation ................................................... 278 and eusart operation .......................................... 251 and multiple sleep commands .................................. 42 and pwm operation ................................................ 203 and spi operation ................................................... 213 associated registers ............................................... 109 clock transitions and status indicators .................... 42 effects on clock sources .......................................... 40 entering ..................................................................... 41 exiting idle and sleep modes .................................... 47 by interrupt ........................................................ 47 by reset ............................................................ 47 by wdt time-out .............................................. 47 without a start-up delay ................................... 48 idle modes ................................................................. 45 pri_idle .......................................................... 46 rc_idle ........................................................... 47 sec_idle ......................................................... 46
pic18f8722 family ds39646b-page 438 preliminary ? 2004 microchip technology inc. run modes ................................................................. 42 pri_run ........................................................... 42 rc_run ............................................................ 43 sec_run .......................................................... 42 selecting .................................................................... 41 sleep mode ................................................................ 45 summary (table) ........................................................ 41 power-on reset (por) ...................................................... 51 power-up timer (pwrt) ........................................... 53 time-out sequence .................................................... 53 power-up delays ................................................................ 40 power-up timer (pwrt) .................................................... 40 prescaler timer2 ...................................................................... 193 prescaler, timer0 ............................................................. 163 prescaler, timer2 ............................................................. 185 pri_idle mode ................................................................. 46 pri_run mode ................................................................. 42 pro mate ii universal device programmer .................. 373 program counter ................................................................ 66 pcl, pch and pcu registers ................................... 66 pclath and pclatu registers .............................. 66 program memory and extended instruction set ..................................... 85 code protection ....................................................... 318 extended microcontroller mode ................................. 63 instructions ................................................................. 70 two-word .......................................................... 71 interrupt vector .......................................................... 63 look-up tables .......................................................... 68 map and stack (diagram) ........................................... 64 microcontroller mode ................................................. 63 microprocessor mode ................................................ 63 microprocessor with boot block mode ....................... 63 reset vector .............................................................. 63 program verification and code protection ....................... 317 associated registers ............................................... 318 programming, device instructions ................................... 321 psp. see parallel slave port. pulse-width modulation. see pwm (ccp module) and pwm (eccp module). push ............................................................................... 350 push and pop instructions .............................................. 67 pushl ............................................................................. 366 pwm (ccp module) associated registers ............................................... 186 duty cycle ................................................................ 184 example frequencies/resolutions .......................... 185 period ....................................................................... 184 setup for pwm operation ........................................ 185 tmr2 to pr2 match ................................................ 184 tmr4 to pr4 match ................................................ 177 pwm (eccp module) ...................................................... 192 associated registers ............................................... 204 ccpr1h:ccpr1l registers ................................... 192 direction change in full-bridge output mode .................................................... 198 duty cycle ................................................................ 193 effects of a reset ..................................................... 203 enhanced pwm auto-shutdown ............................. 200 example frequencies/resolutions .......................... 193 full-bridge application example .............................. 198 full-bridge mode ...................................................... 197 half-bridge mode ..................................................... 196 half-bridge output mode applications example ...................................... 196 operation in power-managed modes ...................... 203 operation with fail-safe clock monitor ................... 203 output configurations .............................................. 194 output relationships (active-high) .......................... 194 output relationships (active-low) .......................... 195 period ...................................................................... 192 programmable dead-band delay ............................ 200 setup for pwm operation ........................................ 203 start-up considerations ........................................... 202 tmr2 to pr2 match ................................................ 192 q q clock .................................................................... 185, 193 r ram. see data memory. rc oscillator ...................................................................... 33 rcio oscillator mode ................................................ 33 rc_idle mode .................................................................. 47 rc_run mode .................................................................. 43 rcall ............................................................................. 351 rcon register bit status during initialization .................................... 56 register file ....................................................................... 74 registers adcon0 (a/d control 0) ......................................... 271 adcon1 (a/d control 1) ......................................... 272 adcon2 (a/d control 2) ......................................... 273 baudconx (baud rate control) ............................ 250 ccpxcon (capture/compare/pwm control) ................... 179 ccpxcon (enhanced capture/compare/pwm control) .................... 187 cmcon (comparator control) ................................ 281 config1h (configuration 1 high) .......................... 299 config2h (configuration 2 high) .......................... 301 config2l (configuration 2 low) ........................... 300 config3h (configuration 3 high) .......................... 303 config3l (configuration 3 low) ........................... 302 config4l (configuration 4 low) ........................... 304 config5h (configuration 5 high) .......................... 306 config5l (configuration 5 low) ........................... 305 config6h (configuration 6 high) .......................... 308 config6l (configuration 6 low) ........................... 307 config7h (configuration 7 high) .......................... 310 config7l (configuration 7 low) ........................... 309 cvrcon (comparator voltage reference control) .......................................... 287 devid1 (device id 1) .............................................. 311 devid2 (device id 2) .............................................. 311 eccpxas (eccp auto-shutdown control) .................................. 201 eccpxdel (enhanced pwm configuration) ........................................ 200 eecon1 (data eeprom control 1) ....................... 112 eecon1 (eeprom control 1) ................................. 89 hlvdcon (high/low-voltage detect control) ................................................ 291 intcon (interrupt control) ...................................... 121 intcon2 (interrupt control 2) ................................. 122 intcon3 (interrupt control 3) ................................. 123 ipr1 (peripheral interrupt priority 1) ....................... 130
? 2004 microchip technology inc. preliminary ds39646b-page 439 pic18f8722 family ipr2 (peripheral interrupt priority 2) ........................ 131 ipr3 (peripheral interrupt priority 3) ........................ 132 memcon (external memory bus control) ....................................................... 98 osccon (oscillator control) .................................... 39 osctune (oscillator tuning) ................................... 35 pie1 (peripheral interrupt enable 1) ........................ 127 pie2 (peripheral interrupt enable 2) ........................ 128 pie3 (peripheral interrupt enable 3) ........................ 129 pir1 (peripheral interrupt request (flag) 1) ............................................. 124 pir2 (peripheral interrupt request (flag) 2) ............................................. 125 pir3 (peripheral interrupt request (flag) 3) ............................................. 126 pspcon (parallel slave port control) .................................................... 159 rcon (reset control) ....................................... 50, 133 rcstax (receive status and control) .................... 249 sspxcon1 (msspx control 1, i 2 c mode) ........................................................ 217 sspxcon1 (msspx control 1, spi mode) ........................................................ 207 sspxcon2 (msspx control 2, i 2 c mode) ........................................................ 218 sspxstat (msspx status, i 2 c mode) ....................................................... 216 sspxstat (msspx status, spi mode) ........................................................ 206 status ..................................................................... 80 stkptr (stack pointer) ............................................ 67 t0con (timer0 control) .......................................... 161 t1con (timer1 control) .......................................... 165 t2con (timer2 control) .......................................... 171 t3con (timer3 control) .......................................... 173 t4con (timer 4 control) ......................................... 177 txstax (transmit status and control) ................... 248 wdtcon (watchdog timer control) ...................... 313 reset ............................................................................. 351 reset state of registers .................................................... 56 resets ........................................................................ 49, 297 brown-out reset (bor) ........................................... 297 oscillator start-up timer (ost) ............................... 297 power-on reset (por) ............................................ 297 power-up timer (pwrt) ......................................... 297 retfie ............................................................................ 352 retlw ............................................................................ 352 return .......................................................................... 353 return address stack ........................................................ 66 return stack pointer (stkptr) ........................................ 67 revision history ............................................................... 427 rlcf ................................................................................ 353 rlncf ............................................................................. 354 rrcf ............................................................................... 354 rrncf ........................ .................................................... 355 s sckx ................................................................................ 205 sdix ................................................................................. 205 sdox ............................................................................... 205 sec_idle mode ................................................................ 46 sec_run mode ................................................................ 42 serial clock, sckx ........................................................... 205 serial data in (sdix) ........................................................ 205 serial data out (sdox) ................................................... 205 serial peripheral interface. see spi mode. setf ............................................................................... 355 slave select (ssx ) ........................................................... 205 slave select synchronization .......................................... 211 sleep ............................................................................. 356 sleep osc1 and osc2 pin states ...................................... 40 sleep mode ....................................................................... 45 software simulator (mplab sim) ................................... 372 software simulator (mplab sim30) ....................................................... 372 special event trigger. see compare (ccp mode). special event trigger. see compare (eccp module). special features of the cpu ........................................... 297 special function registers ................................................ 75 map ............................................................................ 75 spi mode (mssp) ........................................................... 205 associated registers ............................................... 214 bus mode compatibility ........................................... 213 clock speed, interactions ........................................ 213 effects of a reset .................................................... 213 enabling spi i/o ...................................................... 209 master mode ............................................................ 210 master/slave connection ........................................ 209 operation ................................................................. 208 operation in power-managed modes .................................. 213 serial clock ............................................................. 205 serial data in ........................................................... 205 serial data out ........................................................ 205 slave mode .............................................................. 211 slave select ............................................................. 205 slave select synchronization .................................. 211 spi clock ................................................................. 210 sspxbuf register .................................................. 210 sspxsr register .................................................... 210 typical connection .................................................. 209 sspov ............................................................................ 236 sspov status flag ......................................................... 236 sspxstat register r/w bit ............................................................ 219, 220 ssx .................................................................................. 205 stack full/underflow resets .............................................. 68 subfsr .......................................................................... 367 subfwb ......................................................................... 356 sublw ............................................................................ 357 subulnk ........................................................................ 367 subwf ............................................................................ 357 subwfb ......................................................................... 358 swapf ............................................................................ 358 t table pointer operations (table) ........................................ 90 table reads/table writes ................................................. 68 tblrd ............................................................................. 359 tblwt ............................................................................ 360 time-out in various situations (table) ................................ 53
pic18f8722 family ds39646b-page 440 preliminary ? 2004 microchip technology inc. timer0 .............................................................................. 161 associated registers ............................................... 163 operation ................................................................. 162 overflow interrupt .................................................... 163 prescaler .................................................................. 163 prescaler assignment (psa bit) .............................. 163 prescaler select (t0ps2:t0ps0 bits) ..................... 163 prescaler. see prescaler, timer0. reads and writes in 16-bit mode ............................ 162 source edge select (t0se bit) ................................ 162 source select (t0cs bit) ......................................... 162 switching prescaler assignment .............................. 163 timer1 .............................................................................. 165 16-bit read/write mode ........................................... 167 associated registers ............................................... 169 interrupt .................................................................... 168 operation ................................................................. 166 oscillator .......................................................... 165, 167 layout considerations ..................................... 168 overflow interrupt .................................................... 165 resetting, using the ccp special event trigger ....................................... 168 special event trigger (eccp) ................................. 192 tmr1h register ...................................................... 165 tmr1l register ....................................................... 165 use as a real-time clock ....................................... 168 timer2 .............................................................................. 171 associated registers ............................................... 172 interrupt .................................................................... 172 operation ................................................................. 171 output ...................................................................... 172 pr2 register .................................................... 184, 192 tmr2 to pr2 match interrupt .......................... 184, 192 timer3 .............................................................................. 173 16-bit read/write mode ........................................... 175 associated registers ............................................... 175 operation ................................................................. 174 oscillator .......................................................... 173, 175 overflow interrupt ............................................ 173, 175 special event trigger (ccp) .................................... 175 tmr3h register ...................................................... 173 tmr3l register ....................................................... 173 timer4 .............................................................................. 177 associated registers ............................................... 178 mssp clock shift ..................................................... 178 operation ................................................................. 177 postscaler. see postscaler, timer4. pr4 register ............................................................ 177 prescaler. see prescaler, timer4. tmr4 register ......................................................... 177 tmr4 to pr4 match interrupt .......................... 177, 178 timing diagrams a/d conversion ........................................................ 418 asynchronous reception ......................................... 261 asynchronous transmission .................................... 258 asynchronous transmission (back to back) .................................................. 258 automatic baud rate calculation ............................ 256 auto-wake-up bit (wue) during normal operation ............................................. 262 auto-wake-up bit (wue) during sleep ................... 262 baud rate generator with clock arbitration ............................................... 233 brg overflow sequence ......................................... 256 brg reset due to sdax arbitration during start condition ...................................... 242 brown-out reset (bor) ........................................... 405 bus collision during a repeated start condition (case 1) .................................. 243 bus collision during a repeated start condition (case 2) .................................. 243 bus collision during a start condition (sclx = 0) ....................................................... 242 bus collision during a stop condition (case 1) ........................................................... 244 bus collision during a stop condition (case 2) ........................................................... 244 bus collision during start condition (sdax only) ..................................................... 241 bus collision for transmit and acknowledge ................................................... 240 capture/compare/pwm (all eccp/ccp modules) ................................ 407 clko and i/o .......................................................... 402 clock synchronization ............................................. 226 clock/instruction cycle .............................................. 69 eusart synchronous receive (master/slave) ................................................. 417 eusart synchronous transmission (master/slave) ................................................. 417 example spi master mode (cke = 0) ..................... 409 example spi master mode (cke = 1) ..................... 410 example spi slave mode (cke = 0) ....................... 411 example spi slave mode (cke = 1) ....................... 412 external clock (all modes except pll) ................... 400 external memory bus for sleep (microprocessor mode) ............................ 105, 108 external memory bus for tblrd (extended microcontroller mode) ............ 104, 107 external memory bus for tblrd (microprocessor mode) .................................... 107 external memory bus for tblrd with 1 t cy wait state (microprocessor mode) .................. 104 fail-safe clock monitor (fscm) .............................. 316 first start bit timing ................................................ 234 full-bridge pwm output .......................................... 197 half-bridge pwm output ......................................... 196 high/low-voltage detect characteristics ................ 397 high-voltage detect operation (vdirmag = 1) ............................................... 294 i 2 c acknowledge sequence .................................... 239 i 2 c bus data ............................................................ 413 i 2 c bus start/stop bits ............................................ 413 i 2 c master mode (7 or 10-bit transmission) ........................................ 237 i 2 c master mode (7-bit reception) .......................... 238 i 2 c slave mode (10-bit reception, sen = 0) .......................................................... 223 i 2 c slave mode (10-bit reception, sen = 1) .......................................................... 228 i 2 c slave mode (10-bit transmission) .................... 224 i 2 c slave mode (7-bit reception, sen = 0) ............ 221 i 2 c slave mode (7-bit reception, sen = 1) ............ 227 i 2 c slave mode (7-bit transmission) ...................... 222 i 2 c slave mode general call address sequence (7 or 10-bit addr ess mode) ............ 229 i 2 c stop condition receive or transmit mode ................................................. 239 low-voltage detect operation (vdirmag = 0) ............................................... 293 master ssp i 2 c bus data ........................................ 415 master ssp i 2 c bus start/stop bits ........................ 415
? 2004 microchip technology inc. preliminary ds39646b-page 441 pic18f8722 family parallel slave port (pic18f8527/8622/8627/8722) ....................... 408 parallel slave port (psp) read ............................... 160 parallel slave port (psp) write ............................... 160 program memory read ............................................ 403 program memory write ............................................ 404 pwm auto-shutdown (p1rsen = 0, auto-restart disabled) .................................... 202 pwm auto-shutdown (p1rsen = 1, auto-restart enabled) ..................................... 202 pwm direction change ........................................... 199 pwm direction change at near 100% duty cycle .................................... 199 pwm output ............................................................ 184 repeated start condition ......................................... 235 reset, watchdog timer (wdt), oscillator start-up timer (ost) and power-up timer (pwrt) ................................. 405 send break character sequence ............................ 263 slave synchronization ............................................. 211 slow rise time (mclr tied to v dd , v dd rise > t pwrt ) ............................................ 55 spi mode (master mode) ......................................... 210 spi mode (slave mode, cke = 0) ........................... 212 spi mode (slave mode, cke = 1) ........................... 212 synchronous reception (master mode, sren) ..................................... 266 synchronous transmission ...................................... 264 synchronous transmission (through txen) .............................................. 265 time-out sequence on por w/pll enabled (mclr tied to v dd ) ............................. 55 time-out sequence on power-up (mclr not tied to v dd , case 1) ....................... 54 time-out sequence on power-up (mclr not tied to v dd , case 2) ....................... 54 time-out sequence on power-up (mclr tied to v dd , v dd rise < t pwrt ) ........................ 54 timer0 and timer1 external clock .......................... 406 transition for entry to idle mode ................................ 46 transition for entry to sec_run mode .................... 43 transition for entry to sleep mode ............................ 45 transition for two-speed start-up (intosc to hspll) ........................................ 314 transition for wake from idle to run mode ............... 46 transition for wake from sleep (hspll) ................... 45 transition from rc_run mode to pri_run mode ................................................. 44 transition from sec_run mode to pri_run mode (hspll) .................................. 43 transition to rc_run mode ..................................... 44 typical opcode fetch, 8-bit mode ........................... 108 timing diagrams and specifications a/d conversion requirements ................................ 419 ac characteristics internal rc accuracy ....................................... 401 capture/compare/pwm requirements (all eccp/ccp modules) ................................ 407 clko and i/o requirements ........................... 402, 403 eusart synchronous receive requirements .................................................. 417 eusart synchronous transmission requirements .................................................. 417 example spi mode requirements (master mode, cke = 0) .................................. 409 example spi mode requirements (master mode, cke = 1) .................................. 410 example spi mode requirements (slave mode, cke = 0) .................................... 411 example spi slave mode requirements (cke = 1) ................................. 412 external clock requirements .................................. 400 i 2 c bus data requirements (slave mode) .............. 414 i 2 c bus start/stop bits requirements (slave mode) ................................................... 413 master ssp i 2 c bus data requirements ................ 416 master ssp i 2 c bus start/stop bits requirements .................................................. 415 parallel slave port requirements (pic18f8527/8622/8627/8722) ....................... 408 pll clock ................................................................ 401 program memory write requirements .................... 404 reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements ...................... 405 timer0 and timer1 external clock requirements ........................................ 406 top-of-stack access .......................................................... 66 trise register pspmode bit ......................................................... 158 tstfsz ........................................................................... 361 two-speed start-up ................................................. 297, 314 ieso (config1h<7>), internal/external oscillator switchover bit................................... 299 two-word instructions example cases ......................................................... 71 txstax register brgh bit ................................................................. 251 w watchdog timer (wdt) ........................................... 297, 312 associated registers ............................................... 313 control register ....................................................... 312 during oscillator failure .......................................... 315 programming considerations .................................. 312 wcol ...................................................... 234, 235, 236, 239 wcol status flag ................................... 234, 235, 236, 239 www, on-line support ................... ................................... 5 x xorlw ........................................................................... 361 xorwf ........................................................................... 362
pic18f8722 family ds39646b-page 442 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39646b-page 443 pic18f8722 family on-line support microchip provides on-line support on the microchip world wide web site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape ? or microsoft ? internet explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available at the following url: www.microchip.com the file transfer site is available by using an ftp service to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development systems, technical information and more listing of seminars and events systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive the most current upgrade kits. the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-792-7302 for the rest of the world. 042003
pic18f8722 family ds39646b-page 444 preliminary ? 2004 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds39646b pic18f6527/6622/6627/6722 pic18f8527/8622/8627/8722 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2004 microchip technology inc. preliminary ds39646b-page 445 pic18f8722 family pic18f8722 family product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device pic18f6527/6622/6627/6722 (1) , pic18f8527/8622/8627/8722 (1) , pic18f6527/6622/6627/6722t (2) , pic18f8527/8622/8627/8722t (2) ; v dd range 4.2v to 5.5v pic18lf6627/6722 (1) , pic18lf8627/8722 (1) , pic18lf6627/6722t (2) , pic18lf8627/8722t (2) ; v dd range 2.0v to 5.5v temperature range i= -40 c to +85 c (industrial) e= -40 c to +125 c (extended) package pt = tqfp (thin quad flatpack) pattern qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic18lf6622-i/pt 301 = industrial temp., tqfp package, extended v dd limits, qtp pattern #301. b) pic18lf6722-e/pt = extended temp., tqfp package, standard v dd limits. note 1: f = standard voltage range lf = wide voltage range 2: t = in tape and reel tqfp packages only.
ds39646b-page 446 preliminary ? 2004 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta alpharetta, ga tel: 770-640-0034 fax: 770-640-0307 boston westford, ma tel: 978-692-3848 fax: 978-692-3821 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 san jose mountain view, ca tel: 650-215-1444 fax: 650-961-0286 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8676-6200 fax: 86-28-8676-6599 china - fuzhou tel: 86-591-8750-3506 fax: 86-591-8750-3521 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - shunde tel: 86-757-2839-5507 fax: 86-757-2839-5571 china - qingdao tel: 86-532-502-7355 fax: 86-532-502-7205 asia/pacific india - bangalore tel: 91-80-2229-0061 fax: 91-80-2229-0062 india - new delhi tel: 91-11-5160-8631 fax: 91-11-5160-8632 japan - kanagawa tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 taiwan - hsinchu tel: 886-3-572-9526 fax: 886-3-572-6459 europe austria - weis tel: 43-7242-2244-399 fax: 43-7242-2244-393 denmark - ballerup tel: 45-4450-2828 fax: 45-4485-2829 france - massy tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - ismaning tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 england - berkshire tel: 44-118-921-5869 fax: 44-118-921-5820 worldwide sales and service 10/20/04

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